专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

51. 发明授权

EP2359487B1 FOLDING SEQUENTIAL ADAPTIVE EQUALIZER 有权转让
标题翻译： FALTENDER，SEQUENZIELLER UND ADAPTIVER ENTZERRER
公开(公告)号：EP2359487B1
公开(公告)日：2017-04-19
申请号：EP09827074.7
申请日：2009-11-17
申请人： Semtech Canada Corporation
发明人： SHAKIBA, Hossein , SHASHAANI , Mansour
IPC分类号： H04L25/03 , H04L27/08 , H03H21/00
CPC分类号： H03H21/0012 , H04L25/03885 , H04L27/08 , H04L2025/03363

52. 发明公开

EP2933970A4 MULTI-LEVEL DIFFERENTIAL DECODING DEVICE AND METHOD FOR QUADRATURE AMPLITUDE MODULATION COMMUNICATION SYSTEM 有权
标题翻译：多级差解码装置及方法QAM通信系统
公开(公告)号：EP2933970A4
公开(公告)日：2016-07-27
申请号：EP13862983
申请日：2013-11-18
申请人： MITSUBISHI ELECTRIC CORP
发明人： SUGIHARA TAKASHI , NISHIMOTO HIROSHI , YOSHIDA TSUYOSHI
IPC分类号： H04L27/38 , H03M13/45 , H04L27/00
CPC分类号： H04L1/0047 , H04L1/0045 , H04L1/0054 , H04L25/067 , H04L27/34 , H04L27/3845 , H04L2025/03363
摘要： Differential decoding processing applied to multilevel modulation is accomplished with the circuit scale kept small by including: an MSB coordinate rotating part for performing coordinate rotation based on information of the first two most significant bits of a signal received via a synchronous detection part; an MSB symbol likelihood generating part for generating likelihood with respect to the first two most significant bits after differential decoding, with the use of two sets of bit strings at different points in time for which coordinate rotation has been performed; an LSB symbol likelihood generating part for generating likelihood with respect to less significant bits; and a soft decision error correction decoding part for generating a decoded signal with the use of the likelihood of the first two most significant bits and the likelihood of the less significant bits.

53. 发明授权

EP0911967B1 Apparatus and method for equilizer filter units 有权
标题翻译：用于均衡滤波装置的方法和设备
公开(公告)号：EP0911967B1
公开(公告)日：2014-02-26
申请号：EP98308636.4
申请日：1998-10-22
申请人： Texas Instruments Incorporated
发明人： Gu, Richard X.
IPC分类号： H03H21/00
CPC分类号： H03H21/0012 , H04L25/03038 , H04L2025/03363 , H04L2025/03477 , H04L2025/03617

54. 发明公开

EP2586148A1 SOFT CANCELLATION OF INTER-LAYER INTERFERENCE WITHIN A MIMO CODEWORD 有权
标题翻译： SANFTEUNTERDRÜCKUNGVON ZWISCHENSCHICHTINTERFERENZEN BEI EINEM MIMO编码
公开(公告)号：EP2586148A1
公开(公告)日：2013-05-01
申请号：EP11738044.4
申请日：2011-06-20
申请人： Telefonaktiebolaget LM Ericsson (publ)
发明人： WANG, Yi-Pin, Eric
IPC分类号： H04L1/00 , H04L25/03 , H04B7/04
CPC分类号： H04L25/03057 , H04B7/0413 , H04L1/005 , H04L1/0066 , H04L1/208 , H04L25/067 , H04L2025/03363 , H04L2025/03426
摘要： A receiver for processing a received signal encoded with a codeword and mapped to two layers includes a plurality of equalizers for equalizing the received signal, a plurality of demodulators for demodulating a respective equalized signal, a decoder for decoding the demodulated signal by extracting soft bits from the demodulated signal, a modulator for modulating the decoded signal by generating soft symbols based on the extracted soft bits, a demapper for demapping the modulated signal to soft symbols corresponding to each of the two layers and a plurality of inter-layer interference cancellers for cancelling interference utilizing the demapped soft symbols wherein the demapped soft symbols are utilized also by the equalizers to reduce inter-symbol interference.
摘要翻译：用于处理用码字编码并映射到两层的接收信号的接收机包括用于均衡接收信号的多个均衡器，用于解调相应的均衡信号的多个解调器，用于通过提取软比特来解码解调信号的解码器解调信号，用于通过基于提取的软比特生成软符号来调制解码信号的调制器，用于将调制信号解映射到对应于两个层中的每一个的软符号的解映射器和用于消除的多个层间干扰消除器利用去映射的软符号的干扰，其中平滑器还利用去映射的软符号来减少符号间干扰。

55. 发明公开

EP2107746A3 High speed signaling system with adaptive transmit pre-emphasis, reflection cancellation and offset cancellation 有权转让
标题翻译：与反射的自适应预失真消除和抑制DC偏移的快速信令系统
公开(公告)号：EP2107746A3
公开(公告)日：2009-12-30
申请号：EP09165754.4
申请日：2004-12-16
申请人： Rambus Inc.
发明人： Stojanovis, Vladimir, M. , Ho, Andrew , Bessios, Anthony , Chen, Fred, F. , Alon, Elad , Horowitz, Mark, A. , Garlepp, Bruno, W.
IPC分类号： H04L25/49 , H04L25/02 , H04L25/06 , H04L25/03
CPC分类号： H04L25/49 , H04B1/04 , H04B1/0475 , H04B2001/0416 , H04L25/025 , H04L25/028 , H04L25/0282 , H04L25/03019 , H04L25/03343 , H04L25/03885 , H04L25/061 , H04L25/4917 , H04L2025/03363 , H04L2025/03802
摘要： A method of operation an integrated circuit device, the method comprising:
incrementally adjusting a plurality of drive strength values used to control signal levels generated by a corresponding plurality of output drivers (205) included within a transmit circuit (201) the adjusted plurality of drive strength values representing a first level of power consumption in the transmit circuit (201); determining whether the first level of power consumption exceeds a maximum level of power consumption in the transmit circuit (201); and reducing a predetermined one of the plurality of drive strength values if the first level of power consumption exceeds the maximum level of power consumption.

56. 发明授权

EP1195021B1 PHY CONTROL MODULE FOR A MULTI-PAIR GIGABIT TRANSCEIVER 有权
标题翻译： PHY控制模块与几双千兆收发器
公开(公告)号：EP1195021B1
公开(公告)日：2006-10-25
申请号：EP00926364.1
申请日：2000-04-24
申请人： Broadcom Corporation
发明人： AGAZZI, Oscar E.
IPC分类号： H04L12/00
CPC分类号： H04L7/0062 , G01R31/3008 , G01R31/31715 , G01R31/318594 , H04B3/23 , H04B3/32 , H04L1/0054 , H04L1/242 , H04L7/0334 , H04L25/03038 , H04L25/03057 , H04L25/03146 , H04L25/03267 , H04L25/067 , H04L25/14 , H04L25/4917 , H04L25/497 , H04L2025/03363 , H04L2025/03369 , H04L2025/0349 , H04L2025/03503 , H04L2025/03617
摘要： A method for controlling operation of a multi-pair gigabit transceiver. The multi-pair gigabit transceiver comprises a Physical Layer Control module (PHY Control), a Physical Coding Sublayer module (PCS) and a Digital Signal Processing module (DSP). The PHY Control receives user-defined inputs from the Serial Management module and status signals and diagnostics signals from the DSP and the PCS and generates control signals, responsive to the user-defined inputs, the status signals and diagnostics signals, to the DSP and the PCS.

57. 发明授权

EP1145515B1 TRELLIS DECODER WITH CORRECTION OF PAIR SWAPS, FOR USE IN GIGABIT ETHERNET TRANSCEIVERS 有权
标题翻译：有校正PAARTAUSCHUNGEN的TRELLISDEKODER，使用习惯在车站器/接收器千兆以太网
公开(公告)号：EP1145515B1
公开(公告)日：2005-09-14
申请号：EP00903365.5
申请日：2000-01-20
申请人： Broadcom Corporation
发明人： AGAZZI, Oscar E.
IPC分类号： H04L25/14 , H04L1/00 , H04L25/497 , H04L25/03
CPC分类号： H04L7/0062 , G01R31/3004 , G01R31/3008 , G01R31/3016 , G01R31/31715 , G01R31/318502 , G01R31/318552 , G01R31/318594 , H04B3/23 , H04B3/32 , H04L1/005 , H04L1/0054 , H04L1/0059 , H04L1/242 , H04L7/0334 , H04L25/03038 , H04L25/03057 , H04L25/03146 , H04L25/03267 , H04L25/03885 , H04L25/067 , H04L25/14 , H04L25/4917 , H04L25/497 , H04L2025/03363 , H04L2025/03369 , H04L2025/03477 , H04L2025/0349 , H04L2025/03496 , H04L2025/03503 , H04L2025/03617 , H04L2025/03745
摘要： A method and a system for compensating for a permutation of L pairs of cable such that the compensation is localized in a trellis decoder of a receiver. The L pairs of cable correspond to L dimensions of a trellis code associated with the trellis decoder. The trellis code includes a plurality of code-subsets. The permutation of the L pairs of cable is determined. A plurality of sets of swap indicators based on the permutation of the L pairs of cable is generated. Each of the sets of swap indicators corresponds to one of the code-subsets. The code-subsets are remapped based on the corresponding sets of swap indicators.

58. 发明授权

EP1118183B1 TIMING RECOVERY FOR A HIGH SPEED DIGITAL DATA COMMUNICATION SYSTEM BASED ON ADAPTIVE EQUALIZER IMPULSE RESPONSE CHARACTERISTICS 有权
标题翻译：中风恢复期对于高率数字通信系统自适应BERUHEHND ENTZERRERIMPULSANTWORTEIGENSCHAFTEN
公开(公告)号：EP1118183B1
公开(公告)日：2003-07-09
申请号：EP99948492.6
申请日：1999-09-28
申请人： Conexant Systems, Inc.
发明人： JONSSON, Ragnar , OLAFSSON, Sverrir , BJARNASON, Elias
IPC分类号： H04L7/02 , H04L25/49 , H04L25/03
CPC分类号： H04L7/0058 , H04L25/03019 , H04L25/4927 , H04L2025/03363 , H04L2025/03477 , H04L2025/0349

59. 发明公开

EP1203476A1 DETERMINISTIC DISTORTION INSENSITIVE ADAPTIVE RECEIVER USING DECISION UPDATING 审中-公开
标题翻译：应用Decision UPDATE确定性畸变敏感适应接收机
公开(公告)号：EP1203476A1
公开(公告)日：2002-05-08
申请号：EP00950394.7
申请日：2000-07-17
申请人： Altocom Inc.
发明人： GONIKBERG, Mark
IPC分类号： H04L25/49 , H04L25/03
CPC分类号： H04L25/063 , H04J3/125 , H04L25/03012 , H04L25/4927 , H04L2025/03363 , H04L2025/03445
摘要： A technique has been developed whereby an adaptive receiver (e.g., 500) may employ decision updating in a manner insensitive to RBS. One realization achieves nearly-ideal training of an adaptive equalizer (e.g., 20) of a modem during TRN1d training despite potential RBS in a digital portion (110) of the PSTN (100). Rather than updating equalizer coefficients based on decisions that have been perturbed by RBS, updates in the exemplary realization are based upon the true value of the corresponding equalizer output (the decision) and insensitive to RBS. Adaptive equalizer realizations improve equalizer training by treating the received signal as a sequence of blocks of 24 symbols with 24 corresponding separate decision values. In an exemplary variation, equalizer training begins using a single pair of decision points for coefficient updating. After gross convergence of the equalizer coefficients is achieved the update broadens to include updating each of 24 decision points (repeated in round-robin sequence) as well as the equalizer coefficients. Since RBS disturbances introduced in the digital portion of the PSTN are guaranteed to be periodic with a period no greater than 24, each of the 24 ideal decision points is fixed even when RBS is present. The joint updating of decision points and equalizer coefficients is capable of producing a zero-error condition in the absence of noise. Realizations are also described that employ the adaptive decision updating techniques for other receiver structures (e.g., 501) and in data, as well as training, modes of operation.

60. 发明公开

EP1131644A2 DYNAMIC REGISTER WITH LOW CLOCK RATE TESTING CAPABILITY 有权
标题翻译：与测试能力低速率时钟动态寄存器
公开(公告)号：EP1131644A2
公开(公告)日：2001-09-12
申请号：EP99963875.2
申请日：1999-11-09
申请人： Broadcom Corporation
发明人： HATAMIAN, Mehdi
IPC分类号： G01R31/3185
CPC分类号： H04L7/0062 , G01R31/3008 , G01R31/3016 , G01R31/31715 , G01R31/318502 , G01R31/318552 , G01R31/318594 , H04B3/23 , H04B3/32 , H04L1/0054 , H04L1/242 , H04L7/0334 , H04L25/03038 , H04L25/03057 , H04L25/03146 , H04L25/03267 , H04L25/067 , H04L25/14 , H04L25/4917 , H04L25/497 , H04L2025/03363 , H04L2025/03369 , H04L2025/03477 , H04L2025/0349 , H04L2025/03496 , H04L2025/03503 , H04L2025/03617
摘要： A method for refreshing data in a circuit element included in a dynamic register. A static loop is coupled to the circuit element as a feedback path from the ouput terminal to the input terminal of the circuit element. A control signal is provided to the static loop. The static loop is activated via the control signal to refresh the data in the circuit element.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式