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51. 发明公开

EP2047600A2 MULTI-MODULUS DIVIDER RETIMING CIRCUIT 审中-公开
标题翻译：时钟校正电路和用于分配多模块
公开(公告)号：EP2047600A2
公开(公告)日：2009-04-15
申请号：EP07799793.0
申请日：2007-07-24
申请人： QUALCOMM Incorporated
发明人： NARATHONG, Chiewcharn , SU, Wenjun
IPC分类号： H03K21/10 , H03K23/66
CPC分类号： H03K23/667 , H03K21/10 , H03L7/1976
摘要： A multi-modulus divider (MMD) receives an MMD input signal and outputs an MMD output signal SOUT. The MMD includes a chain of modulus divider stages (MDSs). Each MDS receives an input signal, divides it by either two or three, and outputs the result as an output signal. Each MDS responds to its own modulus control signal that controls whether it divides by two or three. In one example, a sequential logic element outputs SOUT. The low jitter modulus control signal of one of the first MDS stages of the chain is used to place a sequential logic element into a first state. The output signal of one of the MDS stages in the middle of the chain is used to place the sequential logic element into a second state. Power consumption is low because the sequential logic element is not clocked at the high frequency of the MMD input signal.

52. 发明公开

EP1252713A1 PLL FREQUENCY SYNTHESIZER USING CONTROLLED DIVIDER PULSE WIDTHS 审中-公开
标题翻译： PLL频率来控制分频器脉冲宽度
公开(公告)号：EP1252713A1
公开(公告)日：2002-10-30
申请号：EP01901085.9
申请日：2001-01-05
申请人： Conexant Systems, Inc.
发明人： RILEY, Thomas, A.D.
IPC分类号： H03L7/087
CPC分类号： H03L7/18 , H03K21/10 , H03K23/665 , H03K23/667 , H03L7/087 , H03L7/0891 , H03L7/1976
摘要： A method and an apparatus relating to a PLL circuit for frequency synthesizer applications. By using a composite PFD large and small phase variations between a reference signal and the divider output are compensated for. The composite phase frequency detector (PFD) has both a digital phase frequency detector (digital PFD) and an analog phase detector (analog PD) with the digital PFD compensating for large phase differences and the analog PD compensating for smaller phase differences. The PLL automatically chooses between these two components in the composite PFD by controlling the pulse width of the divider output. This is accomplished by synchronizing the dead zone of the digital PFD with the active pulse width of the divider output and by similarly synchronizing the phase detector window of the analog PD to be within both the dead zone of the digital PFD and the active pulse width of the divider output. Thus, during the active pulse of the divider output, the analog PD is operative while during the inactive pulse the digital PFD is operative. By essentially having only one PD active at any time, problems with analog/digital mixed circuits are avoided.

53. 发明公开

EP1126615A1 Verfahren zur Frequenzteilung eines Taktsignals und Frequenzteilerschaltung zur Realisierung des Verfahrens 审中-公开
标题翻译：一种用于方法分频的时钟信号和用于实现该方法的分频电路
公开(公告)号：EP1126615A1
公开(公告)日：2001-08-22
申请号：EP01102405.6
申请日：2001-02-02
申请人： SIEMENS AKTIENGESELLSCHAFT
发明人： Stehle, Birgit
IPC分类号： H03K23/66
CPC分类号： H03K21/10 , H03K23/665
摘要： Zur Taktsignalteilung wird ein Taktimpulse des Taktsignals (clkRef) zählender Taktzähler (TZ) jeweils wechselweise nach Durchlaufen unterschiedlicher Zähldifferenzen zurückgesetzt. Dabei wird ein erstes Signal (risingEdge) und ein zweites Signal (fallingEdge) gebildet, deren logischer Zustand jeweils bei Vorliegen eines ersten (11) bzw. zweiten vorgegebenen Zählerstandes (11) des Taktzählers (TZ) durch eine steigende bzw. fallende Taktsignalflanke geändert wird. Ein geteiltes Ausgangstaktsignal (clkDiv5) wird dann durch eine logische Verknüpfung des ersten (risingEdge) und des zweiten Signals (fallingEdge) erzeugt.
摘要翻译：该方法包括通过两个不同的计数差异之后可替代地复位的时钟信号的时钟脉冲计数器，形成第一信号，其逻辑状态被如果定义的第一计数器的状态存在一个时钟上升沿改变，形成第二信号，其逻辑状态被改变由下降沿如果定义的第二计数器的状态存在，并产生具有两个信号的逻辑组合的分频的输出时钟信号。该方法包括复位时钟计数器穿过第一计数差和不同的第二计数值差值之后可选地进行计数的时钟信号的一个时钟脉冲，形成了第一信号（上升沿），其逻辑状态由上升时钟信号边沿改变如果第一计数器的定义的第一状态存在，从而形成一个第二信号（下降沿），其逻辑状态被如果定义的第二计数器的状态存在，并产生具有的逻辑组合的分频的输出时钟信号（clkDiv5）下降信号边缘改变所述第一和第二信号。因此独立权利要求中包括了以下内容：一个分频电路。

54. 发明公开

EP0740420A2 N+1 Frequency divider counter and method therefor 失效
标题翻译： N + 1Zähler/ Teiler unddazugehörendesVerfahren
公开(公告)号：EP0740420A2
公开(公告)日：1996-10-30
申请号：EP96106280.9
申请日：1996-04-22
申请人： MOTOROLA, INC.
发明人： Shankar, Ravi , Leon, Ana Sonia
IPC分类号： H03K23/66
CPC分类号： H03K21/10 , H03K23/588
摘要： An N+1 frequency divider counter (20) has a binary counter (22), ones detect circuitry (26), control logic (24), and an output flip-flop (28). The binary counter (22) counts from an initial value to a final value for each half of an output clock signal. If N+1 is an even number, one full cycle is added to each half cycle of the output clock signal. If N+1 is an odd number, one-half of a cycle is added to each half phase of the output clock signal. At the final count value, the control logic (24) causes the output clock signal to transition on either the rising edge or the falling edge of an input clock signal. The N+1 counter (20) has a fifty percent duty cycle for all count values of N, and does not require additional circuitry to accommodate when N equals zero.
摘要翻译： N + 1分频器计数器包括具有多个触发器的计数器，用于根据周期性时钟信号从N + 1的预定初始值（其中N是正整数或零）计数到最终值具有预定频率。触发器的数量接收对应于预定初始值的最高有效位的二进制数。第一逻辑电路耦合到计数器，用于接收最终值，并且是响应，提供第一控制信号。控制逻辑电路耦合到第一逻辑电路，用于接收第一控制信号，预定初始值的最低有效位和周期性时钟信号，并且响应于使输出时钟信号在上升沿转变当最低有效位为逻辑0时，周期性时钟信号。当最低有效位为逻辑1时，控制逻辑电路使得输出时钟信号在周期性时钟信号的下降沿上转变。

55. 发明公开

EP0473251A1 Frequency divider and pulse signal former 失效
标题翻译：频率和脉冲形成器。
公开(公告)号：EP0473251A1
公开(公告)日：1992-03-04
申请号：EP91302557.3
申请日：1991-03-25
申请人： MITSUBISHI DENKI KABUSHIKI KAISHA
发明人： Maemura, Kousei, c/o Mitsubishi Denki K.K.
IPC分类号： H03K21/10 , H03K23/68
CPC分类号： H03K23/507 , H03K21/10 , H03K23/546
摘要： A frequency divider includes three or more master-slave type flip-flop's (10,20,30) which are connected to each other to construct a 1/N frequency divider, in which two or more outputs whose periods are the same but phases are different are taken out from a master stage and a slave stage of each flip-flop, respectively and then those signals are composed to obtain a 1/(N/2) dividing output signal. As a result, a dividing output signal whose period does not vary with time can be obtained and also when the N is an even number, the output signal whose duty ratio is 1/2 can be further obtained. A pulse signal former (42,51,52) includes a differential amplifier to which two signals whose periods and pulse widths are the same but phases are different from each other by a pulse signal, and an output obtained by comparing those two signals is output from the pulse signal former. As a result, an output signal whose duty ratio is 1/2 is obtained.
摘要翻译：分频器包括三个或更多个主从型触发器（10,20,30），它们彼此连接以构成1 / N分频器，其中两个或更多个周期相同但相位相等的输出分别从每个触发器的主级和从级分别取出不同的，然后构成这些信号以获得1 /（N / 2）分频输出信号。结果，可以获得其周期不随时间变化的分频输出信号，并且当N是偶数时，可以进一步获得占空比为1/2的输出信号。脉冲信号形成器（42,51,52）包括差分放大器，其周期和脉冲宽度相同但两相相位彼此不同的两个信号通过脉冲信号彼此不同，并且输出通过比较两个信号获得的输出来自脉冲信号。结果，得到占空比为1/2的输出信号。

56. 发明申请

WO2016089292A1 POWER EFFICIENT HIGH SPEED LATCH CIRCUITS AND SYSTEMS 审中-公开
标题翻译：功率有效的高速锁存电路和系统
公开(公告)号：WO2016089292A1
公开(公告)日：2016-06-09
申请号：PCT/SE2015/051298
申请日：2015-12-02
申请人： TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
发明人： BAGGER, Reza
IPC分类号： H03K21/10 , H03K23/48 , H03K23/42 , H03K3/356 , H03K3/3562
CPC分类号： H03K21/10 , H03K3/356104 , H03K3/356139 , H03K3/35625 , H03K5/15066 , H03K19/20 , H03K23/425 , H03K23/483 , H04B1/40
摘要： The present invention relates to a combiner latch circuit and a latching system for generation of one phase differential signal pair or two phase differential signal pairs. The scope of the applications ranges from division and frequency generation in prescalers to phase and frequency generation in mixer's transceivers for high speed wireless applications. The combiner latch circuit 700 comprises an input circuit 701 with an input A 702, an input B 703, a clock input CLK 704, and an inverted clock input CLK705, an output circuit 706with a differential output X, Y 707,708. The input circuit 701 is connected to the output circuit 706, and configured to select a state of the output circuit 706 from a group of: a fourth state (S4) comprising the differential output X=1, Y=0 of the differential output X, Y 707,708, a fifth state (S5) comprising the differential output X=0,Y=1 of the differential output X, Y 707,708. The input circuit 701 is further configured to select the fourth state S4 if the input A=0 and the input B=1 and the clock input CLK 704 encounter a leading edge from 0 to 1 and the output circuit is in the fifth state S5, and select the fifth state S5 if the input A=1 and the input B=0 and the clock input CLK 704encounter a leading edge from 0 to 1 and the output circuit is in the fourth state S4.
摘要翻译：本发明涉及用于产生一相差分信号对或两相差分信号对的组合器锁存电路和闭锁系统。应用范围从预分频器的分频和频率生成到混频器收发器中的高频无线应用的相位和频率产生。组合器锁存电路700包括具有输入A 702，输入B 703，时钟输入CLK 704和反相时钟输入CLK705的输入电路701，具有差分输出X的输出电路706，Y 707,708。输入电路701连接到输出电路706，并且被配置为从包括差分输出X的差分输出X = 1，Y = 0的第四状态（S4）中选择输出电路706的状态，Y 707,708，包括差分输出X = 0，差分输出X的Y = 1的第五状态（S5），Y 707,708。输入电路701还被配置为：如果输入A = 0且输入B = 1并且时钟输入CLK 704的前沿从0到1，并且输出电路处于第五状态S5，则选择第四状态S4，并且如果输入A = 1并且输入B = 0并且时钟输入CLK 704en从0到1的前沿，并且输出电路处于第四状态S4，则选择第五状态S5。

57. 发明申请

WO2013155352A1 COMPACT HIGH FREQUENCY DIVIDER 审中-公开
标题翻译：紧凑型高频分频器
公开(公告)号：WO2013155352A1
公开(公告)日：2013-10-17
申请号：PCT/US2013/036251
申请日：2013-04-11
申请人： QUALCOMM INCORPORATED
发明人： CHAN, Ngar, Loong, A.
IPC分类号： H03K3/356 , H03K21/02 , H03K21/10
CPC分类号： H03B19/14 , H03K3/35613 , H03K21/026 , H03K21/10
摘要： A frequency divider circuit having two stages of transistors has improved performance at low supply voltages. The circuit may include cross-coupled PMOS (112a, 112b) and NMOS transistors (114a, 114b), in which the input signal to be frequency divided is supplied to the body of the PMOS and/or NMOS transistors. The input signal may be coupled to the PMOS and/or NMOS transistors through capacitive or inductive coupling. The input signal to the PMOS and/or NMOS transistors may be generated by a voltage controlled oscillator circuit. With the frequency divider circuit having inputs signals coupled to the body of the PMOS and/or NMOS transistors supply voltages as low as 0.5 Volts may be possible.
摘要翻译：具有两级晶体管的分频器电路在低电源电压下具有改进的性能。电路可以包括交叉耦合的PMOS（112a，112b）和NMOS晶体管（114a，114b），其中待分频的输入信号被提供给PMOS和/或NMOS晶体管的主体。输入信号可以通过电容或电感耦合耦合到PMOS和/或NMOS晶体管。可以通过压控振荡器电路产生到PMOS和/或NMOS晶体管的输入信号。利用具有耦合到PMOS和/或NMOS晶体管的输入信号的分频器电路，可以提供低至0.5伏特的电压。

58. 发明申请

WO2005029720A1 MULTI-BAND TRANSCEIVER 审中-公开
标题翻译：多带收发器
公开(公告)号：WO2005029720A1
公开(公告)日：2005-03-31
申请号：PCT/IB2004/051691
申请日：2004-09-06
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , LEENAERTS, Dominicus, M., W. , REDMAN-WHITE, William
发明人： LEENAERTS, Dominicus, M., W. , REDMAN-WHITE, William
IPC分类号： H04B1/40
CPC分类号： H03K21/10 , H03K23/505 , H03L7/183 , H04B1/30 , H04B1/406
摘要： A multi-band transceiver (100) for receiving or transmitting signals situated in substantially different frequency ranges comprising first transceiver (1) coupled to an input/output terminal (In/Out) via a first pair of switches (SWI, SW2). The multi-band transceiver further comprises a second transceiver (2) coupled to the input/output terminal (In/Out) via second pair of switches (SW 1', SW2') and only one local oscillating system (3) comprising only one voltage controlled oscillator (VCO).
摘要翻译：一种用于接收或发送位于基本上不同的频率范围内的信号的多频带收发器（100），包括经由第一对开关（SWI，SW2）耦合到输入/输出端子（输入/输出）的第一收发器（1）。多频带收发机还包括经由第二对开关（SW 1'，SW 2'）耦合到输入/输出端（输入/输出）的第二收发器（2），并且仅一个本地振荡系统（3）仅包括一个压控振荡器（VCO）。

59. 发明申请

WO02029973A2 A PROGRAMMABLE DIVIDER WITH BUILT-IN PROGRAMMABLE DELAY CHAIN FOR HIGH-SPEED/LOW POWER APPLICATION 审中-公开
标题翻译：具有可编程可编程延迟链的可编程分频器，用于高速/低功率应用
公开(公告)号：WO02029973A2
公开(公告)日：2002-04-11
申请号：PCT/US2001/031038
申请日：2001-10-04
IPC分类号： H03K21/10 , H03K23/54 , H03K23/66 , H03K23/50
CPC分类号： H03K23/542 , H03K21/10 , H03K23/66
摘要： A programmable divider includes a synchronous counter (202) configured to process an input clock signal and produce first output signals in response the input clock signal. A number of logic devices (210,...,21N) are coupled to the synchronous counter (202) and configurable to receive the first output signals and correspondingly produce second output signals. Also included is a mulitplexer (204) that is configured to receive the second output signals and has an output coupled to an input of the synchronous counter. In the programmable divider, characteristics of the synchronous counter are selectable based upon a particular number of the logic devices configured.
摘要翻译：可编程分频器包括被配置为处理输入时钟信号并响应输入时钟信号产生第一输出信号的同步计数器（202）。多个逻辑设备（210，...，21N）耦合到同步计数器（202），并且可配置为接收第一输出信号并相应地产生第二输出信号。还包括多路复用器（204），其被配置为接收第二输出信号并且具有耦合到同步计数器的输入的输出。在可编程分频器中，基于配置的逻辑器件的特定数量可选择同步计数器的特性。

60. 发明申请

WO01050610A1 PLL FREQUENCY SYNTHESIZER USING CONTROLLED DIVIDER PULSE WIDTHS 审中-公开
标题翻译：使用控制分路器脉冲宽度的PLL频率合成器
公开(公告)号：WO01050610A1
公开(公告)日：2001-07-12
申请号：PCT/CA2001/000020
申请日：2001-01-05
IPC分类号： H03L7/113 , H03K21/10 , H03K23/66 , H03L7/087 , H03L7/089 , H03L7/18 , H03L7/183 , H03L7/197
CPC分类号： H03L7/18 , H03K21/10 , H03K23/665 , H03K23/667 , H03L7/087 , H03L7/0891 , H03L7/1976
摘要： A method and an apparatus relating to a PLL circuit for frequency synthesizer applications. By using a composite PFD large and small phase variations between a reference signal and the divider output are compensated for. The composite phase frequency detector (PFD) has both a digital phase frequency detector (digital PFD) and an analog phase detector (analog PD) with the digital PFD compensating for large phase differences and the analog PD compensating for smaller phase differences. The PLL automatically chooses between these two components in the composite PFD by controlling the pulse width of the divider output. This is accomplished by synchronizing the dead zone of the digital PFD with the active pulse width of the divider output and by similarly synchronizing the phase detector window of the analog PD to be within both the dead zone of the digital PFD and the active pulse width of the divider output. Thus, during the active pulse of the divider output, the analog PD is operative while during the inactive pulse the digital PFD is operative. By essentially having only one PD active at any time, problems with analog/digital mixed circuits are avoided.
摘要翻译：涉及用于频率合成器应用的PLL电路的方法和装置。通过使用复合PFD补偿参考信号和分频器输出之间的大小相位变化。复合相位频率检测器（PFD）具有数字相位频率检测器（数字PFD）和模拟相位检测器（模拟PD），数字PFD补偿大的相位差，模拟PD补偿较小的相位差。 PLL通过控制分频器输出的脉冲宽度自动在复合PFD中的这两个组件之间进行选择。这是通过将数字PFD的死区与分频器输出的有效脉冲宽度同步来实现的，并且通过类似地使模拟PD的相位检测器窗口同步在数字PFD的死区内和分频器输出。因此，在分频器输出的有效脉冲期间，模拟PD工作，而无效脉冲期间数字PFD可操作。通过在任何时间基本上仅具有一个PD活动，避免了模拟/数字混合电路的问题。

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