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51. 发明公开

EP0642158A1 Method of isolating vertical shorts in an electronic array 失效
标题翻译： Isolierungsverfahren von vertikalenKurzschlüssen在einer elektronischen Anordnung。
公开(公告)号：EP0642158A1
公开(公告)日：1995-03-08
申请号：EP94306162.2
申请日：1994-08-19
申请人： GENERAL ELECTRIC COMPANY
发明人： Liu, Yung Sheng , Guida, Renato, , Wei, Ching-Yey,
IPC分类号： H01L21/768 , H01L21/48 , G02F1/136
CPC分类号： H01L21/76894 , G02F1/1362 , H01L21/485 , H05K3/225 , Y10S438/94
摘要： A process for repairing an electronic array wafer assembly having a short circuit between two non-insulative layers (116,113a,113b) separated by a dielectric layer (114) includes the step of selectively ablating one of the non-insulative layers so as to electrically isolate the situs of the short circuit while maintaining the electrical integrity of the underlying non-insulative layer intact. A laser beam is directed onto the non-insulative layer and scanned in a selected pattern to isolate the situs of the short circuit; the laser is further controlled such that a selected energy density is delivered to the surface to be ablated such that the underlying non-insulative layer (113a,113b) is not damaged.
摘要翻译：在由介电层（114）分开的两个非绝缘层（116,113a，113b）之间具有短路的电子阵列晶片组件的修复方法包括以下步骤：选择性地将非绝缘层中的一个烧蚀以便电隔离短路的位置，同时保持底层非绝缘层的电气完整性。激光束被引导到非绝缘层上并以选定的图案扫描以隔离短路的位置; 进一步控制激光，使得所选择的能量密度被传送到要消融的表面，使得下面的非绝缘层（113a，113b）不被损坏。

52. 发明公开

EP0478368A1 Integrated circuits and processes of manufacture 失效
标题翻译： Integrierte Schaltung und Verfahren zu deren Herstellung。
公开(公告)号：EP0478368A1
公开(公告)日：1992-04-01
申请号：EP91308860.5
申请日：1991-09-27
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Sauerbrey, Roland, Rice University , Smayling, Michael C.
IPC分类号： H01L21/768 , H01L23/485 , H01L23/498 , H01L23/525
CPC分类号： H01L23/5328 , H01B1/12 , H01B1/128 , H01L21/485 , H01L23/5254 , H01L2924/0002 , H01L2924/09701 , H01L2924/12044 , H05K3/105 , H05K3/4038 , H05K2201/0329 , H05K2203/107 , H05K2203/1136 , H01L2924/00
摘要： An integrated circuit includes conductive elements (415.i, 417.j) and a radiation sensitive material (511) interposed between the conductive elements and dosed to different conductivities in different portions (e.g. 447) thereof. Another aspect is a process of integrated circuit fabrication including steps (163, 615) of depositing a radiation sensitive material as a layer and variably dosing it with radiation to establish areas of higher and lower resistivity in the layer. A printed wiring board (241) includes radiation sensitive material (251) and the board further has a conductor layer (245, 247, 249) affixed to the base. A transistor (1401) has a radiation sensitive material (1413) dosed to have two conductive regions (1431, 1433) separated by a gap (1435) of a lower conductivity in the radiation sensitive material, and a conductive substance (1415) deposited over the gap. These elements are useful in smart power devices, digital computers, controllers and electronic applications generally. Other devices, systems and processes are disclosed.
摘要翻译：集成电路包括介于导电元件之间的导电元件（415.i，417.j）和辐射敏感材料（511），并且在不同部分（例如447）中被赋予不同的电导率。另一方面是集成电路制造的过程，包括将辐射敏感材料沉积为层并且用辐射可变地配量辐射的步骤（163,615），以在层中建立更高和更低电阻率的区域。印刷电路板（241）包括辐射敏感材料（251），并且该板还具有固定到基底的导体层（245,247,249）。晶体管（1401）具有辐射敏感材料（1413），辐射敏感材料（1413）被配置为具有由辐射敏感材料中较低导电性的间隙（1435）分隔开的两个导电区域（1431,1433），以及沉积在差距。这些元件通常用于智能功率器件，数字计算机，控制器和电子应用中。公开了其他设备，系统和过程。

53. 发明公开

EP3264458A1 METHOD FOR CAPPING CU LAYER USING GRAPHENE IN SEMICONDUCTOR 审中-公开
标题翻译：在半导体中用石墨烯覆盖CU层的方法
公开(公告)号：EP3264458A1
公开(公告)日：2018-01-03
申请号：EP17178818.5
申请日：2017-06-29
申请人： Semiconductor Manufacturing International Corporation (Shanghai) , Semiconductor Manufacturing International Corporation (Beijing)
发明人： ZHOU, Ming
IPC分类号： H01L23/532 , H01L21/768
CPC分类号： H01L23/53233 , H01L21/485 , H01L21/768 , H01L21/76811 , H01L21/76813 , H01L21/76829 , H01L21/76849 , H01L21/76895 , H01L21/823475 , H01L21/823871 , H01L23/29 , H01L23/4928 , H01L23/53238
摘要： An interconnect structure includes a substrate, a dielectric layer (220) on the substrate, a metal interconnect layer (230) in the dielectric layer and in contact with the substrate, the metal interconnect layer having an upper surface flush with an upper surface of the dielectric layer, and a graphene layer (260) on the metal interconnect layer. The graphene layer insulates a metal from air and prevents the metal from being oxidized by oxygen in the air, thereby increasing the queue time for the CMP process and the device reliability.
摘要翻译：一种互连结构，包括衬底，衬底上的电介质层（220），电介质层中的金属互连层（230）以及与衬底接触，金属互连层具有与上表面齐平的上表面介电层以及金属互连层上的石墨烯层（260）。石墨烯层将金属与空气隔离并防止金属被空气中的氧气氧化，从而增加了CMP工艺的排队时间和器件的可靠性。

54. 发明公开

EP3023836A1 METHOD OF MANUFACTURING DISPLAY SUBSTRATE, REPAIR METHOD OF DISPLAY SUBSTRATE AND DISPLAY SUBSTRATE REPAIRED BY THE REPAIR METHOD 审中-公开
标题翻译：用于生产的显示基板，方法修复显示基板和程序固定显示器基板
公开(公告)号：EP3023836A1
公开(公告)日：2016-05-25
申请号：EP15172094.3
申请日：2015-06-15
申请人： Samsung Display Co., Ltd.
发明人： Lee, Hong-Beom , Min, Kyeoung-Hae , Baek, Yeon-Ha , Shin, Ji-Hoon , Shin, Ho-Yong , Lee, Jae-Hyun
IPC分类号： G02F1/1362 , H01L21/768
CPC分类号： G02F1/136259 , G02F1/1309 , G02F1/136227 , G02F1/136286 , G02F2001/136222 , G02F2001/136263 , G02F2201/42 , G09G3/20 , G09G3/3648 , G09G2300/0426 , G09G2330/08 , G09G2330/12 , H01L21/485 , H01L21/76894 , H01L22/22 , H01L27/124 , H01L27/1248 , H01L27/1259 , H01L2221/101
摘要： A display substrate includes a gate metal pattern comprising a gate line extending in a first direction and a gate electrode electrically connected to the gate line, a data metal pattern comprising a data line extending in a second direction crossing the first direction, a source electrode electrically connected to the data line and a drain electrode spaced apart from the source electrode, an organic layer disposed on the data metal pattern, a repair hole penetrating the organic layer and exposing a crossing area in which the gate line crosses with the data line and a pixel electrode disposed on the organic layer and electrically connected to the drain electrode.
摘要翻译：一种显示基板包括：栅极金属图案包括栅极线在第一方向上延伸和栅电极电连接到所述栅极线，数据金属图案包括数据线在第二方向上延伸交叉的第二方向，源电极，电连接到数据线，并从源电极到设置在数据金属图案有机层间隔开的漏电极，修复孔穿透所述有机层和暴露的交叉区域，其中所述栅极线与所述数据线和交叉像素电极设置在有机层上，并且电连接到所述漏电极。

55. 发明公开

EP2919265A2 SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING BASE FOR SEMICONDUCTOR PACKAGE 有权
标题翻译：半导体本体及其制造方法的基础的半导体HOUSING
公开(公告)号：EP2919265A2
公开(公告)日：2015-09-16
申请号：EP15155491.2
申请日：2015-02-18
申请人： MediaTek, Inc
发明人： Hsu, Wen-Sung , Yu, Ta-Jen
IPC分类号： H01L23/66
CPC分类号： H01L21/485 , H01F17/00 , H01F17/0006 , H01L21/486 , H01L21/568 , H01L21/6835 , H01L21/705 , H01L23/49822 , H01L23/49827 , H01L23/5389 , H01L23/642 , H01L23/645 , H01L23/66 , H01L24/17 , H01L25/50 , H01L2224/13147 , H01L2224/16113 , H01L2224/16225 , H01L2224/16237 , H01L2924/12042 , H01L2924/1206 , H01L2924/1421 , H01L2924/15165 , H01L2924/1517 , H01L2924/2064 , H05K1/165 , H05K1/181 , H05K1/183 , H05K3/0017 , H05K3/0026 , H05K3/0047 , H05K3/107 , H05K3/188 , H05K3/303 , H05K2201/10098 , H01L2924/00
摘要： The invention provides a semiconductor package and a method for fabricating a base for a semiconductor package. The semiconductor package includes a base. The base has a device-attach surface. A radio-frequency (RF) device is embedded in the base. The RF device is close to the device-attach surface.
摘要翻译：本发明提供一种半导体封装和用于制造基础的半导体封装的方法。所述半导体封装包括一底座。所述基座具有设备粘贴面。一种射频（RF）设备被嵌入基。 RF设备是靠近器件贴装表面。

56. 发明公开

EP1774582A2 MICRO-CASTELLATED INTERPOSER 审中-公开
标题翻译： MICRO-CASTELLATED插入器
公开(公告)号：EP1774582A2
公开(公告)日：2007-04-18
申请号：EP05769151.1
申请日：2005-06-29
申请人： Honeywell International, Inc.
发明人： LEVINE, Aaron , STANKE, Jay, D.
IPC分类号： H01L21/48 , H01L23/538 , H01L23/498
CPC分类号： H01L21/485 , H01L23/49805 , H01L2924/0002 , H05K1/141 , H05K3/225 , H05K3/3442 , H05K3/403 , H05K2201/068 , H05K2201/09063 , H05K2201/09181 , H05K2201/09645 , H01L2924/00
摘要： A miniature PWB (101) with features that incorporate the required circuitry changes and component footprints (105), which has been enhanced with micro-castellations (111) such as those found on ceramic surface mount packages. The miniature PWB (101) is mounted on the circuit board (125) using techniques well known in the art. This combination of technologies provides an adaptable, durable interconnect methodology, which allows for circuit (109) and part changes (113, 115, 117) without changing the layout of the base printed wiring board (125).
摘要翻译：一种微型PWB（101），其特征包括所需的电路变化和元件占位面积（105），这些元件占位面积已通过陶瓷表面贴装封装上的微型城堡（111）得到了增强。使用本领域公知的技术将微型PWB（101）安装在电路板（125）上。这种技术组合提供了一种适应性强，持久的互连方法，该方法允许电路（109）和部件更换（113,115,117），而不改变基座印刷电路板（125）的布局。

57. 发明公开

EP1689554A2 LASER-BASED SYSTEM FOR MEMORY LINK PROCESSING WITH PICOSECOND LASERS 审中-公开
标题翻译：澳大利亚激光基础系统FÜRSPEICHERVERBINDUNGSBEARBEITUNG MIT PIKOSEKUNDENLASERN
公开(公告)号：EP1689554A2
公开(公告)日：2006-08-16
申请号：EP04794131.5
申请日：2004-10-05
申请人： GSI Lumonics Corporation
发明人： GU, Bo , SMART, Donald, V. , CORDINGLEY, James, J. , LEE, Joohan , SVETKOFF, Donald, J. , JOHNSON, Shepard, D. , EHRMANN, Jonathan, S.
IPC分类号： B23K26/36
CPC分类号： H01S3/2383 , B23K26/04 , B23K26/0624 , B23K26/0626 , B23K26/0736 , B23K26/361 , B23K26/389 , B23K26/40 , B23K2201/38 , B23K2201/40 , B23K2203/10 , B23K2203/12 , B23K2203/172 , H01L21/485 , H01L21/76894 , H01L22/12 , H01L23/5258 , H01L2924/0002 , H01S3/0085 , H01S3/06758 , H01S3/1618 , H01S3/23 , H05K3/0026 , H01L2924/00
摘要： A laser-based system for processing target material within a microscopic region without causing undesirable changes in electrical or physical characteristics of at least one material surrounding the target material, the system includes a seed laser, an optical amplifier, and a beam delivery system. The seed laser for generating a sequence of laser pulses having a first pre-determined wavelength. The optical amplifier for amplifying at least a portion of the sequence of pulses to obtain an amplified sequence of output pulses. The beam delivery system for delivering and focusing at least one pulse of the amplified sequence of pulses onto the target material. The at least one output pulse having a pulse duration in the range of about (10) picoseconds to less than (1) nanosecond. The pulse duration being within a thermal processing range. The at least one focused output pulse having sufficient power density at a location within the target material to reduce the reflectivity of the target material and efficiently couple the focused output into the target material to remove the target material.
摘要翻译：一种用于在微观区域内处理目标材料而不引起围绕靶材料的至少一种材料的电学或物理特性的不希望的变化的基于激光的系统，该系统包括种子激光器，光放大器和光束传递系统。用于产生具有第一预定波长的激光脉冲序列的种子激光器。用于放大脉冲序列的至少一部分以获得放大的输出脉冲序列的光放大器。用于将放大的脉冲序列的至少一个脉冲传送和聚焦到目标材料上的光束传送系统。所述至少一个输出脉冲具有在约10皮秒至小于1纳秒范围内的脉冲持续时间。脉冲持续时间在热处理范围内。所述至少一个聚焦输出脉冲在目标材料内的位置处具有足够的功率密度，以减少目标材料的反射率并有效地将聚焦的输出耦合到目标材料中以去除目标材料。

58. 发明公开

EP1547142A1 SELECTIVE CONNECTION IN IC PACKAGING 有权
标题翻译：与IC包胶选择性地连接
公开(公告)号：EP1547142A1
公开(公告)日：2005-06-29
申请号：EP03798966.2
申请日：2003-09-15
申请人： International Business Machines Corporation
发明人： MACQUARRIE, Stephen, Wesley , MEMIS, Irving
IPC分类号： H01L21/60 , H01L23/498
CPC分类号： H01L23/13 , H01L21/485 , H01L23/49811 , H01L23/50 , H01L24/16 , H01L24/17 , H01L24/81 , H01L2224/05568 , H01L2224/05573 , H01L2224/13099 , H01L2224/16225 , H01L2224/81191 , H01L2224/81801 , H01L2924/00014 , H01L2924/01004 , H01L2924/01019 , H01L2924/01033 , H01L2924/014 , H01L2924/14 , H01L2924/30105 , H05K1/0256 , H05K3/3452 , H05K2201/09036 , H05K2201/10674 , H01L2224/05599
摘要： In an integrated circuit package employing solder bump technology, a metal wiring placed on the surface of a substrate below an array of bonding pads is split and displaced from its axis at selected locations to preserve electrical continuity, but to also lower the height of an insulating solder mask layer at those locations.

59. 发明公开

EP1290730A1 PROCEDE POUR REALISER UNE PERMUTATION D'ENTREES/SORTIES DE PLUSIEURS PISTES A BRANCHES PARALLELES D'UN CIRCUIT INTEGRE ET CIRCUIT OBTENU 有权
标题翻译：法Backup与集成电路中的并联支路输入/输出导体和由此得到集成电路
公开(公告)号：EP1290730A1
公开(公告)日：2003-03-12
申请号：EP01947499.8
申请日：2001-06-06
申请人： CENTRE NATIONAL D'ETUDES SPATIALES
发明人： DESPLATS, Romain , BENTEO, Bruno
IPC分类号： H01L23/538 , H01L21/48
CPC分类号： H01L23/5382 , H01L21/485 , H01L2924/0002 , H01L2924/00
摘要： The invention concerns a method for producing an input/output permutation of several conductive strips on an integrated circuit. The method consists in: identifying, among the parallel branches of the conductive strips, a minimal group whereof the branches are designed to be subjected to input/output swapping; locating a bend (3) on a deflected branch (2) and carrying out a conductive deposit (5) perpendicular from said bend (3) between the two parallel branches (1, 2), and an inclined deposit (9) between the perpendicular branch (4) and the parallel branch (1) with breaks (7, 8) so as to swap the inputs and the outputs. The invention also concerns the resulting integrated circuit.

60. 发明公开

EP1130408A2 Verfahren und Vorrichtung zur Anpassung/Abstimmung von Signallaufzeiten auf Leitungssystemen oder Netzen zwischen integrierten Schaltungen 有权
标题翻译：用于集成电路之间适配在线路系统/调谐信号渡越时间或网络的方法和装置
公开(公告)号：EP1130408A2
公开(公告)日：2001-09-05
申请号：EP01101831.4
申请日：2001-01-26
申请人： Infineon Technologies AG
发明人： Muff, Simon
IPC分类号： G01R31/317 , G06F13/40
CPC分类号： H05K1/0248 , G01R31/3016 , G01R31/31725 , H01L21/485 , H05K1/0268 , H05K1/162 , H05K2201/10689 , H05K2203/107 , H05K2203/171 , H05K2203/175
摘要： Die Erfindung betrifft ein Verfahren und eine Vorrichtung zur Anpassung/Abstimmung von Signallaufzeiten auf Leitungssystemen oder Netzen zwischen auf gedruckten Leiterplatten montierten integrierten Schaltungen, bei dem sich durch kapazitive Laststrukturen an Leiterbahnen (3-9) in der Nähe von Chipgehäusen von den integrierten Schaltungen auf der gedruckten Leiterplatte eine Feinabstimmung der Laufzeitunterschiede einfach dadurch durchführen läßt, dass Verbindungsleitungen (20, 21) mittels eines Schneidelasers durchgetrennt werden (Figur 1B).
摘要翻译：本发明涉及一种方法和用于适配设备上线系统或网络/调谐信号渡越时间安装在印刷电路板上的集成电路之间，其中通过在所述的集成电路芯片外壳的附近导体路径（3-9）的电容性负载的结构印刷电路板可通过的时间差即连接线（20，21）是由一个激光切割（图1B）的方法分离微调可以容易地进行。

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