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51. 发明申请

US20090035905A1 INSITU FORMATION OF INVERSE FLOATING GATE POLY STRUCTURES 有权
标题翻译：逆向浮选门结构的形成
公开(公告)号：US20090035905A1
公开(公告)日：2009-02-05
申请号：US11832972
申请日：2007-08-02
申请人： Ramakanth Alapati , Gurtej Sandhu
发明人： Ramakanth Alapati , Gurtej Sandhu
IPC分类号： H01L21/336
CPC分类号： H01L29/7881 , H01L21/28273 , H01L27/115 , H01L27/11521
摘要： Briefly, in accordance with one or more embodiments, a method of making an inverse-t shaped floating gate in a non-volatile memory cell or the like is disclosed.
摘要翻译：简而言之，根据一个或多个实施例，公开了在非易失性存储单元等中制造逆T形浮置栅极的方法。

52. 发明授权

US07452759B2 Carbon nanotube field effect transistor and methods for making same 有权
标题翻译：碳纳米管场效应晶体管及其制造方法
公开(公告)号：US07452759B2
公开(公告)日：2008-11-18
申请号：US11288816
申请日：2005-11-29
申请人： Gurtej Sandhu
发明人： Gurtej Sandhu
IPC分类号： H01L21/84
CPC分类号： H01L51/0512 , B82Y10/00 , H01L51/0048 , Y10S977/842 , Y10S977/938
摘要： A structure and fabrication process for a carbon nanotube field effect transistor is disclosed herein. In one embodiment, a method for forming a carbon nanotube transistor starts with a substrate comprised of a bottom dielectric, a carbon nanotube layer, and a top dielectric. A pillar is formed on the top dielectric, and a sidewall gate is formed on a sidewall of the pillar. A source is formed proximate to an outer edge of the gate and in contact with the carbon nanotube layer. The pillar is then removed, the source area masked, and a drain is formed proximate to an inner edge of the gate and in contact with the carbon nanotube layer. The source and drain are self aligned to the gate as dictated by the placement of dielectric spacers on the inner and outer edges of the gate.
摘要翻译：本文公开了一种用于碳纳米管场效应晶体管的结构和制造方法。在一个实施例中，用于形成碳纳米管晶体管的方法从由底部电介质，碳纳米管层和顶部电介质构成的衬底开始。在顶部电介质上形成有支柱，并且在该支柱的侧壁上形成侧壁浇口。源极靠近栅极的外边缘形成并与碳纳米管层接触。然后移除柱，源区域被掩蔽，并且漏极形成在栅极的内边缘附近并与碳纳米管层接触。源极和漏极与栅极自对准，这是由栅极的内部和外部边缘上的介质间隔物的放置所决定的。

53. 发明授权

US07444934B2 Supercritical fluid-assisted direct write for printing integrated circuits 失效
标题翻译：用于印刷集成电路的超临界流体辅助直接写入
公开(公告)号：US07444934B2
公开(公告)日：2008-11-04
申请号：US11135453
申请日：2005-05-24
申请人： Gurtej Sandhu , Cem Basceri
发明人： Gurtej Sandhu , Cem Basceri
IPC分类号： B41F33/00
CPC分类号： B41F33/00 , B33Y40/00 , H01L21/288 , H01L21/76838 , H01L23/5328 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： High resolution patterns provided on a surface of a semiconductor substrate and methods of direct printing of such high resolution patterns are disclosed. The high resolution patterns may have dimensions less than 0.1 micron and are formed by a direct writing method employing a supercritical fluid comprising nanometer-sized particles, which may be optionally electrically charged.
摘要翻译：公开了在半导体衬底的表面上提供的高分辨率图案以及直接印刷这种高分辨率图案的方法。高分辨率图案可以具有小于0.1微米的尺寸，并且通过使用包含纳米尺寸颗粒的超临界流体的直接书写方法形成，所述超临界流体可以任选带电。

54. 发明授权

US07429536B2 Methods for forming arrays of small, closely spaced features 有权
标题翻译：用于形成小的，紧密间隔的特征的阵列的方法
公开(公告)号：US07429536B2
公开(公告)日：2008-09-30
申请号：US11134982
申请日：2005-05-23
申请人： Mirzafer Abatchev , Gurtej Sandhu
发明人： Mirzafer Abatchev , Gurtej Sandhu
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/31144 , H01L21/0337 , H01L21/0338 , H01L21/76816 , H01L27/105 , H01L27/1052 , H01L2924/0002 , Y10S438/947 , H01L2924/00
摘要： Methods of forming arrays of small, densely spaced holes or pillars for use in integrated circuits are disclosed. Various pattern transfer and etching steps can be used, in combination with pitch-reduction techniques, to create densely-packed features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form sumperimposed, pitch-reduced patterns of crossing elongate features that can be consolidated into a single layer.
摘要翻译：公开了形成集成电路中使用的小密集间隔开的孔或柱的阵列的方法。可以使用各种图案转移和蚀刻步骤，结合减音技术来产生密集包装的特征。传统的光刻步骤可以与俯仰减小技术结合使用，以形成可以被整合成单一层的交叉细长特征的叠加的俯仰减小图案。

55. 发明申请

US20080089647A1 RESONATOR FOR THERMO OPTIC DEVICE 有权
标题翻译：热电偶装置谐振器
公开(公告)号：US20080089647A1
公开(公告)日：2008-04-17
申请号：US11951796
申请日：2007-12-06
申请人： Gurtej Sandhu , Guy Blalock , Howard Rhodes
发明人： Gurtej Sandhu , Guy Blalock , Howard Rhodes
IPC分类号： G02B6/26
CPC分类号： G02B6/132 , G02B6/12004 , G02B6/12007 , G02B6/136 , G02F1/011 , G02F1/0147 , G02F2203/15
摘要： A resonator for thermo optic devices is formed in the same process steps as a waveguide and is formed in a depression of a lower cladding while the waveguide is formed on a surface of the lower cladding. Since upper surfaces of the resonator and waveguide are substantially coplanar, the aspect ratio, as between the waveguide and resonator in an area where the waveguide and resonator front one another, decreases thereby increasing the bandwidth of the resonator. The depression is formed by photomasking and etching the lower cladding before forming the resonator and waveguide. Pluralities of resonators are also taught that are formed in a plurality of depressions of the lower cladding. To decrease resonator bandwidth, waveguide(s) are formed in the depression(s) of the lower cladding while the resonator is formed on the surface. Thermo optic devices formed with these resonators are also taught.
摘要翻译：用于热光器件的谐振器以与波导相同的工艺步骤形成，并且形成在下包层的凹陷中，同时波导形成在下包层的表面上。由于谐振器和波导的上表面基本上是共面的，因此在波导和谐振器彼此前向的区域中的波导和谐振器之间的纵横比减小，从而增加了谐振器的带宽。在形成谐振器和波导之前，通过光掩模和蚀刻下部包层形成凹陷。还教导了形成在下部包层的多个凹部中的多个谐振器。为了减小谐振器带宽，当在表面上形成谐振器时，在下包层的凹陷中形成波导。还教导了用这些谐振器形成的热光器件。

56. 发明申请

US20070284638A1 Conductive container structures having a dielectric cap 审中-公开
公开(公告)号：US20070284638A1
公开(公告)日：2007-12-13
申请号：US11728912
申请日：2007-03-27
申请人： Gurtej Sandhu , Alan Reinberg
发明人： Gurtej Sandhu , Alan Reinberg
IPC分类号： H01L27/108
CPC分类号： H01L28/90 , H01L27/10852 , H01L28/84 , H01L28/91 , Y10S257/906
摘要： Container structures for use in integrated circuits and methods of their manufacture. The container structures have a dielectric cap on the top of a conductive container to reduce the risk of container-to-container shorting by insulating against bridging of conductive debris across the tops of adjacent container structures. The container structures are adapted for use in memory cells and apparatus incorporating such memory cells, as well as other integrated circuits.

57. 发明申请

US20070275526A1 METHODS OF PROGRAMMING MEMORY CELLS USING MANIPULATION OF OXYGEN VACANCIES 有权
标题翻译：使用操作氧气存储器编程记忆细胞的方法
公开(公告)号：US20070275526A1
公开(公告)日：2007-11-29
申请号：US11837149
申请日：2007-08-10
申请人： Cem Basceri , Gurtej Sandhu
发明人： Cem Basceri , Gurtej Sandhu
IPC分类号： H01L21/336
CPC分类号： G11C11/5671 , G11C8/12 , G11C16/0416 , G11C16/0466 , H01L29/513 , H01L29/792
摘要： One-transistor memory devices facilitate nonvolatile data storage through the manipulation of oxygen vacancies within a trapping layer of a field-effect transistor (FET), thereby providing control and variation of threshold voltages of the transistor. Various threshold voltages may be assigned a data value, providing the ability to store one or more bits of data in a single memory cell. To control the threshold voltage, the oxygen vacancies may be manipulated by trapping electrons within the vacancies, freeing trapped electrons from the vacancies, moving the vacancies within the trapping layer and annihilating the vacancies.
摘要翻译：单晶体管存储器件通过操纵场效应晶体管（FET）的俘获层内的氧空位来促进非易失性数据存储，从而提供晶体管的阈值电压的控制和变化。可以为各种阈值电压分配数据值，提供将一个或多个位数据存储在单个存储器单元中的能力。为了控制阈值电压，可以通过在空位内捕获电子来操纵氧空位，从空位释放被俘获的电子，移动捕获层内的空位并湮灭空位。

58. 发明申请

US20070210390A1 Method of making an isolation trench and resulting isolation trench 有权
标题翻译：制造隔离沟槽和产生的隔离沟槽的方法
公开(公告)号：US20070210390A1
公开(公告)日：2007-09-13
申请号：US11714220
申请日：2007-03-06
申请人： Sukesh Sandhu , Gurtej Sandhu
发明人： Sukesh Sandhu , Gurtej Sandhu
IPC分类号： H01L29/76
CPC分类号： H01L21/76232 , H01L21/76229
摘要： A method of forming and resulting isolation region, which allows for densification of an oxide layer in the isolation region. One exemplary embodiment of the method includes the steps of forming a first trench, forming an oxide layer on the bottom and sidewalls of the trench, forming nitride spacers on the lined trench, and thereafter etching the silicon beneath the first trench to form a second trench area. An oxide layer is then deposited to fill the second trench. Densificiation of the isolation region is possible because the silicon is covered with nitride, and therefore will not be oxidized. Light etches are then performed to etch the oxide and nitride spacer area in the first trench region. A conventional oxide fill process can then be implemented to complete the isolation region.
摘要翻译：形成和产生的隔离区域的方法，其允许隔离区域中的氧化物层致密化。该方法的一个示例性实施例包括以下步骤：形成第一沟槽，在沟槽的底部和侧壁上形成氧化物层，在衬里的沟槽上形成氮化物间隔物，之后蚀刻第一沟槽下方的硅以形成第二沟槽区。然后沉积氧化物层以填充第二沟槽。隔离区的密集是可能的，因为硅被氮化物覆盖，因此不会被氧化。然后进行光蚀刻以蚀刻第一沟槽区域中的氧化物和氮化物间隔物区域。然后可以实现常规氧化物填充过程以完成隔离区域。

59. 发明申请

US20070190463A1 METHOD TO ALIGN MASK PATTERNS 有权
标题翻译：对齐掩蔽图案的方法
公开(公告)号：US20070190463A1
公开(公告)日：2007-08-16
申请号：US11691192
申请日：2007-03-26
申请人： Gurtej Sandhu , Randal Chance , William Rericha
发明人： Gurtej Sandhu , Randal Chance , William Rericha
IPC分类号： G03C5/00
CPC分类号： H01L23/50 , H01L21/0337 , H01L21/0338 , H01L21/32139 , H01L27/1052 , H01L27/10894 , H01L2924/0002 , Y10S438/95 , Y10S438/975 , H01L2924/00
摘要： Alignment tolerances between narrow mask lines, for forming interconnects in the array region of an integrated circuit, and wider mask lines, for forming interconnects in the periphery of the integrated circuit, are increased. The narrow mask lines are formed by pitch multiplication and the wider mask lines are formed by photolithography. The wider mask lines and are aligned so that one side of those lines is flush with or inset from a corresponding side of the narrow lines. Being wider, the opposite sides of the wider mask lines protrude beyond the corresponding opposite sides of the narrow mask lines. The wider mask lines are formed in negative photoresist having a height less than the height of the narrow mask lines. Advantageously, the narrow mask lines can prevent expansion of the mask lines in one direction, thus increasing alignment tolerances in that direction. In the other direction, use of photolithography and a shadowing effect caused by the relative heights of the photoresist and the narrow mask lines causes the wider mask lines to be formed with a rounded corner, thus increasing alignment tolerances in that direction by increasing the distance to a neighboring narrow mask line.
摘要翻译：在集成电路的阵列区域中用于形成互连的窄掩模线之间的对准公差和用于在集成电路的外围形成互连的较宽的掩模线增加。通过间距倍增形成窄屏蔽线，通过光刻法形成较宽的掩模线。较宽的掩模线对准，使得这些线的一侧与窄线的相应侧齐平或嵌入。较宽的掩模线的相对侧突出超过窄掩模线的对应的相对侧。较宽的掩模线形成在具有小于窄掩模线的高度的高度的负光致抗蚀剂中。有利地，窄掩模线可以防止掩模线在一个方向上的膨胀，从而增加该方向上的对准公差。在另一个方向上，使用光刻法和由光致抗蚀剂和窄掩模线的相对高度引起的阴影效应导致较宽的掩模线形成有圆角，从而通过增加到该方向的距离来增加该方向上的对准公差相邻的窄屏线。

60. 发明申请

US20070148984A1 METHOD FOR INTEGRATED CIRCUIT FABRICATION USING PITCH MULTIPLICATION 失效
标题翻译：使用PITCH MULTIPLICATION的集成电路制造方法
公开(公告)号：US20070148984A1
公开(公告)日：2007-06-28
申请号：US11683518
申请日：2007-03-08
申请人： Mirzafer Abatchev , Gurtej Sandhu , Luan Tran , William Rericha , D. Durcan
发明人： Mirzafer Abatchev , Gurtej Sandhu , Luan Tran , William Rericha , D. Durcan
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/0337 , H01L21/0332 , H01L21/0338 , H01L21/3081 , H01L21/3086 , H01L21/3088 , H01L21/31144 , H01L21/32139 , Y10S438/947 , Y10S438/95
摘要： Different sized features in the array and in the periphery of an integrated circuit are patterned on a substrate in a single step. In particular, a mixed pattern, combining two separately formed patterns, is formed on a single mask layer and then transferred to the underlying substrate. The first of the separately formed patterns is formed by pitch multiplication and the second of the separately formed patterns is formed by conventional photolithography. The first of the separately formed patterns includes lines that are below the resolution of the photolithographic process used to form the second of the separately formed patterns. These lines are made by forming a pattern on photoresist and then etching that pattern into an amorphous carbon layer. Sidewall pacers having widths less than the widths of the un-etched parts of the amorphous carbon are formed on the sidewalls of the amorphous carbon. The amorphous carbon is then removed, leaving behind the sidewall spacers as a mask pattern. Thus, the spacers form a mask having feature sizes less than the resolution of the photolithography process used to form the pattern on the photoresist. A protective material is deposited around the spacers. The spacers are further protected using a hard mask and then photoresist is formed and patterned over the hard mask. The photoresist pattern is transferred through the hard mask to the protective material. The pattern made out by the spacers and the temporary material is then transferred to an underlying amorphous carbon hard mask layer. The pattern, having features of difference sizes, is then transferred to the underlying substrate.
摘要翻译：集成电路的阵列和周边中的不同尺寸的特征在单个步骤中在衬底上图案化。特别地，组合两个单独形成的图案的混合图案形成在单个掩模层上，然后转移到下面的基底。单独形成的图案中的第一个通过间距倍增形成，并且通过常规光刻形成第二个单独形成的图案。单独形成的图案中的第一个包括低于用于形成第二个单独形成的图案的光刻工艺的分辨率的线。这些线通过在光致抗蚀剂上形成图案然后将该图案刻蚀成无定形碳层而制成。在无定形碳的侧壁上形成宽度小于无定形碳的未蚀刻部分的宽度的侧壁盘。然后去除无定形碳，留下侧壁间隔物作为掩模图案。因此，间隔物形成具有小于用于在光致抗蚀剂上形成图案的光刻工艺的分辨率的特征尺寸的掩模。保护材料沉积在间隔物周围。使用硬掩模进一步保护间隔物，然后在硬掩模上形成并图案化光致抗蚀剂。光致抗蚀剂图案通过硬掩模转印到保护材料上。然后将由间隔物和临时材料制成的图案转移到下面的无定形碳硬掩模层。具有不同尺寸特征的图案然后被转移到下面的基底。

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