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    • 58. 发明授权
    • Nonvolatile semiconductor memory device
    • 非易失性半导体存储器件
    • US08575590B2
    • 2013-11-05
    • US13038771
    • 2011-03-02
    • Koichi MuraokaHiroyuki Nagashima
    • Koichi MuraokaHiroyuki Nagashima
    • H01L47/00H01L27/10H01L29/06
    • G11C13/003G11C13/0004G11C13/0007G11C13/0014G11C2213/31G11C2213/32G11C2213/56G11C2213/71G11C2213/76H01L27/101H01L27/2418H01L27/2463
    • According to one embodiment, there is provided a nonvolatile semiconductor memory device including a first interconnection layer, memory cell modules each of which is formed by laminating a non-ohmic element layer with an MIM structure having an insulating film sandwiched between metal films and a variable resistance element layer, and a second interconnection layer formed on the memory cell modules, the insulating film of the non-ohmic element layer includes plural layers whose electron barriers and dielectric constants are different, or contains impurity atoms that form defect levels in the insulating film or contains semiconductor or metal dots. The nonvolatile semiconductor memory device using non-ohmic elements and variable resistance elements in which memory cells can be miniaturized and formed at low temperatures is realized by utilizing the above structures.
    • 根据一个实施例,提供了一种非易失性半导体存储器件,其包括第一互连层,存储单元模块,每个存储单元模块通过层叠具有MIM结构的非欧姆元件层而形成,所述MIM结构具有夹在金属膜之间的绝缘膜和可变 电阻元件层和形成在存储单元模块上的第二互连层,非欧姆元件层的绝缘膜包括其电子势垒和介电常数不同的多个层,或包含在绝缘膜中形成缺陷水平的杂质原子 或包含半导体或金属点。 通过利用上述结构,实现了使用非欧姆元件和可变电阻元件的非易失性半导体存储器件,其中存储单元可以在低温下小型化并形成。
    • 59. 发明授权
    • Semiconductor memory device
    • 半导体存储器件
    • US08441040B2
    • 2013-05-14
    • US12886090
    • 2010-09-20
    • Yoichi MinemuraHiroyuki Nagashima
    • Yoichi MinemuraHiroyuki Nagashima
    • H01L23/52
    • H01L27/2481H01L27/0688H01L27/2409H01L45/085H01L45/1233H01L45/147
    • A semiconductor memory device according to an embodiment includes: a cell array block having, above a semiconductor substrate, a plurality of first and second wirings intersecting with one another, and a plurality of memory cells, the first and second wirings being separately formed in a plurality of layers in a perpendicular direction to the semiconductor substrate; and a first via wiring, connecting the first wiring in an n1-th layer of the cell array block with the first wiring in an n2-th layer, the semiconductor substrate or another metal wiring, and extending in a laminating direction of the cell array block. The first via wiring has a cross section orthogonal to the laminating direction of the cell array block. The cross section has an elliptical shape and a longer diameter in a direction perpendicular to the first wiring direction.
    • 根据实施例的半导体存储器件包括:单元阵列块,其在半导体衬底上方具有彼此相交的多个第一和第二布线,以及多个存储单元,所述第一和第二布线分别形成在 在与半导体衬底垂直的方向上的多个层; 以及第一通孔布线,将第一电极阵列块的第n1层中的第一布线与第n2层的第一布线,半导体基板或其他金属布线连接,并且在电池阵列的层叠方向上延伸 块。 第一通孔布线具有与单元阵列块的层叠方向正交的截面。 横截面在垂直于第一布线方向的方向上具有椭圆形状和较长直径。
    • 60. 发明授权
    • Semiconductor memory device and method of manufacturing the same
    • 半导体存储器件及其制造方法
    • US08222677B2
    • 2012-07-17
    • US12399376
    • 2009-03-06
    • Yasuyuki BabaHiroyuki Nagashima
    • Yasuyuki BabaHiroyuki Nagashima
    • H01L29/00
    • H01L27/2409G11C13/0004G11C13/0007G11C13/0011G11C2213/31G11C2213/71H01L27/2481H01L45/085H01L45/1233H01L45/147H01L45/1675
    • A semiconductor memory device comprises a semiconductor substrate; a cell array block formed on the semiconductor substrate and including plural stacked cell array layers each comprising a plurality of first lines, a plurality of second lines crossing the plurality of first lines, and memory cells connected at intersections of the first and second lines between both lines; and a plurality of contact plugs extending in the stack direction of the cell array layers to connect between the first lines, between the second lines, between the first or second line and the semiconductor substrate, or between the first or second line and another metal line, in the cell array layers. The first or second line in a certain one of the cell array layers has a contact connector making contact with both sides of the contact plug.
    • 半导体存储器件包括半导体衬底; 形成在所述半导体衬底上的单元阵列块,并且包括多个堆叠的单元阵列层,每个堆叠的单元阵列层包括多个第一线,与所述多条第一线交叉的多个第二线,以及连接在所述第一和第二线之间的第一和第二线的交点处的存储单元 线条 以及在单元阵列层的堆叠方向上延伸的多个接触插塞,以在第一线之间,第二线之间,第一线或第二线与半导体衬底之间,或第一线或第二线与另一金属线之间连接 ,在单元阵列层。 电池阵列层中某一个的第一或第二线具有与接触插塞的两侧接触的接触连接器。