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51. 发明申请

US20120075251A1 PIXEL CIRCUIT AND DISPLAY DEVICE 有权
标题翻译：像素电路和显示设备
公开(公告)号：US20120075251A1
公开(公告)日：2012-03-29
申请号：US13375614
申请日：2010-06-07
申请人： Yoshimitsu Yamauchi
发明人： Yoshimitsu Yamauchi
IPC分类号： G09G5/00 , G06F3/045
CPC分类号： G09G3/3659 , G09G3/3258 , G09G2300/0866 , G09G2300/0876 , G09G2330/021
摘要： An embodiment of the present invention provides a liquid crystal display device. In each pixel circuit, a pixel electrode is connected to a source line via a third transistor. When a refreshing circuit performs a refreshing operation, a boosting signal line is supplied with a voltage pulse. If the pixel electrode is at a high voltage level at this time point, a voltage at a node is boosted and a first transistor turns ON to supply a refreshing voltage to the pixel electrode. If the pixel electrode is at a low voltage level, there is no boost, and the first transistor stays in OFF state, so a node assumes a voltage which is given by an off-resistance ratio of the first and the third transistors, and this voltage is supplied to the pixel electrode.
摘要翻译：本发明的实施例提供一种液晶显示装置。在每个像素电路中，像素电极经由第三晶体管连接到源极线。当刷新电路进行刷新操作时，向升压信号线提供电压脉冲。如果在该时间点像素电极处于高电压电平，则节点处的电压被升高，并且第一晶体管导通以向像素电极提供刷新电压。如果像素电极处于低电压电平，则不存在升压，并且第一晶体管保持截止状态，因此节点呈现由第一和第三晶体管的截止电阻比给出的电压，并且这个电压被提供给像素电极。

52. 发明授权

US07326991B2 Nonvolatile semiconductor memory and method of operating the same 有权
标题翻译：非易失性半导体存储器及其操作方法
公开(公告)号：US07326991B2
公开(公告)日：2008-02-05
申请号：US11157973
申请日：2005-06-22
申请人： Yoshimitsu Yamauchi
发明人： Yoshimitsu Yamauchi
IPC分类号： G11C16/04
CPC分类号： H01L27/11521 , G11C16/0433 , H01L27/115
摘要： A nonvolatile semiconductor memory having a memory cell comprises: a semiconductor substrate having a pair of trenches formed on a surface thereof; first electrodes formed in a pair of trenches through the intervention of a first insulating film, respectively; a second electrode formed on the semiconductor substrate between the trenches through the intervention of a second insulating film; and a third electrode formed on the second electrode through the intervention of a third insulating film.
摘要翻译：具有存储单元的非易失性半导体存储器包括：具有在其表面上形成的一对沟槽的半导体衬底; 分别通过介入第一绝缘膜形成在一对沟槽中的第一电极; 通过介入第二绝缘膜形成在沟槽之间的半导体衬底上的第二电极; 以及通过第三绝缘膜介入形成在第二电极上的第三电极。

53. 发明申请

US20050135161A1 Semiconductor readout circuit 失效
标题翻译：半导体读出电路
公开(公告)号：US20050135161A1
公开(公告)日：2005-06-23
申请号：US11013119
申请日：2004-12-14
申请人： Nobuhiko Ito , Kaoru Yamamoto , Yoshimitsu Yamauchi
发明人： Nobuhiko Ito , Kaoru Yamamoto , Yoshimitsu Yamauchi
IPC分类号： G11C11/419 , G11C7/02 , G11C7/06 , G11C7/08 , G11C7/10 , G11C7/12 , G11C16/06 , G11C5/00
CPC分类号： G11C7/1069 , G11C7/062 , G11C7/1051 , G11C7/12
摘要： A semiconductor readout circuit reads out a potential of each of plural data lines by comparing the potential with a potential of a common reference data line, using a sense amplifier provided for each of the data lines. This semiconductor readout circuit has a current control circuit provided for each of the data lines. The current control circuit controls the potential of the corresponding one of the data lines so that a potential difference between the potential of the corresponding data line and the potential of the reference data line can be reduced based on an output as to the potential difference detected by the sense amplifier.
摘要翻译：半导体读出电路通过使用为每条数据线提供的读出放大器来比较电位与公共参考数据线的电位，来读出多条数据线中的每一条线的电位。该半导体读出电路具有为每条数据线设置的电流控制电路。电流控制电路控制对应的一条数据线的电位，使得相应的数据线的电位与参考数据线的电位之间的电位差可以基于关于由读出放大器。

54. 发明授权

US06392927B2 Cell array, operating method of the same and manufacturing method of the same 失效
标题翻译：电池阵列，操作方法相同，制造方法相同
公开(公告)号：US06392927B2
公开(公告)日：2002-05-21
申请号：US09789726
申请日：2001-02-22
申请人： Yoshimitsu Yamauchi
发明人： Yoshimitsu Yamauchi
IPC分类号： G11C1604
CPC分类号： H01L27/11521 , G11C16/0433 , G11C16/0491 , G11C16/3427 , H01L27/115
摘要： A cell array comprising nonvolatile memory cells having; a floating gate formed on a semiconductor substrate with the intervention of a first insulating film; a split gate formed with the intervention of a second insulating film at a predetermined distance from the floating gate; a control gate formed at least on the floating gate with the intervention of a third insulating film; and an impurity diffusion layer formed in a surface layer of the semiconductor substrate and capacitively coupled with an edge of the floating gate on an opposite side to the split gate in an X direction in parallel with a channel direction; wherein two or more cells are arranged in matrix along the X direction and a Y direction vertical to the X direction, the floating gates and the split gates are alternately arranged in the X direction and the impurity diffusion layer of one cell is capacitively coupled with a split gate of another cell adjacent to said one cell in the X direction, the control gates of the cells arranged along the X direction are commonly connected along the X direction, the impurity diffusion layers of the cells arranged along the Y direction are commonly connected along the Y direction, and the split gates commonly connected along the Y direction are also commonly connected along the X direction through at least one conductive layer.
摘要翻译：一种包括非易失性存储单元的单元阵列，具有：介于第一绝缘膜之间的形成在半导体衬底上的浮栅; 形成有与浮动栅极隔开预定距离的第二绝缘膜介入的分路门; 至少在所述浮动栅极上形成的第三绝缘膜介入的控制栅极; 以及杂质扩散层，其形成在所述半导体衬底的表面层中，并且与所述浮栅的边缘在与沟道方向平行的X方向上与所述分离栅极相反的一侧电容耦合; 其中两个或更多个单元沿着X方向和垂直于X方向的Y方向排列成矩阵，浮置栅极和分离栅极在X方向上交替排列，并且一个单元的杂质扩散层与电容耦合在X方向上与所述一个单元相邻的另一个单元的分离栅极沿X方向排列的单元的控制栅极沿着X方向共同连接，沿Y方向排列的单元的杂质扩散层共同连接 Y方向和沿着Y方向共同连接的分割门也通过至少一个导电层沿X方向共同连接。

55. 发明授权

US5877054A Method of making nonvolatile semiconductor memory 失效
公开(公告)号：US5877054A
公开(公告)日：1999-03-02
申请号：US672666
申请日：1996-06-28
申请人： Yoshimitsu Yamauchi
发明人： Yoshimitsu Yamauchi
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/115
CPC分类号： H01L27/11521 , G11C16/0491 , H01L27/115
摘要： The nonvolatile semiconductor memory of this invention includes: a semiconductor substrate; a plurality of memory cells formed in a matrix on the semiconductor substrate, each of the memory cells including a first insulating film formed on the semiconductor substrate, a floating gate formed on the first insulating film, and a control gate formed on the floating gate via a second insulating film sandwiched therebetween, a source diffusion region, and a drain diffusion region; a diffusion layer formed in a portion of the semiconductor substrate located between two of the memory cells adjacent in a first direction, the diffusion layer including the drain diffusion region for one of the two memory cells and the source diffusion region for the other memory cell; a word line formed by connecting the control gates of the memory cells lined in the first direction; and a bit line formed by connecting the diffusion layers lined in a second direction substantially perpendicular to the first direction, wherein the memory cells have a structure in which a tunnel current flows between the drain diffusion region and the floating gate of one of the two adjacent memory cells via the first insulating film when a predetermined voltage is applied to the diffusion layers and no tunnel current flows between the diffusion layer and the floating gate of the other memory cell.

56. 发明授权

US5422297A Method for forming a semiconductor device 失效
标题翻译：半导体器件形成方法
公开(公告)号：US5422297A
公开(公告)日：1995-06-06
申请号：US254574
申请日：1994-06-06
申请人： Yoshimitsu Yamauchi
发明人： Yoshimitsu Yamauchi
IPC分类号： H01L27/112 , H01L21/8242 , H01L21/8246 , H01L21/70
CPC分类号： H01L27/10873
摘要： A method for forming a semiconductor device comprising steps of: (i) depositing an oxide film and then an anti-oxide film on a semiconductor substrate of a first conductive type, (ii) removing the anti-oxide film provided in a prescribed region where a field oxide film is to be formed, followed by forming a resist on the semiconductor substrate including the anti-oxide film in a prescribed region where a buried bit line is to be formed, (iii) implanting ions of a second conductive type to the semiconductor substrate using the oxide film and the resist as a mask, (iv) forming the field oxide film in the prescribed region by LOCOS method, followed by forming a gate electrode on the semiconductor substrate, (v) implanting ions of the second conductive type to the semiconductor substrate using the gate electrode as a mask and subjecting the resulting semiconductor substrate to a thermal treatment, thereby forming a source/drain region to which the buried bit line is connected.
摘要翻译：一种形成半导体器件的方法，包括以下步骤：（i）在第一导电类型的半导体衬底上沉积氧化膜，然后沉积抗氧化膜，（ii）除去在规定区域中设置的抗氧化膜，形成场氧化膜，然后在要形成掩埋位线的规定区域中的包含抗氧化膜的半导体衬底上形成抗蚀剂，（iii）将第二导电类型的离子注入到使用氧化膜和抗蚀剂作为掩模的半导体衬底，（iv）通过LOCOS法在规定区域中形成场氧化膜，然后在半导体衬底上形成栅电极，（v）注入第二导电类型的离子使用栅极电极作为掩模对半导体基板进行热处理，从而形成与埋置的位线连接的源极/漏极区域。

57. 发明授权

US5401993A Non-volatile memory 失效
标题翻译：非易失性存储器
公开(公告)号：US5401993A
公开(公告)日：1995-03-28
申请号：US083873
申请日：1993-06-30
申请人： Yoshimitsu Yamauchi , Kenichi Tanaka , Keizo Sakiyama
发明人： Yoshimitsu Yamauchi , Kenichi Tanaka , Keizo Sakiyama
IPC分类号： H01L21/8247 , G11C17/16 , H01L21/8246 , H01L27/112 , H01L27/115 , H01L29/788 , H01L29/792 , H01L27/02 , H01L29/68 , H01L29/78 , H01L29/92
CPC分类号： G11C17/16 , H01L27/112 , H01L27/115
摘要： A non-volatile memory includes a single transistor having a semiconductor substrate, source and drain diffusion layers formed on a surface of the semiconductor substrate, and a gate electrode provided on the semiconductor substrate with a gate insulating film interposed between them. The non-volatile memory further includes a programmable insulating film provided in self-alignment between the gate electrode and at least one of the source and drain diffusion layers and the programmable insulating film is broken down by a voltage applied to the gate electrode so as to execute programming.
摘要翻译：非易失性存储器包括具有半导体衬底的单晶体管，形成在半导体衬底的表面上的源极和漏极扩散层，以及设置在半导体衬底上的栅电极，栅极绝缘膜置于它们之间。非易失性存储器还包括设置在栅极电极和源极和漏极扩散层中的至少一个之间自对准的可编程绝缘膜，并且可编程绝缘膜被施加到栅电极的电压分解，从而执行编程。

58. 发明授权

US5268585A Non-volatile memory and method of manufacturing the same 失效
标题翻译：非易失性存储器及其制造方法
公开(公告)号：US5268585A
公开(公告)日：1993-12-07
申请号：US896010
申请日：1992-06-09
申请人： Yoshimitsu Yamauchi
发明人： Yoshimitsu Yamauchi
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8247 , H01L29/423 , H01L29/788 , H01L29/68 , H01L21/265
CPC分类号： H01L27/11519 , H01L21/28273 , H01L27/11521 , H01L29/42328 , H01L29/66825 , H01L29/7885
摘要： A non-volatile memory comprises an auxiliary gate of polysilicon provided on a Si substrate having a gate insulating film and a field oxidation film; a floating gate which is provided on a side wall of the auxiliary gate lying in an active region with a small piece of a first insulating film interposed between them and which is formed by etchback of useless part of a polysilicon side wall spacer; and a control gate of polysilicon provided at least on the floating gate including a second insulating film interposed between them; the floating gate being formed in self-alignment to the control gate.
摘要翻译：非易失性存储器包括设置在具有栅极绝缘膜和场氧化膜的Si衬底上的多晶硅辅助栅极; 设置在位于有源区域的辅助栅极侧壁上的浮置栅极，其中插入有位于它们之间的第一绝缘膜的小片，并且通过蚀刻多晶硅侧壁间隔物的无用部分形成; 以及至少设置在所述浮置栅极上的多晶硅控制栅极，包括插在其间的第二绝缘膜; 浮动栅极与控制栅极自对准地形成。

59. 发明授权

US5139964A Method for forming isolation region of semiconductor device 失效
标题翻译：形成半导体器件隔离区域的方法
公开(公告)号：US5139964A
公开(公告)日：1992-08-18
申请号：US646203
申请日：1991-01-28
申请人： Shigeo Onishi , Kenichi Tanaka , Yoshimitsu Yamauchi , Keizo Sakiyama
发明人： Shigeo Onishi , Kenichi Tanaka , Yoshimitsu Yamauchi , Keizo Sakiyama
IPC分类号： H01L21/76 , H01L21/308 , H01L21/316 , H01L21/32 , H01L21/762
CPC分类号： H01L21/3085 , H01L21/32 , H01L21/7621 , Y10S438/944
摘要： An improved LOCOS method for forming an isolation region with a higher breakdown voltage and a reduced width in a semiconductor device, comprising the steps of:(a) forming on a silicon substrate a silicon nitride layer having a predetermined pattern and a tapered-slant side wall, between the silicon nitride layer and the silicon substrate being formed a silicon oxide layer,(b) subjecting the silicon substrate to an isotropic etching using the silicon nitride layer as a mask to form a recess on the substrate, the recess extending to and under the side wall of the silicon nitride layer, and(c) forming a channel stopper region by implanting an impurity into the silicon substrate through the recess-formed surface, and thereafter growing and forming a LOCOS layer on the recess-formed surface to obtain an isolation region.
摘要翻译：一种用于在半导体器件中形成具有较高击穿电压和减小的宽度的隔离区域的改进的LOCOS方法，包括以下步骤：（a）在硅衬底上形成具有预定图案和倾斜斜面的氮化硅层在氮化硅层和硅衬底之间形成硅氧化物层，（b）使用氮化硅层作为掩模对硅衬底进行各向同性蚀刻，以在衬底上形成凹部，在氮化硅层的侧壁下方，（c）通过凹陷形成表面向硅衬底中注入杂质形成通道阻挡区域，然后在凹形形成表面上生长并形成LOCOS层以获得隔离区。

60. 发明授权

US5108783A Process for producing semiconductor devices 失效
标题翻译：半导体器件的制造方法
公开(公告)号：US5108783A
公开(公告)日：1992-04-28
申请号：US454368
申请日：1989-12-21
申请人： Makoto Tanigawa , Hidehisa Tateoka , Keizo Sakiyama , Shigeo Ohnishi , Yoshimitsu Yamauchi , Kenichi Tanaka
发明人： Makoto Tanigawa , Hidehisa Tateoka , Keizo Sakiyama , Shigeo Ohnishi , Yoshimitsu Yamauchi , Kenichi Tanaka
IPC分类号： H01L21/76 , H01L21/08 , H01L21/74 , H01L21/762 , H01L21/763 , H01L27/08
CPC分类号： H01L21/763 , H01L21/74 , H01L21/76202 , H01L21/76237
摘要： A process for producing a semiconductor device including the steps of:(a) forming a trench in a semiconductor substrate at a portion thereof where an isolating zone is to be formed,(b) doping the substrate with an impurity element from the inner wall thereof defining the trench to form a high-concentration impurity diffused region, and(c) etching the bottom surface of the trench to increase the depth of the trench, thereby separating the impurity diffused region to form the isolating zone,which is useful for the fabrication of semiconductor devices of high integration with low well resistance.
摘要翻译：一种制造半导体器件的方法，包括以下步骤：（a）在半导体衬底的形成隔离区的部分形成沟槽，（b）从其内壁掺杂杂质元素的衬底限定沟槽以形成高浓度杂质扩散区域，以及（c）蚀刻沟槽的底表面以增加沟槽的深度，由此分离杂质扩散区域以形成隔离区，其可用于制造的半导体器件，具有低阱电阻的高集成度。

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