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51. 发明申请

US20060214681A1 Impedance matching circuit, input-output circuit and semiconductor test apparatus 失效
标题翻译：阻抗匹配电路，输入输出电路和半导体测试装置
公开(公告)号：US20060214681A1
公开(公告)日：2006-09-28
申请号：US11326182
申请日：2006-01-05
申请人： Shoji Kojima
发明人： Shoji Kojima
IPC分类号： H03K17/16
CPC分类号： H04L25/0278
摘要： A characteristic test of a DUT having a weak transmission line driving capability can be performed with a simple configuration at a low cost. An impedance matching circuit 90 is connected between a transmission line 70 and a DUT 10 in an input-output circuit 80 of a semiconductor test apparatus 1. The impedance matching circuit 90 is constituted of: a resistance (a first resistance Rtp 81-1 and a second resistance Rts 81-2); an analog computing unit having two inputs and one output (a first analog computing unit 82-1 and a second analog computing unit 82-2) which multiplies a voltage from one end of this resistance by a predetermined number, subtracts a voltage at the other end of the resistance from the voltage multiplied by the predetermined number and outputs a voltage obtained by this subtraction; and a buffer (a first buffer 83-1 and a second buffer 83-2) which outputs an output signal from this analog computing unit with a low impedance. The impedance matching circuit 90 outputs an output signal from the DUT 10 with a low impedance, and can drive the transmission line 70.
摘要翻译：可以以简单的结构以低成本执行具有弱传输线驱动能力的DUT的特性测试。阻抗匹配电路90连接在半导体测试装置1的输入输出电路80中的传输线70和DUT 10之间。阻抗匹配电路90由以下部分构成：电阻（第一电阻Rtp 81-1和第二阻力Rts 81-2）; 具有两个输入和一个输出（第一模拟计算单元82-1和第二模拟计算单元82-2）的模拟计算单元，其将来自该电阻的一端的电压乘以预定数量，减去另一个处的电压从电压乘以预定数量的电阻结束，并输出通过该减法获得的电压; 以及以低阻抗输出来自该模拟计算单元的输出信号的缓冲器（第一缓冲器83-1和第二缓冲器83-2）。阻抗匹配电路90以低阻抗输出来自DUT 10的输出信号，并且可以驱动传输线70。

52. 发明授权

US07012444B2 Semiconductor tester 失效
标题翻译：半导体测试仪
公开(公告)号：US07012444B2
公开(公告)日：2006-03-14
申请号：US10848823
申请日：2004-05-19
申请人： Shoji Kojima
发明人： Shoji Kojima
IPC分类号： G01R1/04
CPC分类号： G01R31/31922
摘要： A semiconductor tester comprising a driver circuit for generating a predetermined driver waveform without using a coil device. The driver circuit provided in a pin electronics receives a waveform-shaped signal to be supplied to an IC pin of a device under test (DUT) and converts the amplitude to an amplitude of predetermined level. The driver output pulse outputted from the output terminal of the driver and having the converted amplitude to the IC pin of the DUT. The tester has pulse compensating means for compensating the individual waveforms of the rising and falling edges of the driver output pulse in a predetermined way.
摘要翻译：一种半导体测试器，包括用于在不使用线圈装置的情况下产生预定驱动器波形的驱动电路。设置在引脚电子装置中的驱动器电路接收要提供给被测器件（DUT）的IC引脚的波形信号，并将振幅转换为预定电平的幅度。从驱动器的输出端子输出的驱动器输出脉冲具有转换的幅度到DUT的IC引脚。测试器具有用于以预定方式补偿驱动器输出脉冲的上升沿和下降沿的各个波形的脉冲补偿装置。

53. 发明申请

US20060010360A1 Semiconductor testing apparatus and method of testing semiconductor 有权
标题翻译：半导体测试仪器和半导体测试方法
公开(公告)号：US20060010360A1
公开(公告)日：2006-01-12
申请号：US11176300
申请日：2005-07-08
申请人： Shoji Kojima
发明人： Shoji Kojima
IPC分类号： G01R31/28
CPC分类号： G01R31/31924 , G01R31/31932
摘要： A semiconductor testing apparatus, includes a test signal generating unit that generates a test signal corresponding to a test pattern to output the generated test signal to a device under test (DUT); a comparison signal generating unit that generates a comparison signal by combining a reference signal and the test signal; and a comparing unit that compares a response signal, which is output from the DUT in response to the input of the test signal, and the reference signal by offsetting the test signal contained in a composite signal of the test signal and the response signal and the test signal contained in the comparison signal. The DUT is determined to be defective or not based on a result of comparison by the comparing unit.
摘要翻译：一种半导体测试装置，包括测试信号产生单元，其生成与测试图案相对应的测试信号，以将生成的测试信号输出到被测器件（DUT）; 比较信号生成单元，其通过组合参考信号和所述测试信号来生成比较信号; 以及比较单元，其通过将测试信号和响应信号的复合信号中包含的测试信号进行偏移来比较来自DUT的响应信号，以响应于测试信号的输入和参考信号，测试信号包含在比较信号中。基于比较单元的比较结果，DUT被确定为有缺陷。

54. 发明申请

US20050225349A1 Semiconductor tester 失效
标题翻译：半导体测试仪
公开(公告)号：US20050225349A1
公开(公告)日：2005-10-13
申请号：US10848823
申请日：2004-05-19
申请人： Shoji Kojima
发明人： Shoji Kojima
IPC分类号： G01R31/319 , G01R31/28
CPC分类号： G01R31/31922
摘要： A semiconductor tester comprising a driver circuit for generating a predetermined driver waveform without using a coil device. The driver circuit provided in a pin electronics receives a waveform-shaped signal to be supplied to an IC pin of a device under test (DUT) and converts the amplitude to an amplitude of predetermined level. The driver output pulse outputted from the output terminal of the driver and having the converted amplitude to the IC pin of the DUT. The tester has pulse compensating means for compensating the individual waveforms of the rising and falling edges of the driver output pulse in a predetermined way.
摘要翻译：一种半导体测试器，包括用于在不使用线圈装置的情况下产生预定驱动器波形的驱动电路。设置在引脚电子装置中的驱动器电路接收要提供给被测器件（DUT）的IC引脚的波形信号，并将振幅转换为预定电平的幅度。从驱动器的输出端子输出的驱动器输出脉冲具有转换的幅度到DUT的IC引脚。测试器具有用于以预定方式补偿驱动器输出脉冲的上升沿和下降沿的各个波形的脉冲补偿装置。

55. 发明授权

US08704692B2 Digital to analog converter 失效
标题翻译：数模转换器
公开(公告)号：US08704692B2
公开(公告)日：2014-04-22
申请号：US13360610
申请日：2012-01-27
申请人： Ken'ichi Sawada , Shoji Kojima
发明人： Ken'ichi Sawada , Shoji Kojima
IPC分类号： H03M1/80
CPC分类号： H03M1/068 , H03M1/808
摘要： N upper-side resistors and N lower-side resistors are severally associated with respective bits of a digital input code. Each resistance value is weighted in an essentially binary manner according to the corresponding bit. N upper-side switches are each arranged in parallel with a corresponding upper-side resistor, and each is configured such that its on/off state is controlled according to the corresponding bit. N lower-side switches are each arranged in parallel with a corresponding lower-side resistor, and each is configured such that its on/off state is controlled according to logical inversion of the corresponding bit.
摘要翻译： N个上侧电阻器和N个下侧电阻器分别与数字输入代码的各个位相关联。每个电阻值根据相应的位以基本上二进制的方式进行加权。 N个上侧开关各自与相应的上侧电阻并联布置，并且每个被配置为使得其根据相应位的控制。 N个下侧开关各自与相应的下侧电阻器并联布置，并且每个被配置为使得其根据相应位的逻辑反相来控制其导通/截止状态。

56. 发明授权

US08502549B2 Test apparatus and driver circuit 失效
标题翻译：测试设备和驱动电路
公开(公告)号：US08502549B2
公开(公告)日：2013-08-06
申请号：US12957184
申请日：2010-11-30
申请人： Shoji Kojima , Toshiyuki Okayasu
发明人： Shoji Kojima , Toshiyuki Okayasu
IPC分类号： G01R31/00 , G01R31/319
CPC分类号： G01R31/31924
摘要： A test apparatus includes: a driver circuit that supplies, to a device under test, a test signal corresponding to an input signal; and a judging section that judges pass/fail of the device under test, based on the load voltage or the load current supplied to the device under test when supplying a test signal of a constant current or a constant voltage to the device under test from the driver circuit, where the driver circuit includes: a driver section that outputs the test signal; a supply current detecting section that detects a supply current supplied to the driver section; and an output control section that controls a voltage or a current of the test signal outputted from the driver section to the predetermined value, based on the supply current detected by the supply current detecting section.
摘要翻译：测试装置包括：驱动器电路，向被测设备提供对应于输入信号的测试信号; 以及判断部，其根据在向所述被测试装置供给恒定电流或恒定电压的测试信号的负载电压或提供给所述被测定装置的负载电流时，判定所述被测试器件的通过/失败。驱动器电路，其中所述驱动器电路包括：驱动器部分，其输出所述测试信号; 电源电流检测部，其检测供给到所述驱动器部的电源电流; 以及输出控制部，其基于由所述供给电流检测部检测出的供给电流，将从所述驱动部输出的所述测试信号的电压或电流控制为所述规定值。

57. 发明申请

US20120153975A1 DRIVER CIRCUIT 审中-公开
标题翻译：驱动电路
公开(公告)号：US20120153975A1
公开(公告)日：2012-06-21
申请号：US13324984
申请日：2011-12-13
申请人： Yasuyuki Arai , Shoji Kojima
发明人： Yasuyuki Arai , Shoji Kojima
IPC分类号： G01R31/26 , H03B1/00
CPC分类号： G01R31/2841 , G01R31/31922 , G01R31/31924
摘要： A branch circuit branches an input signal to be transmitted into multiple paths. Each timing adjustment circuit applies a delay to at least one from among a positive edge and a negative edge of a signal to be transmitted, which has been branched into a corresponding path. A combining output circuit combines the output signals of the multiple timing adjustment circuits, and outputs the signal thus combined to a transmission line.
摘要翻译：分支电路将要发送的输入信号分支到多个路径。每个定时调整电路对已被分支为相应路径的要发送的信号的上升沿和下降沿中的至少一个施加延迟。组合输出电路组合多个定时调整电路的输出信号，并将这样组合的信号输出到传输线。

58. 发明申请

US20120043968A1 VARIABLE EQUALIZER CIRCUIT 审中-公开
标题翻译：可变均衡器电路
公开(公告)号：US20120043968A1
公开(公告)日：2012-02-23
申请号：US13266330
申请日：2010-03-31
申请人： Shoji Kojima
发明人： Shoji Kojima
IPC分类号： G01R31/02 , H04B3/14
CPC分类号： G01R31/2851 , H04B3/14
摘要： A variable equalizer circuit equalizes a signal received via a transmission line from a device which is a communication partner device. A first resistor is arranged between an output terminal and a fixed voltage terminal, and is configured to have a variable resistance. A first capacitor is arranged between an output terminal and the fixed voltage terminal, and is arranged in parallel with the first resistor, and is configured to have a variable capacitance. A second resistor is arranged between an input terminal and the output terminal. A second capacitor is arranged in parallel with the second resistor between the input terminal and the output terminal. A shunt resistor is arranged on a path including the first capacitor and the second capacitor between the input terminal and the fixed voltage terminal.
摘要翻译：可变均衡器电路使通过传输线从作为通信伙伴设备的设备接收的信号相等。第一电阻器布置在输出端子和固定电压端子之间，并且被配置为具有可变电阻。第一电容器布置在输出端子和固定电压端子之间，并且与第一电阻器并联布置，并且被配置为具有可变电容。第二电阻器设置在输入端子和输出端子之间。第二电容器与输入端子和输出端子之间的第二电阻器并联布置。在包括输入端和固定电压端子之间的第一电容器和第二电容器的路径上设置分流电阻器。

59. 发明授权

US08065102B2 Pulse width measurement circuit 失效
标题翻译：脉宽测量电路
公开(公告)号：US08065102B2
公开(公告)日：2011-11-22
申请号：US12200914
申请日：2008-08-28
申请人： Shoji Kojima
发明人： Shoji Kojima
IPC分类号： G01R25/00
CPC分类号： G01R29/0273 , G01R31/317 , G01R31/31922 , G01R31/31937
摘要： A pulse width measurement circuit generates a time difference signal that corresponds to the pulse width of the input pulse signal PULSE. A delay circuit delays the input pulse signal PULSE by a predetermined amount, and outputs a start signal. An inverter inverts the input pulse signal PULSE, and outputs a stop signal. A time measurement circuit measures the time difference between a positive edge in the start signal and a positive edge in the stop signal, and outputs a time difference signal that corresponds to the time difference.
摘要翻译：脉冲宽度测量电路产生对应于输入脉冲信号PULSE的脉冲宽度的时差信号。延迟电路将输入脉冲信号PULSE延迟预定量，并输出起始信号。反相器反相输入脉冲信号PULSE，并输出停止信号。时间测量电路测量起始信号中的上升沿与停止信号中的上升沿之间的时间差，并输出与时间差对应的时差信号。

60. 发明申请

US20110163771A1 TEST APPARATUS AND DRIVER CIRCUIT 失效
标题翻译：测试装置和驱动电路
公开(公告)号：US20110163771A1
公开(公告)日：2011-07-07
申请号：US12957184
申请日：2010-11-30
申请人： Shoji Kojima , Toshiyuki OKAYASU
发明人： Shoji Kojima , Toshiyuki OKAYASU
IPC分类号： G01R31/00 , G05F5/00
CPC分类号： G01R31/31924
摘要： A test apparatus includes: a driver circuit that supplies, to a device under test, a test signal corresponding to an input signal; and a judging section that judges pass/fail of the device under test, based on the load voltage or the load current supplied to the device under test when supplying a test signal of a constant current or a constant voltage to the device under test from the driver circuit, where the driver circuit includes: a driver section that outputs the test signal; a supply current detecting section that detects a supply current supplied to the driver section; and an output control section that controls a voltage or a current of the test signal outputted from the driver section to the predetermined value, based on the supply current detected by the supply current detecting section.
摘要翻译：测试装置包括：驱动器电路，向被测设备提供对应于输入信号的测试信号; 以及判断部，其根据在向所述被测试装置供给恒定电流或恒定电压的测试信号时，向所述被测设备供给的负载电压或负载电流，判定所述被测试器件的通过/失败。驱动器电路，其中所述驱动器电路包括：驱动器部分，其输出所述测试信号; 电源电流检测部，其检测供给到所述驱动器部的电源电流; 以及输出控制部，其基于由所述供给电流检测部检测出的供给电流，将从所述驱动部输出的所述测试信号的电压或电流控制为所述规定值。

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