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51. 发明授权

US09355095B2 Click noise characterization model 有权
标题翻译：点击噪声表征模型
公开(公告)号：US09355095B2
公开(公告)日：2016-05-31
申请号：US13341653
申请日：2011-12-30
申请人： Weizhu Chen , Zheng Chen , Adish Singla
发明人： Weizhu Chen , Zheng Chen , Adish Singla
IPC分类号： G06F17/30
CPC分类号： G06F17/30 , G06F17/30424 , G06F17/3053 , G06F17/30634 , G06F17/30657 , G06F17/30864
摘要： The techniques discussed herein consider a degree of noise associated with user clicks performed during search sessions. The techniques then generate a model that characterizes click noise so that search engines can more accurately infer document relevance.
摘要翻译：这里讨论的技术考虑了与在搜索会话期间执行的用户点击相关联的噪音程度。然后，该技术产生表征点击噪声的模型，使得搜索引擎可以更准确地推断文档相关性。

52. 发明授权

US09195942B2 Method and system for mining information based on relationships 有权
公开(公告)号：US09195942B2
公开(公告)日：2015-11-24
申请号：US12406039
申请日：2009-03-17
申请人： Benyu Zhang , Wei-Ying Ma , Gu Xu , Hongbin Gao , Zheng Chen , Randy Hinrichs , Hua-Jun Zeng
发明人： Benyu Zhang , Wei-Ying Ma , Gu Xu , Hongbin Gao , Zheng Chen , Randy Hinrichs , Hua-Jun Zeng
IPC分类号： G06F17/30 , G06N5/02
CPC分类号： G06N5/022 , G06F17/30616 , Y10S707/99933 , Y10S707/99934 , Y10S707/99935
摘要： A method and system for identifying information about people is provided. The information system identifies groups of people that have relationships based on their relationships to documents or more generally to objects. The information system initially is provided with an indication of which people have which relationships to which documents. The information system then identifies clusters of people based on having a relationship to the same objects. The information system may also identify clusters of related objects associated with a cluster of people. When a user wants to identify information about a person, the user can provide the name of that person to the information system. The information system then can retrieve and display the names of the other people who are in the same cluster as the person.

53. 发明授权

US09013860B2 Asymmetric hybrid supercapacitors based on nanotube nanowire composites 有权
标题翻译：基于纳米管纳米线复合材料的非对称混合超级电容器
公开(公告)号：US09013860B2
公开(公告)日：2015-04-21
申请号：US13571647
申请日：2012-08-10
申请人： Zheng Chen , Yunfeng Lu
发明人： Zheng Chen , Yunfeng Lu
IPC分类号： H01G9/00 , H01G11/04 , H01G9/04 , H01G11/36 , H01G11/46 , B82Y30/00
CPC分类号： H01G11/34 , B82Y30/00 , H01G9/058 , H01G9/155 , H01G11/04 , H01G11/36 , H01G11/46 , Y02E60/13 , Y02T10/7022
摘要： An asymmetric supercapacitor includes a first structure and a second structure spaced apart from said second structure. One of the structures comprises an anode, and the other of the first and second structures comprises a cathode, wherein the first structure comprises an activated carbon electrode, and the second structure comprises a nanocomposite electrode. The nanocomposite electrode comprises a first network of nanowires that are interpenetrating with a second network of carbon nanotubes.
摘要翻译：不对称超级电容器包括与所述第二结构间隔开的第一结构和第二结构。所述结构中的一个包括阳极，并且所述第一和第二结构中的另一个包括阴极，其中所述第一结构包括活性炭电极，并且所述第二结构包括纳米复合电极。纳米复合电极包括与碳纳米管的第二网络互穿的纳米线的第一网络。

54. 发明授权

US08865732B2 Heterocyclic compounds and uses thereof 有权
标题翻译：杂环化合物及其用途
公开(公告)号：US08865732B2
公开(公告)日：2014-10-21
申请号：US13396339
申请日：2012-02-14
申请人： Zilin Huang , Jeff Jin , Timothy Machajewski , William R. Antonios-McCrea , Maureen McKenna , Daniel Poon , Paul A. Renhowe , Martin Sendzik , Cynthia Shafer , Aaron Smith , Yongjin Xu , Qiong Zhang , Zheng Chen
发明人： Zilin Huang , Jeff Jin , Timothy Machajewski , William R. Antonios-McCrea , Maureen McKenna , Daniel Poon , Paul A. Renhowe , Martin Sendzik , Cynthia Shafer , Aaron Smith , Yongjin Xu , Qiong Zhang , Zheng Chen
IPC分类号： A61K31/505 , C07D241/02
CPC分类号： A61K31/4439 , A61K31/444 , A61K31/4709 , A61K31/497 , A61K31/506 , A61K31/5383 , A61K45/06 , C07D401/14 , C07D403/14 , C07D405/14 , C07D413/14 , C07D417/14 , C07D471/04 , C07D498/04 , A61K2300/00
摘要： New substituted heterocyclic compounds, compositions containing them, and methods of using them for the inhibition of Raf kinase activity are provided. The new compounds and compositions may be used either alone or in combination with at least one additional agent for the treatment of a Raf kinase mediated disorder, such as cancer.
摘要翻译：提供了新的取代的杂环化合物，含有它们的组合物，以及使用它们来抑制Raf激酶活性的方法。新化合物和组合物可以单独使用或与至少一种另外的药物组合使用，用于治疗Raf激酶介导的病症，例如癌症。

55. 发明授权

US08522126B1 Blocking memory readback in a programmable logic device 有权
标题翻译：在可编程逻辑器件中阻塞存储器回读
公开(公告)号：US08522126B1
公开(公告)日：2013-08-27
申请号：US12977011
申请日：2010-12-22
申请人： Zheng Chen , Rohith Sood , Loren McLaury
发明人： Zheng Chen , Rohith Sood , Loren McLaury
IPC分类号： G06F11/10
CPC分类号： G06F11/004
摘要： A programmable logic device (PLD) is provided that includes: a configuration memory including a plurality of memory cells arranged according to rows and columns, wherein a subset of the rows are RAM rows, and wherein a subset of the columns in each RAM row are RAM columns and at least one column in each RAM row is a flag bit column, the memory cells corresponding to the flag bit column and RAM rows operable to store flag bit signals; a soft error detection (SED) circuit operable to read the configuration memory to derive a checksum; a logic circuit to determine if a RAM row is being read by the SED circuit that includes an asserted flag bit; and a blocking circuit that provides a known logical value to the SED circuit responsive to the logic circuit to block readback of the memory cells corresponding to the RAM rows and RAM columns.
摘要翻译：提供了一种可编程逻辑器件（PLD），其包括：配置存储器，包括根据行和列排列的多个存储器单元，其中行的子集是RAM行，并且其中每个RAM行中的列的子集是 RAM列和每个RAM行中的至少一列是标志位列，对应于标志位列的存储器单元和可用于存储标志位信号的RAM行; 软错误检测（SED）电路，用于读取配置存储器以得到校验和; 逻辑电路，用于确定由SED电路读取的RAM行是否包括一个断言的标志位; 以及阻塞电路，其响应于逻辑电路向SED电路提供已知的逻辑值，以阻止对应于RAM行和RAM列的存储单元的读回。

56. 发明授权

US08461894B1 Low-power configurable delay element 有权
标题翻译：低功耗可配置延迟元件
公开(公告)号：US08461894B1
公开(公告)日：2013-06-11
申请号：US13585142
申请日：2012-08-14
申请人： Fulong Zhang , Zheng Chen , Chien Kuang Chen , John Schadt
发明人： Fulong Zhang , Zheng Chen , Chien Kuang Chen , John Schadt
IPC分类号： H03H11/26
CPC分类号： H03K5/131
摘要： In one embodiment, a configurable delay element has three stages. The first stage has an 8-buffer first delay chain and an (8×1) first mux that selects one of the eight first-delay-chain outputs. The second stage has a 24-buffer second delay chain connected to receive the first-mux output and organized into three 8-buffer sub-chains and a (4×1) second mux that selects one of the four second-delay-chain outputs. The third stage has a 96-buffer third delay chain connected to receive the second-mux output and organized into three 32-buffer sub-chains and a (4×1) third mux that selects one of the four third-delay-chain outputs as the delay-element output signal. A delay-element controller provides glitch-less updates to the signal used to control the delay-element muxes by timing those updates to occur when all delay-element buffers have the same state. The controller bases the update timing on the delay-element output signal.
摘要翻译：在一个实施例中，可配置延迟元件具有三个阶段。第一级具有8缓冲器第一延迟链和（8×1）第一多路复用器，其选择八个第一延迟链输出之一。第二级具有连接的24缓冲器第二延迟链，用于接收第一多路复用器输出并被组织成三个8缓冲子链和选择四个第二延迟链输出之一的（4×1）第二复用器。第三级具有96缓冲器第三延迟链，用于接收第二多路复用器输出，并组织成三个32缓冲子链和（4×1）第三复用器，选择四个第三延迟链输出中的一个作为延迟元件输出信号。延迟元件控制器通过定时在所有延迟元件缓冲器具有相同状态时进行定时的这些更新来为用于控制延迟元件多路复用器的信号提供无故障更新。控制器基于延迟元件输出信号的更新时序。

57. 发明授权

US08368424B1 Programmable logic device wakeup using a general purpose input/output port 有权
标题翻译：可编程逻辑器件使用通用输入/输出端口唤醒
公开(公告)号：US08368424B1
公开(公告)日：2013-02-05
申请号：US13038259
申请日：2011-03-01
申请人： Wei Han , Zheng Chen , Warren Juenemann , Eric Lee
发明人： Wei Han , Zheng Chen , Warren Juenemann , Eric Lee
IPC分类号： H03K19/173
CPC分类号： H03K19/17772
摘要： In one embodiment, a programmable logic device such as an FPGA includes a programmable fabric adapted to operate normally and in a sleep mode, and a general purpose input/output port (I/O). The I/O port is adapted to function in conventional fashion during normal operation of the programmable fabric and as a wakeup control port during the sleep mode.
摘要翻译：在一个实施例中，诸如FPGA的可编程逻辑器件包括适于正常和处于休眠模式的可编程结构以及通用输入/输出端口（I / O）。 I / O端口适于在可编程结构的正常操作期间以常规方式起作用，并且在睡眠模式期间用作唤醒控制端口。

58. 发明授权

US08319521B1 Safe programming of key information into non-volatile memory for a programmable logic device 有权
标题翻译：将密钥信息安全地编程到可编程逻辑器件的非易失性存储器中
公开(公告)号：US08319521B1
公开(公告)日：2012-11-27
申请号：US13076300
申请日：2011-03-30
申请人： Wei Han , Barry Britton , Eric Lee , Zheng Chen , Warren Juenemann , Mose Wahlstrom
发明人： Wei Han , Barry Britton , Eric Lee , Zheng Chen , Warren Juenemann , Mose Wahlstrom
IPC分类号： H03K19/177 , H01L25/00
CPC分类号： H03K19/17764 , H03K19/17768
摘要： A programmable logic device (PLD) is disclosed that includes a non-volatile memory; a shadow register; and a data shift register (DSR) configurable to receive control information from an external programming tool, wherein the DSR is configured to shift the control information into the shadow register if the PLD is in a first programming mode, the PLD being configurable to operate in the first programming mode using the control information stored in the shadow register without the control information being stored in the non-volatile memory.
摘要翻译：公开了一种包括非易失性存储器的可编程逻辑器件（PLD）; 影子寄存器以及数据移位寄存器（DSR），其被配置为从外部编程工具接收控制信息，其中所述DSR被配置为如果所述PLD处于第一编程模式，则将所述控制信息移位到所述影子寄存器中，所述PLD可配置为在使用存储在影子寄存器中的控制信息的第一编程模式，而不将控制信息存储在非易失性存储器中。

59. 发明授权

US08248136B1 Low-power, glitch-less, configurable delay element 有权
标题翻译：低功耗，无毛刺，可配置延迟元件
公开(公告)号：US08248136B1
公开(公告)日：2012-08-21
申请号：US13007804
申请日：2011-01-17
申请人： Fulong Zhang , Zheng Chen , Chien Kuang Chen , John Schadt
发明人： Fulong Zhang , Zheng Chen , Chien Kuang Chen , John Schadt
IPC分类号： H03H11/26
CPC分类号： H03K5/131
摘要： In one embodiment, a configurable delay element has three stages. The first stage has an 8-buffer first delay chain and an (8×1) first mux that selects one of the eight first-delay-chain outputs. The second stage has a 24-buffer second delay chain connected to receive the first-mux output and organized into three 8-buffer sub-chains and a (4×1) second mux that selects one of the four second-delay-chain outputs. The third stage has a 96-buffer third delay chain connected to receive the second-mux output and organized into three 32-buffer sub-chains and a (4×1) third mux that selects one of the four third-delay-chain outputs as the delay-element output signal. A delay-element controller provides glitch-less updates to the signal used to control the delay-element muxes by timing those updates to occur when all delay-element buffers have the same state. The controller bases the update timing on the delay-element output signal.
摘要翻译：在一个实施例中，可配置延迟元件具有三个阶段。第一级具有8缓冲器第一延迟链和（8×1）第一多路复用器，其选择八个第一延迟链输出之一。第二级具有连接的24缓冲器第二延迟链，用于接收第一多路复用器输出并被组织成三个8缓冲子链和选择四个第二延迟链输出之一的（4×1）第二复用器。第三级具有96缓冲器第三延迟链，用于接收第二多路复用器输出，并组织成三个32缓冲子链和（4×1）第三复用器，选择四个第三延迟链输出中的一个作为延迟元件输出信号。延迟元件控制器通过定时在所有延迟元件缓冲器具有相同状态时进行定时的这些更新来为用于控制延迟元件多路复用器的信号提供无故障更新。控制器基于延迟元件输出信号的更新时序。

60. 发明申请

US20120143789A1 CLICK MODEL THAT ACCOUNTS FOR A USER'S INTENT WHEN PLACING A QUIERY IN A SEARCH ENGINE 审中-公开
标题翻译：在搜索引擎中放置校园时，用户的信息的点击模式
公开(公告)号：US20120143789A1
公开(公告)日：2012-06-07
申请号：US12957521
申请日：2010-12-01
申请人： Gang Wang , Weizhu Chen , Zheng Chen
发明人： Gang Wang , Weizhu Chen , Zheng Chen
IPC分类号： G06F17/30 , G06F15/18 , G06N5/02
CPC分类号： G06F16/951
摘要： A method of generating training data for a search engine begins by retrieving log data pertaining to user click behavior. The log data is analyzed based on a click model that includes a parameter pertaining to a user intent bias representing the intent of a user in performing a search in order to determine a relevance of each of a plurality of pages to a query. The relevance of the pages is then converted into training data.
摘要翻译：生成搜索引擎的训练数据的方法从检索与用户点击行为有关的日志数据开始。基于点击模型分析日志数据，所述点击模型包括与用户意图偏差相关的参数，所述参数表示用户执行搜索的意图，以便确定多个页面中的每一个与查询的相关性。然后将页面的相关性转换为训练数据。

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