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51. 发明申请

US20080283963A1 Electrical Fuse Circuit for Security Applications 有权
标题翻译：用于安全应用的电保险电路
公开(公告)号：US20080283963A1
公开(公告)日：2008-11-20
申请号：US11748959
申请日：2007-05-15
申请人： Shine Chung , Fu-Lung Hsueh , Fu-Chieh Hsu
发明人： Shine Chung , Fu-Lung Hsueh , Fu-Chieh Hsu
IPC分类号： H01L23/62 , H01L29/00
CPC分类号： G11C17/18
摘要： A fuse circuit is disclosed, which comprises at least one electrical fuse element having a resistance that changes after being stressed in an electromigration mode, a switching device serially coupled with the electrical fuse element in a predetermined path between a fuse programming power supply (VDDQ) and a low voltage power supply (GND) for selectively allowing a programming current passing through the electrical fuse element during a programming operation, and at least one peripheral circuit coupled to the VDDQ, wherein the peripheral circuit is active and draws current from the VDDQ during a fuse programming operation.
摘要翻译：公开了一种熔丝电路，其包括至少一个电熔丝元件，该电熔丝元件具有在电迁移模式下受到应力之后变化的电阻;开关装置，其在熔丝编程电源（VDDQ）之间的预定路径中与电熔丝元件串联连接，以及用于在编程操作期间选择性地允许通过电熔丝元件的编程电流的低电压电源（GND），以及耦合到所述VDDQ的至少一个外围电路，其中所述外围电路是有效的并且在VDDQ期间从VDDQ引出电流保险丝编程操作。

52. 发明授权

US07323379B2 Fabrication process for increased capacitance in an embedded DRAM memory 失效
标题翻译：嵌入式DRAM存储器中增加电容的制造工艺
公开(公告)号：US07323379B2
公开(公告)日：2008-01-29
申请号：US11050988
申请日：2005-02-03
申请人： Dennis Sinitsky , Fu-Chieh Hsu
发明人： Dennis Sinitsky , Fu-Chieh Hsu
IPC分类号： H01L21/8238
CPC分类号： H01L29/66181 , H01L27/10829 , H01L27/1087 , H01L27/10894 , H01L27/11
摘要： An embedded memory system includes an array of dynamic random access memory (DRAM) cells, which are isolated with deep trench isolation, and logic transistors, which are isolated with shallow trench isolation. Each DRAM cell includes an access transistor and a capacitor structure. The capacitor structure is fabricated by forming a metal-dielectric-semiconductor (MOS) capacitor in a deep trench isolation region. A cavity is formed in the deep trench isolation, thereby exposing a sidewall region of the substrate. The sidewall region is doped, thereby forming one electrode of the cell capacitor. A gate dielectric layer is formed over the exposed sidewall, and a polysilicon layer is deposited over the resulting structure, thereby filling the cavity. The polysilicon layer is patterned to form the gate electrode of the access transistor and a capacitor electrode, which extends over the sidewall region and upper surface of the substrate.
摘要翻译：嵌入式存储器系统包括与深沟槽隔离隔离的动态随机存取存储器（DRAM）单元阵列和与浅沟槽隔离隔离的逻辑晶体管。每个DRAM单元包括存取晶体管和电容器结构。通过在深沟槽隔离区域中形成金属 - 电介质半导体（MOS）电容器来制造电容器结构。在深沟槽隔离中形成空腔，从而暴露衬底的侧壁区域。侧壁区域被掺杂，从而形成单元电容器的一个电极。在暴露的侧壁上形成栅介电层，并且在所得结构上沉积多晶硅层，从而填充空腔。图案化多晶硅层以形成存取晶体管的栅电极和在衬底的侧壁区域和上表面上延伸的电容器电极。

53. 发明申请

US20060172504A1 Fabrication process for increased capacitance in an embedded DRAM memory 失效
标题翻译：嵌入式DRAM存储器中增加电容的制造工艺
公开(公告)号：US20060172504A1
公开(公告)日：2006-08-03
申请号：US11050988
申请日：2005-02-03
申请人： Dennis Sinitsky , Fu-Chieh Hsu
发明人： Dennis Sinitsky , Fu-Chieh Hsu
IPC分类号： H01L21/20
CPC分类号： H01L29/66181 , H01L27/10829 , H01L27/1087 , H01L27/10894 , H01L27/11
摘要： An embedded memory system includes an array of dynamic random access memory (DRAM) cells, which are isolated with deep trench isolation, and logic transistors, which are isolated with shallow trench isolation. Each DRAM cell includes an access transistor and a capacitor structure. The capacitor structure is fabricated by forming a metal-dielectric-semiconductor (MOS) capacitor in a deep trench isolation region. A cavity is formed in the deep trench isolation, thereby exposing a sidewall region of the substrate. The sidewall region is doped, thereby forming one electrode of the cell capacitor. A gate dielectric layer is formed over the exposed sidewall, and a polysilicon layer is deposited over the resulting structure, thereby filling the cavity. The polysilicon layer is patterned to form the gate electrode of the access transistor and a capacitor electrode, which extends over the sidewall region and upper surface of the substrate.
摘要翻译：嵌入式存储器系统包括与深沟槽隔离隔离的动态随机存取存储器（DRAM）单元阵列和与浅沟槽隔离隔离的逻辑晶体管。每个DRAM单元包括存取晶体管和电容器结构。通过在深沟槽隔离区域中形成金属 - 电介质半导体（MOS）电容器来制造电容器结构。在深沟槽隔离中形成空腔，从而暴露衬底的侧壁区域。侧壁区域被掺杂，从而形成单元电容器的一个电极。在暴露的侧壁上形成栅介电层，并且在所得结构上沉积多晶硅层，从而填充空腔。图案化多晶硅层以形成存取晶体管的栅电极和在衬底的侧壁区域和上表面上延伸的电容器电极。

54. 发明授权

US07056785B2 Non-volatile memory cell fabricated with slight modification to a conventional logic process and methods of operating same 失效
公开(公告)号：US07056785B2
公开(公告)日：2006-06-06
申请号：US10999259
申请日：2004-11-29
申请人： Fu-Chieh Hsu
发明人： Fu-Chieh Hsu
IPC分类号： H01L21/8242
CPC分类号： H01L27/11521 , G11C7/20 , G11C16/0416 , G11C2216/10 , H01L21/28273 , H01L27/11558 , H01L29/66825
摘要： A non-volatile memory cell is fabricated using a conventional logic process, with minor modifications. The cell is fabricated by forming a shallow trench isolation (STI) region in a well region of a semiconductor substrate. A recessed region is formed in the STI region, wherein the recessed region extends into the STI region and exposes a sidewall region in the well region. A capacitor region is formed in the sidewall region. A dielectric layer is formed over the well region, including the sidewall region. A gate electrode is then formed over the dielectric layer, wherein a portion of the gate electrode extends into the recessed region. An access transistor of the cell is then formed in a self-aligned manner with respect to the gate electrode. A capacitor structure is formed by the gate electrode (in the recessed region), the dielectric layer on the sidewall region, and the capacitor region.

55. 发明授权

US06661042B2 One-transistor floating-body DRAM cell in bulk CMOS process with electrically isolated charge storage region 失效
标题翻译：具有电隔离电荷存储区域的大容量CMOS工艺中的单晶体管浮体DRAM单元
公开(公告)号：US06661042B2
公开(公告)日：2003-12-09
申请号：US10095901
申请日：2002-03-11
申请人： Fu-Chieh Hsu
发明人： Fu-Chieh Hsu
IPC分类号： H01L29768
CPC分类号： H01L27/108 , H01L27/0214 , H01L27/10802 , H01L27/10873 , H01L29/7841
摘要： A one-transistor, floating-body (1T/FB) dynamic random access memory (DRAM) cell is provided that includes a field-effect transistor fabricated using a process compatible with a standard CMOS process. The field-effect transistor includes a source region and a drain region of a first conductivity type and a floating body region of a second conductivity type, opposite the first conductivity type, located between the source region and the drain region. A buried region of the first conductivity type is located under the source region, drain region and floating body region. The buried region helps to form a depletion region, which is located between the buried region and the source region, the drain region and the floating body region. The floating body region is thereby isolated by the depletion region. A bias voltage can be applied to the buried region, thereby controlling leakage currents in the 1T/FB DRAM cell.
摘要翻译：提供了一个单晶体管浮体（1T / FB）动态随机存取存储器（DRAM）单元，其包括使用与标准CMOS工艺兼容的工艺制造的场效应晶体管。场效应晶体管包括位于源极区域和漏极区域之间的第一导电类型的源极区域和漏极区域以及与第一导电类型相反的第二导电类型的浮动体区域。第一导电类型的掩埋区域位于源极区域，漏极区域和浮体区域的下方。掩埋区域有助于形成耗尽区，其位于掩埋区域与源极区域，漏极区域和浮体区域之间。浮体区由此被耗尽区隔离。可以将偏置电压施加到掩埋区域，从而控制1T / FB DRAM单元中的漏电流。

56. 发明授权

US06425046B1 Method for using a latched sense amplifier in a memory module as a high-speed cache memory 失效
标题翻译：将存储器模块中的锁存读出放大器用作高速缓存存储器的方法
公开(公告)号：US06425046B1
公开(公告)日：2002-07-23
申请号：US08820297
申请日：1997-03-18
申请人： Wing Yu Leung , Fu-Chieh Hsu
发明人： Wing Yu Leung , Fu-Chieh Hsu
IPC分类号： G11C700
CPC分类号： H04L25/0272 , G06F11/006 , G06F11/10 , G06F11/1032 , G06F11/2007 , G06F12/0661 , G06F13/4077 , G11C5/04 , G11C29/006 , G11C29/08 , G11C29/48 , G11C29/76 , G11C29/808 , G11C29/81 , G11C29/832 , G11C29/88 , G11C2029/0401 , G11C2029/0411 , G11C2029/4402 , H01L22/22 , H01L27/0203 , H04L5/1461 , H04L25/026 , H04L25/028 , H04L25/029 , H04L25/0292 , Y10S257/907
摘要： A fault-tolerant, high-speed wafer scale system includes a plurality of functional memory modules, each having associated sense amplifiers which act as high-speed cache memory, a parallel hierarchical bus which is fault-tolerant to defects and a interconnect network, and one or more bus masters. By grouping the DRAM arrays into logically independent modules of relatively small memory capacity (588 Kbit), a large number of cache lines (128) is obtained at small main memory capacity (4 Megabytes). The large number of cache lines allows maintaining a high cache hit rate (greater than 90%).
摘要翻译：容错的高速晶片刻度系统包括多个功能存储器模块，每个功能存储器模块具有作为高速高速缓冲存储器的相关联的读出放大器，对缺陷容错的并行分层总线和互连网络，以及一个或多个巴士主人。通过将DRAM阵列分组成具有相对小的存储容量（588Kbit）的逻辑上独立的模块，在小的主存储器容量（4兆字节）下获得大量的高速缓存行（128）。大量的缓存行允许保持高缓存命中率（大于90％）。

57. 发明授权

US5790138A Method and structure for improving display data bandwidth in a unified memory architecture system 失效
标题翻译：在统一存储器架构系统中提高显示数据带宽的方法和结构
公开(公告)号：US5790138A
公开(公告)日：1998-08-04
申请号：US587379
申请日：1996-01-16
申请人： Fu-Chieh Hsu
发明人： Fu-Chieh Hsu
IPC分类号： G06F15/17 , G09G5/36 , G09G5/39 , G09G5/393 , G09G5/399 , G06F15/167
CPC分类号： G09G5/363 , G06F15/17 , G09G5/399 , G09G2360/123 , G09G2360/125 , G09G2360/126 , G09G2360/128 , G09G5/393
摘要： A computer unified memory architecture (UMA) system and method which includes a unified memory which is partitioned into a main memory and a main frame buffer memory, as well as a separate expansion frame buffer memory. Together, the main frame buffer memory and the expansion frame buffer memory form an entire frame buffer memory. The UMA system performs a display refresh operation by alternately accessing the main frame buffer memory and the expansion frame buffer memory. Because the display data bandwidth is split between the main frame buffer memory and the expansion frame buffer memory, the data bandwidth of the unified memory is effectively increased, thereby enabling higher system performance. The expansion frame buffer memory has a relatively small capacity, thereby retaining much of the cost benefit of a UMA system.
摘要翻译：一种计算机统一存储器架构（UMA）系统和方法，包括分为主存储器和主帧缓冲存储器的统一存储器以及单独的扩展帧缓冲存储器。一起，主帧缓冲存储器和扩展帧缓冲存储器形成整个帧缓冲存储器。 UMA系统通过交替访问主帧缓冲存储器和扩展帧缓冲存储器来执行显示刷新操作。由于显示数据带宽分散在主帧缓冲存储器和扩展帧缓冲存储器之间，所以统一存储器的数据带宽有效提高，从而实现更高的系统性能。扩展帧缓冲存储器具有相对较小的容量，从而保留了UMA系统的大部分成本优势。

58. 发明申请

US20100199238A1 Systematic Method for Variable Layout Shrink 有权
标题翻译：可变布局收缩的系统方法
公开(公告)号：US20100199238A1
公开(公告)日：2010-08-05
申请号：US12617046
申请日：2009-11-12
申请人： Fu-Chieh Hsu , Louis Chao-Chiuan Liu , Lee-Chung Lu , Yi-Kan Cheng
发明人： Fu-Chieh Hsu , Louis Chao-Chiuan Liu , Lee-Chung Lu , Yi-Kan Cheng
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A method for integrated circuit design includes providing a layout of an integrated circuit; determining key parameters of the integrated circuit; determining target values of the key parameters; and performing a first shrinkage of the layout using a first shrink percentage to generate a shrunk layout. The shrunk layout is evaluated by generating values of the key parameters from the shrunk layout. A portion of the values of the key parameters failing to meet respective ones of the target values is found. Guidelines for tuning manufacturing processes of the shrunk layout are provided, so that the portion of the values of the key parameters can meet the respective ones of the target values.
摘要翻译：一种用于集成电路设计的方法包括提供集成电路的布局; 确定集成电路的关键参数; 确定关键参数的目标值; 并且使用第一收缩百分比来执行布局的第一收缩以产生收缩的布局。通过从缩小布局生成关键参数的值来评估收缩布局。找到关键参数的值的一部分不能满足相应的目标值。提供用于调整缩小布局的制造过程的指南，使得关键参数的值的部分可以满足相应的目标值。

59. 发明授权

US07505345B2 Circuit and method for an SRAM with two phase word line pulse 有权
标题翻译：具有两相字线脉冲的SRAM的电路和方法
公开(公告)号：US07505345B2
公开(公告)日：2009-03-17
申请号：US11811659
申请日：2007-06-11
申请人： Chia Wei Wang , Cheng Hung Lee , Hung-Jen Liao , Fu-Chieh Hsu
发明人： Chia Wei Wang , Cheng Hung Lee , Hung-Jen Liao , Fu-Chieh Hsu
IPC分类号： G11C7/02
CPC分类号： G11C11/418 , G11C8/08
摘要： A circuit and method for providing a two phase word line pulse for use during access cycles in an SRAM memory with improved operating margins. A first and a second timing circuit are provided and a word line voltage suppression circuit is provided to reduce the voltage on the active word lines in a first phase of a word line pulse, and to allow the word lines to rise to a second, unsuppressed voltage in a second phase of the word line pulse, responsive to the first and second timing circuits. The first and second timing circuits observe the bit lines voltage discharge and provide control signals active when the bit lines are discharged past certain thresholds, these signals control the voltage suppression circuit. Operating margins for the SRAM are therefore improved. Methods for operating an SRAM using a two phase word line pulse are provided.
摘要翻译：一种电路和方法，用于在具有改进的操作余量的SRAM存储器中的访问周期期间提供两相字线脉冲。提供第一和第二定时电路，并且提供字线电压抑制电路以减小字线脉冲的第一相中有效字线上的电压，并允许字线上升到第二，未压缩响应于第一和第二定时电路在字线脉冲的第二相位中的电压。第一和第二定时电路观察位线电压放电，并且当位线经过某些阈值时提供控制信号有效，这些信号控制电压抑制电路。因此，SRAM的工作裕度得到改善。提供了使用两相字线脉冲来操作SRAM的方法。

60. 发明授权

US06913964B2 Method of fabricating a one transistor floating-body DRAM cell in bulk CMOS process with electrically isolated charge storage region 失效
标题翻译：在具有电隔离电荷存储区域的本体CMOS工艺中制造一个晶体管浮体DRAM单元的方法
公开(公告)号：US06913964B2
公开(公告)日：2005-07-05
申请号：US10676695
申请日：2003-09-30
申请人： Fu-Chieh Hsu
发明人： Fu-Chieh Hsu
IPC分类号： H01L21/8242 , H01L27/02 , H01L27/108 , H01L27/148 , H01L29/768
CPC分类号： H01L27/108 , H01L27/0214 , H01L27/10802 , H01L27/10873 , H01L29/7841
摘要： A one-transistor, floating-body (1T/FB) dynamic random access memory (DRAM) cell is provided that includes a field-effect transistor fabricated using a process compatible with a standard CMOS process. The field-effect transistor includes a source region and a drain region of a first conductivity type and a floating body region of a second conductivity type, opposite the first conductivity type, located between the source region and the drain region. A buried region of the first conductivity type is located under the source region, drain region and floating body region. The buried region helps to form a depletion region, which is located between the buried region and the source region, the drain region and the floating body region. The floating body region is thereby isolated by the depletion region. A bias voltage can be applied to the buried region, thereby controlling leakage currents in the 1T/FB DRAM cell.
摘要翻译：提供了一个单晶体管浮体（1T / FB）动态随机存取存储器（DRAM）单元，其包括使用与标准CMOS工艺兼容的工艺制造的场效应晶体管。场效应晶体管包括位于源极区域和漏极区域之间的第一导电类型的源极区域和漏极区域以及与第一导电类型相反的第二导电类型的浮动体区域。第一导电类型的掩埋区域位于源极区域，漏极区域和浮体区域的下方。掩埋区域有助于形成耗尽区，其位于掩埋区域与源极区域，漏极区域和浮体区域之间。浮体区由此被耗尽区隔离。可以将偏置电压施加到掩埋区域，从而控制1T / FB DRAM单元中的漏电流。

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