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51. 发明授权

US07420532B2 Flat display apparatus and portable terminal apparatus 有权
标题翻译：平板显示装置和便携式终端装置
公开(公告)号：US07420532B2
公开(公告)日：2008-09-02
申请号：US10541095
申请日：2003-12-26
申请人： Yoshiharu Nakajima , Noboru Toyozawa
发明人： Yoshiharu Nakajima , Noboru Toyozawa
IPC分类号： G09G5/10
CPC分类号： G09G3/3688 , G09G3/3607 , G09G2310/027 , G09G2310/0281 , G09G2330/021
摘要： The present invention applies illustratively to a liquid crystal display apparatus as well as to a PDA and a mobile phone each using that liquid crystal display apparatus. Typically, a gradation setting circuit 20B for the green color is disposed along one of two opposing sides of a display unit 14, and a gradation setting circuit 20A for the red and blue colors is positioned along the other side of the unit 14.
摘要翻译：本发明示例性地应用于液晶显示装置以及分别使用该液晶显示装置的PDA和移动电话。通常，用于绿色的灰度设置电路20B沿着显示单元14的两个相对侧中的一个设置，并且用于红色和蓝色的灰度设置电路20A沿着单元14的另一侧定位。

52. 发明授权

US07372446B2 Display device, method for driving the same, and portable terminal apparatus using the same 有权
标题翻译：显示装置及其驱动方法以及使用其的便携式终端装置
公开(公告)号：US07372446B2
公开(公告)日：2008-05-13
申请号：US11207211
申请日：2005-08-19
申请人： Masaki Murase , Yoshiharu Nakajima
发明人： Masaki Murase , Yoshiharu Nakajima
IPC分类号： G09G3/36
CPC分类号： G09G3/3648 , G09G2310/0232 , G09G2310/0289 , G09G2310/0297 , G09G2330/021
摘要： A selection-addressing-type liquid crystal display selectively addresses a signal line of a pixel unit using groups of three selectors of a selector circuit in a time-division manner. A level converter level shifts selector pulses having a voltage swing corresponding to the external-circuit power supply to selector pulses having a voltage swing corresponding to the internal-circuit power supply. In a non-display region in partial display mode, the level converter is deactivated under the control of a control signal to reduce direct current consumption therein.
摘要翻译：选择寻址型液晶显示器以时分方式使用选择器电路的三个选择器的组来选择性地寻址像素单元的信号线。电平转换器电平将具有与外部电路电源相对应的电压摆幅的选择器脉冲移位到具有与内部电路电源相对应的电压摆幅的选择器脉冲。在部分显示模式的非显示区域中，电平转换器在控制信号的控制下被去激活，以减少其中的直流消耗。

53. 发明授权

US07368945B2 Logic circuit, timing generation circuit, display device, and portable terminal 有权
标题翻译：逻辑电路，定时生成电路，显示装置和便携式终端
公开(公告)号：US07368945B2
公开(公告)日：2008-05-06
申请号：US11441879
申请日：2006-05-26
申请人： Yoshitoshi Kida , Yoshiharu Nakajima , Toshikazu Maekawa
发明人： Yoshitoshi Kida , Yoshiharu Nakajima , Toshikazu Maekawa
IPC分类号： H03K19/173 , H03K3/037
CPC分类号： G09G3/20 , G09G3/3648 , G09G5/18 , G09G2300/0408 , G09G2310/0289 , G09G2310/08
摘要： When a buffer is formed by using transistors having large element characteristic variations, the deviation of the timing between the input clock pulse and the reset pulse is likely to occur. When the deviation of the timing becomes larger, a malfunction is caused to occur, and an operation margin becomes smaller with respect to the variations of the element characteristics. In a timing generation circuit, which is formed on an insulating substrate and which has two TFFs (12, 13), for generating a dot clock DCK and a horizontal clock HCK whose frequencies are different in synchronization with a master clock MCK which is input external to the substrate, separate reset pulses drst and hrst are generated at a pulse generation circuit 15 with respect to the two TFFs (12, 13), and a resetting operation is performed at separate timings. Thus, a large operation margin can be ensured even when each circuit is formed by using TFTs having large element characteristic variations and a rough process rule.
摘要翻译：当通过使用具有大的元件特性变化的晶体管形成缓冲器时，可能会发生输入时钟脉冲与复位脉冲之间的定时偏差。当定时的偏差变大时，会发生故障，相对于元件特性的变化，操作余量变小。在形成在绝缘基板上并具有两个TFF（12,13）的定时产生电路中，用于产生点时钟DCK和频率与输入外部的主时钟MCK同步的频率不同的水平时钟HCK 在相对于两个TFF（12,13）的脉冲发生电路15处产生分离的复位脉冲drst和hrst，并且在单独的定时执行复位操作。因此，即使当通过使用具有大的元件特性变化的TFT和粗略的处理规则形成每个电路时，也可以确保大的操作余量。

54. 发明授权

US07224200B2 Level shift circuit, display apparatus, and portable terminal 有权
公开(公告)号：US07224200B2
公开(公告)日：2007-05-29
申请号：US10484953
申请日：2003-05-26
申请人： Yoshitoshi Kida , Yoshiharu Nakajima , Hiroaki Ichikawa
发明人： Yoshitoshi Kida , Yoshiharu Nakajima , Hiroaki Ichikawa
IPC分类号： H03L5/00
CPC分类号： G09G3/3688 , G09G3/3655 , G09G2300/0408 , G09G2310/027 , G09G2310/0289 , G09G2310/0294 , H03K3/356165
摘要： In the structure in which an input signal IN and a reverse-phase signal XIN thereof are externally input, an external IC is required for generating the reverse-phase signal XIN, and the number of required input signal terminals is two.A level shift circuit formed on an insulating substrate, such as a glass substrate, using transistors with large characteristic variations, for example, TFTs with high thresholds Vth, includes a complementary generator unit (11) driven by a first power supply (VCC) having an amplitude voltage equal to the amplitude voltage of a signal externally input from the substrate to generate complementary signals from a single-phase input signal IN. The complementary signals generated by the complementary generator unit (11) are level-shifted by a level shift unit (14). Therefore, it is no longer necessary to externally input the reverse-phase signal XIN.

55. 发明申请

US20070109282A1 Data transfer circuit and flat display device 有权
标题翻译：数据传输电路和平板显示设备
公开(公告)号：US20070109282A1
公开(公告)日：2007-05-17
申请号：US10561870
申请日：2004-07-06
申请人： Yoshitoshi Kida , Yoshiharu Nakajima
发明人： Yoshitoshi Kida , Yoshiharu Nakajima
IPC分类号： G09G5/00
CPC分类号： H03K3/356156 , G09G3/3688 , G09G2300/0408 , G09G2310/027 , G09G2310/0289 , G09G2310/0294 , G09G2330/02 , G09G2330/021 , G11C19/00 , H03K3/0375
摘要： The present invention is a data transfer circuit applicable to a liquid crystal display apparatus with a drive circuit formed integral, for example, on an insulation substrate, configured such that only an inverted output of a latch result of a first latch section (41) or only a non-inverted output thereof is data-transferred to a second latch section (42), and that at least during a period of data transfer to the second latch section (42), a power supply voltage of the first latch section (41) is raised.
摘要翻译：本发明是可应用于液晶显示装置的数据传输电路，该液晶显示装置具有例如在绝缘基板上形成为一体的驱动电路，该驱动电路被配置为仅使第一锁存部分（41）的锁存结果的反相输出或仅将其非反相输出数据传送到第二锁存部分（42），并且至少在数据传送到第二锁存部分（42）期间，第一锁存部分（41）的电源电压）被提升。

56. 发明授权

US07205989B2 Power supply voltage converting circuit control method thereof display apparatus and portable terminal 有权
标题翻译：电源电压转换电路的控制方法显示装置和便携式终端
公开(公告)号：US07205989B2
公开(公告)日：2007-04-17
申请号：US10182873
申请日：2001-12-06
申请人： Yoshiharu Nakajima
发明人： Yoshiharu Nakajima
IPC分类号： G09G5/00
CPC分类号： G09G3/3696 , G09G2300/0408 , G09G2310/04 , G09G2320/0233 , G09G2330/02 , G09G2330/022 , G09G2340/0428 , H02M3/07 , H02M2001/0012 , H02M2001/0032 , H02M2003/071 , Y02B70/16
摘要： In a power supply voltage converting circuit using a charge pump circuit having a switch device (Nch MOS transistor Qn(12) and Pch MOS transistor Qp(12)) in an output unit, a first clamp circuit (13) diode-clamps a switching pulse voltage (control pulse voltage) for the switch device at the time of starting the power supply voltage converting circuit, and a second clamp circuit (16) clamps the switching pulse voltage at a ground level (negative side circuit power supply potential) on the basis of a clamp pulse obtained by using an output voltage Vout at the time of an end of the starting process. A sufficient driving voltage is thereby provided for the Pch MOS transistor Qp(12) in particular. Thus, a power supply voltage converting circuit that can obtain a high current capacity on a small-area circuit scale, a control method thereof, a display apparatus having the power supply voltage converting circuit as a power supply circuit, and a portable terminal having the display apparatus are provided.
摘要翻译：在输出单元中使用具有开关器件（Nch MOS晶体管Qn（12）和Pch MOS晶体管Qp（12））的电荷泵电路的电源电压转换电路中，第一钳位电路（13）二极管钳位开关在启动电源电压转换电路时用于开关装置的脉冲电压（控制脉冲电压），以及第二钳位电路（16）将开关脉冲电压（负侧电路电源电位）钳位在在启动过程结束时通过使用输出电压Vout获得的钳位脉冲的基础。从而为Pch MOS晶体管Qp（12）提供足够的驱动电压。因此，可以在小面积电路规模上获得高电流容量的电源电压转换电路，其控制方法，具有电源电压转换电路作为电源电路的显示装置，以及具有提供显示装置。

57. 发明申请

US20070040827A1 Power supply generating circuit, display apparatus, and portable terminal device 有权
标题翻译：电源发生电路，显示装置和便携式终端装置
公开(公告)号：US20070040827A1
公开(公告)日：2007-02-22
申请号：US11590169
申请日：2006-10-30
申请人： Noboru Toyozawa , Yoshiharu Nakajima
发明人： Noboru Toyozawa , Yoshiharu Nakajima
IPC分类号： G09G5/00
CPC分类号： H02M3/073 , G09G3/36 , G09G2330/022 , H02M3/07
摘要： A power supply generating circuit, a display apparatus incorporating the same, and a portable terminal device using the display apparatus as an output display unit are provided. In a DC-DC converter having a charge pump circuit (31), a voltage dividing circuit (32), and a regulation circuit (33), p-channel MOS transistors (Qp21, Qp22, Qp31) are turned on/off based on an enable pulse enb to make the voltage dividing circuit (32) and a comparator (41) active only for a period of regulation time and inactive otherwise. This can cause a current to flow in voltage-divider resistors (R1, R2) and the comparator (41) only for a certain period of time required for the regulation operation, thus reducing the power consumption loss caused by a constant current flow in the voltage-divider resistors (R1, R2) and the comparator (41).
摘要翻译：提供电源发生电路，其结合的显示装置以及使用该显示装置作为输出显示单元的便携式终端装置。在具有电荷泵电路（31），分压电路（32）和调节电路（33）的DC-DC转换器中，p沟道MOS晶体管（Qp 21，Qp 22，Qp 31）导通/ 基于使能脉冲enb使得分压电路（32）和比较器（41）仅在调节时间的周期内有效，否则不起作用。这可能导致电流在分压电阻（R 1，R 2）和比较器（41）中流过调节操作所需的一段时间，从而减少由恒定电流流动引起的功耗损耗在分压电阻（R 1，R 2）和比较器（41）中。

58. 发明申请

US20060214694A1 Logic circuit, timing generation circuit, display device, and portable terminal 有权
公开(公告)号：US20060214694A1
公开(公告)日：2006-09-28
申请号：US11441879
申请日：2006-05-26
申请人： Yoshitoshi Kida , Yoshiharu Nakajima , Toshikazu Maekawa
发明人： Yoshitoshi Kida , Yoshiharu Nakajima , Toshikazu Maekawa
IPC分类号： H03K19/00
CPC分类号： G09G3/20 , G09G3/3648 , G09G5/18 , G09G2300/0408 , G09G2310/0289 , G09G2310/08
摘要： When a buffer is formed by using transistors having large element characteristic variations, the deviation of the timing between the input clock pulse and the reset pulse is likely to occur. When the deviation of the timing becomes larger, a malfunction is caused to occur, and an operation margin becomes smaller with respect to the variations of the element characteristics. In a timing generation circuit, which is formed on an insulating substrate and which has two TFFs (12, 13), for generating a dot clock DCK and a horizontal clock HCK whose frequencies are different in synchronization with a master clock MCK which is input external to the substrate, separate reset pulses drst and hrst are generated at a pulse generation circuit 15 with respect to the two TFFs (12, 13), and a resetting operation is performed at separate timings. Thus, a large operation margin can be ensured even when each circuit is formed by using TFTs having large element characteristic variations and a rough process rule.

59. 发明申请

US20060164364A1 Delay time correction circuit, video data processing circuit, and flat display device 审中-公开
标题翻译：延迟时间校正电路，视频数据处理电路和平板显示设备
公开(公告)号：US20060164364A1
公开(公告)日：2006-07-27
申请号：US10564473
申请日：2004-07-27
申请人： Masaki Murase , Yoshiharu Nakajima , Yoshitoshi Kida
发明人： Masaki Murase , Yoshiharu Nakajima , Yoshitoshi Kida
IPC分类号： G09G3/36
CPC分类号： G09G3/3685 , G09G2300/0408
摘要： The present invention is applied to, for example, a liquid crystal display device having a driving circuit integrally formed on an insulating substrate, and makes it possible to effectively avoid a variation in delay time in a logical circuit using TFTs or the like by inserting dummy data (DD) into input data (D1) and forcedly switching the logical level of the input data (D1) at a predetermined timing during a quiescent period (T2) in which the input data is held at a constant logical level.
摘要翻译：本发明应用于例如具有整体形成在绝缘基板上的驱动电路的液晶显示装置，并且可以通过插入虚拟装置来有效地避免使用TFT等的逻辑电路中的延迟时间的变化数据（DD）输入到输入数据（D 1）中，并且在其中输入数据保持在恒定逻辑电平的静止时段（T 2）期间，以预定定时强制切换输入数据（D 1）的逻辑电平。

60. 发明申请

US20060152460A1 Display device 失效
标题翻译：显示设备
公开(公告)号：US20060152460A1
公开(公告)日：2006-07-13
申请号：US10542503
申请日：2003-12-25
申请人： Noboru Toyozawa , Yoshiharu Nakajima , Hirotoshi Koyama
发明人： Noboru Toyozawa , Yoshiharu Nakajima , Hirotoshi Koyama
IPC分类号： G09G3/36
CPC分类号： G09G3/3677 , G09G3/2011 , G09G3/3614 , G09G3/3648 , G09G3/3655 , G09G3/3696 , G09G2300/0876 , G09G2310/027 , G09G2310/08 , G09G2330/02 , G09G2330/021
摘要： A display apparatus that can improve power savings in a waiting mode is disclosed. The display apparatus (0) is used as a display component of an electronic device capable of switching between a normal power consumption state and a low power consumption state and includes a panel in which a display area (2) and a peripheral circuit section for driving the display area are integrally formed on an insulating substrate (1). The circuit section can switch between an operation mode and a waiting mode in response to the switching between the normal power consumption state and the low power consumption state of a main body of the electronic device. The circuit section includes standby control means that, in the operation mode, the circuit section operates by receiving a power supply voltage from the main body of the electronic device and drives the display area (2) to show an image. In the waiting mode, while receiving the power supply voltage from the main body of the electronic device, the standby control means stops driving the display area 2 and inactivates the circuit section to suppress power consumption. The standby control means executes a control sequence to shut off direct current components flowing through resistive elements at least included in the circuit section during the inactivation.
摘要翻译：公开了一种可以提高等待模式下的节能的显示装置。显示装置（0）用作能够在正常功耗状态和低功耗状态之间切换的电子设备的显示部件，并且包括其中显示区域（2）和用于驱动的外围电路部分显示区域一体地形成在绝缘基板（1）上。响应于电子设备的主体的正常功耗状态和低功耗状态之间的切换，电路部分可以在操作模式和等待模式之间切换。电路部分包括备用控制装置，在操作模式中，电路部分通过从电子设备的主体接收电源电压并驱动显示区域（2）来显示图像来操作。在等待模式中，待机控制装置在从电子装置主体接收电源电压的同时，停止驱动显示区域2，使电路部分失效以抑制电力消耗。备用控制装置执行控制顺序，以在停用期间截止至少包括在电路部分中的电阻元件流过的直流分量。

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