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51. 发明授权

US07952423B2 Process/design methodology to enable high performance logic and analog circuits using a single process 有权
标题翻译：使用单一过程实现高性能逻辑和模拟电路的过程/设计方法
公开(公告)号：US07952423B2
公开(公告)日：2011-05-31
申请号：US12241706
申请日：2008-09-30
申请人： Qi Xiang , Albert Ratnakumar , Jeffrey Xiaoqi Tung , Weiqi Ding
发明人： Qi Xiang , Albert Ratnakumar , Jeffrey Xiaoqi Tung , Weiqi Ding
IPC分类号： G05F1/10
CPC分类号： G05F3/205 , H01L29/1083 , H01L29/6659 , H01L29/7833
摘要： A method for improving analog circuits performance using a circuit design using forward bias and a modified mixed-signal process is presented. A circuit consisting plurality of NMOS and PMOS transistors is defined. The body terminal of the NMOS transistors are coupled to a first voltage source and the body terminal of the PMOS transistors are coupled a second voltage source. Transistors in the circuit are selectively biased by applying the first voltage source to the body terminal of each selected NMOS transistor and applying the second voltage source to the body terminal of each selected PMOS transistor. In one embodiment, the first voltage source and the second voltage source are modifiable to provide forward and reverse bias to the body terminal of the transistors.
摘要翻译：提出了使用正向偏置电路设计和改进的混合信号处理来提高模拟电路性能的方法。定义了包括多个NMOS和PMOS晶体管的电路。 NMOS晶体管的主体端子耦合到第一电压源，并且PMOS晶体管的主体端子耦合第二电压源。通过将第一电压源施加到每个选定的NMOS晶体管的主体端子并将第二电压源施加到每个选择的PMOS晶体管的主体端子来选择性地偏置电路中的晶体管。在一个实施例中，第一电压源和第二电压源是可修改的，以向晶体管的主体端子提供正向和反向偏置。

52. 发明授权

US08933751B1 High resolution capacitor 有权
标题翻译：高分辨率电容
公开(公告)号：US08933751B1
公开(公告)日：2015-01-13
申请号：US13475678
申请日：2012-05-18
申请人： Wilson Wong , Weiqi Ding , Shuxian Chen , Simardeep Maangat , Albert Ratnakumar
发明人： Wilson Wong , Weiqi Ding , Shuxian Chen , Simardeep Maangat , Albert Ratnakumar
IPC分类号： H03F3/45 , H01G4/40 , H03F1/56
CPC分类号： H01G4/40 , H01G17/00 , H03F1/56
摘要： A first trimming capacitor having a first terminal and a second terminal is coupled in parallel between a first terminal and a second terminal of a first capacitor. The first trimming capacitor comprises a first plurality of switched capacitors having different capacitances coupled in parallel. Each of the switched capacitors comprises a switch capacitor and a switch coupled in series. In an illustrative application the first capacitor and the first trimming capacitor are coupled between an output terminal of an operational amplifier (op-amp) and an inverting input terminal of the op-amp. A second capacitor and a second trimming capacitor similar to the first capacitor and the first trimming capacitor are coupled between an input and the inverting input terminal of the op-amp.
摘要翻译：具有第一端子和第二端子的第一微调电容器并联耦合在第一电容器的第一端子和第二端子之间。第一微调电容器包括具有并联耦合的不同电容的第一多个开关电容器。每个开关电容器包括开关电容器和串联耦合的开关。在说明性应用中，第一电容器和第一微调电容器耦合在运算放大器（运算放大器）的输出端和运算放大器的反相输入端之间。类似于第一电容器和第一微调电容器的第二电容器和第二微调电容器耦合在运算放大器的输入端和反相输入端子之间。

53. 发明授权

US08611403B1 Apparatus and methods for transceiver power adaptation 有权
标题翻译：收发机功率调整的装置和方法
公开(公告)号：US08611403B1
公开(公告)日：2013-12-17
申请号：US13446543
申请日：2012-04-13
申请人： Weiqi Ding
发明人： Weiqi Ding
IPC分类号： H04B1/38
CPC分类号： G06F1/3206
摘要： Disclosed are apparatus and methods to advantageously manage transceiver power in an automated manner using adaptation logic that may be implemented on a same integrated circuit as the transceiver circuitry. In one embodiment, a power-consuming component of the transceiver is turned on at a lowest power setting. A determination is made as to whether a first set of eye opening data for a serial data signal meets preset criteria. If the preset criteria are not met by the first set of eye opening data, then the power-consuming component is changed to a second lowest power setting. Another embodiment relates to an integrated circuit including a receiver buffer, a receiver equalization circuit, an eye viewer circuit and adaptation logic. The adaptation logic is configured to obtain the eye opening data and to adapt the receiver equalization circuit to conserve power used. Other embodiments, aspects and features are also disclosed.
摘要翻译：公开了利用可以在与收发器电路相同的集成电路上实施的自适应逻辑来以自动方式来管理收发器功率的装置和方法。在一个实施例中，收发器的功耗部件在最低功率设置下被接通。确定串行数据信号的第一组眼图数据是否满足预设标准。如果第一组睁眼数据不满足预设标准，则将功耗组件改变为第二低功率设置。另一个实施例涉及一种集成电路，其包括接收缓冲器，接收器均衡电路，眼睛观察器电路和适配逻辑。适配逻辑被配置为获得睁眼数据并使接收机均衡电路适应以节省所使用的功率。还公开了其它实施例，方面和特征。

54. 发明授权

US08462906B1 Apparatus and methods for detection and correction of transmitter duty cycle distortion 有权
标题翻译：用于检测和校正发射机占空比失真的装置和方法
公开(公告)号：US08462906B1
公开(公告)日：2013-06-11
申请号：US13234062
申请日：2011-09-15
申请人： Weiqi Ding
发明人： Weiqi Ding
IPC分类号： H04L7/00
CPC分类号： H04L7/00 , H03K5/1565
摘要： One embodiment relates to an integrated circuit which includes a transmitter buffer circuit, a duty cycle distortion (DCD) detector, correction logic, and a duty cycle adjuster. The DCD detector is configured to selectively couple to the serial output of the transmitter buffer circuit. The correction logic is configured to generate control signals based on the output of the DCD detector. The duty cycle adjuster is configured to adjust a duty cycle of the serial input signal based on the control signals. Another embodiment relates to a method of correcting duty cycle distortion in a transmitter. Other embodiments and features are also disclosed.
摘要翻译：一个实施例涉及一种集成电路，其包括发射机缓冲电路，占空比失真（DCD）检测器，校正逻辑和占空比调节器。 DCD检测器被配置为选择性地耦合到发射机缓冲电路的串行输出。校正逻辑被配置为基于DCD检测器的输出产生控制信号。占空比调整器被配置为基于控制信号调整串行输入信号的占空比。另一实施例涉及一种校正发射机中占空比失真的方法。还公开了其它实施例和特征。

55. 发明授权

US08125254B1 Techniques for configuring multi-path feedback loops 有权
标题翻译：用于配置多径反馈回路的技术
公开(公告)号：US08125254B1
公开(公告)日：2012-02-28
申请号：US12613465
申请日：2009-11-05
申请人： Weiqi Ding
发明人： Weiqi Ding
IPC分类号： H03L7/06
CPC分类号： H03L7/089 , H03L2207/06
摘要： In some embodiments, a feedback loop circuit includes a phase detector, first and second charge pumps that are each coupled to receive an output signal of the phase detector, a first low pass filter, a second low pass filter coupled to an output of the second charge pump, a clock signal generation circuit having first and second control inputs, a first switch circuit coupled between the first low pass filter and the second low pass filter, and a second switch circuit coupled to the first low pass filter and the first control input of the clock signal generation circuit.
摘要翻译：在一些实施例中，反馈回路包括相位检测器，第一和第二电荷泵，每个电荷泵被耦合以接收相位检测器的输出信号，第一低通滤波器，耦合到第二低通滤波器的输出的第二低通滤波器电荷泵，具有第一和第二控制输入的时钟信号发生电路，耦合在第一低通滤波器和第二低通滤波器之间的第一开关电路，以及耦合到第一低通滤波器和第一控制输入端的第二开关电路的时钟信号发生电路。

56. 发明授权

US08754794B1 Methods and apparatus for calibrating pipeline analog-to-digital converters 有权
标题翻译：用于校准管道模数转换器的方法和装置
公开(公告)号：US08754794B1
公开(公告)日：2014-06-17
申请号：US13558136
申请日：2012-07-25
申请人： Wei Li , Weiqi Ding , Wilson Wong
发明人： Wei Li , Weiqi Ding , Wilson Wong
IPC分类号： H03M1/10
CPC分类号： H03M1/1057 , H03M1/1028 , H03M1/164
摘要： An integrated circuit with a pipeline analog-to-digital (A/D) converter and associated calibration circuitry is provided. The A/D converter may include multiple series-connected pipeline stages at least some of which are implemented using a switched capacitor configuration. The calibration circuitry may include an analog error correction circuit, a digital error correction circuit, and a calibration control circuit for coordinating the operation of the analog and digital error correction circuits. During calibration operations, the analog error correction circuit may be used to suitably adjust a gain setting for each pipeline stage, whereas the digital error correction circuit may be used to compute a code offset value for each pipeline stage. Calibration may proceed from a least-significant-bit pipeline stage towards a most-significant-bit pipeline stage, one stage at a time.
摘要翻译：提供了具有管线模数（A / D）转换器和相关校准电路的集成电路。 A / D转换器可以包括多个串联连接的流水线级，其中至少一些使用开关电容器配置来实现。校准电路可以包括模拟误差校正电路，数字误差校正电路和用于协调模拟和数字纠错电路的操作的校准控制电路。在校准操作期间，可以使用模拟错误校正电路来适当地调整每个流水线级的增益设置，而数字纠错电路可以用于计算每个流水线级的代码偏移值。校准可以从最低有效位流水线阶段进入最高有效位流水线阶段，一次一个阶段。

57. 发明授权

US08612795B1 Segmented clock network for transceiver array 有权
标题翻译：收发器阵列的分段时钟网络
公开(公告)号：US08612795B1
公开(公告)日：2013-12-17
申请号：US12847268
申请日：2010-07-30
申请人： Weiqi Ding , Kumara Tharmalingam
发明人： Weiqi Ding , Kumara Tharmalingam
IPC分类号： G06F1/04
CPC分类号： G06F1/10 , G11C7/222
摘要： One embodiment relates to a clocking network interconnecting an array of transceivers. The clocking network includes first and second series of multiplexers, each multiplexer in the first and second series being adjacent to a transceiver. The first series of multiplexers selectively transmits clock signals in a first direction of the array, and the second series of multiplexers selectively transmits clock signals in a second direction of the array. Another embodiment relates to an integrated circuit with a programmable interface. The integrated circuit includes an array of physical media attachment circuits, phase-locked loop circuits, and a clock distribution network. The clock distribution network is arranged to be programmed into multiple segments. Each segment distributes a clock signal to a bounded range of the physical media attachment circuits in the array. Another embodiment relates to a method of distributing clock signals in an integrated circuit. Other embodiments and features are also disclosed.
摘要翻译：一个实施例涉及互连收发器阵列的时钟网络。时钟网络包括第一和第二系列多路复用器，第一和第二系列中的每个多路复用器与收发器相邻。第一系列多路复用器选择性地在阵列的第一方向上传输时钟信号，并且第二系列多路复用器选择性地在阵列的第二方向上传输时钟信号。另一实施例涉及具有可编程接口的集成电路。集成电路包括物理介质连接电路，锁相环电路和时钟分配网络的阵列。时钟分配网络被布置成被编程成多个段。每个段将时钟信号分配到阵列中物理介质连接电路的有界范围。另一实施例涉及在集成电路中分配时钟信号的方法。还公开了其它实施例和特征。

58. 发明授权

US07924046B1 Configurable emphasis for high-speed transmitter driver circuitry 有权
标题翻译：配置强调高速发射器驱动电路
公开(公告)号：US07924046B1
公开(公告)日：2011-04-12
申请号：US12776871
申请日：2010-05-10
申请人： Weiqi Ding
发明人： Weiqi Ding
IPC分类号： H03K17/16
CPC分类号： H04L25/0286
摘要： Pre-emphasis may be able to operate in either of two modes. In a first mode, when one bit has a same value as the bit that immediately preceded it, an output signal for said one bit is based on a first electrical current reduced by a second electrical current. Otherwise the output signal for said one bit is based on the first current without regard for the second current. The second mode may be similar to the first mode when said one bit has the same value as the immediately preceding bit; but otherwise the output signal for said one bit is based on the first current increased by the second current. As an alternative to using the immediately preceding bit (as in the above “post-tap” operation), the immediately succeeding (following) bit may be used in generally the same way (in so-called “pre-tap” operation).
摘要翻译：预加重可能能够以两种模式中的任一种运行。在第一模式中，当一位与其之前的位具有相同的值时，所述一位的输出信号基于由第二电流减小的第一电流。否则，所述一位的输出信号基于第一电流而不考虑第二电流。当所述一个比特具有与前一比特相同的值时，第二模式可以类似于第一模式; 否则所述一位的输出信号基于第二电流增加的第一电流。作为使用紧接在前的位（如在上述“后抽头”操作中）的替代方案，可以以大致相同的方式（在所谓的“预抽头”操作）中使用紧随其后的（后续）位。

59. 发明授权

US09224685B1 Shielded metal-oxide-metal (MOM) capacitor structure 有权
标题翻译：屏蔽金属氧化物金属（MOM）电容器结构
公开(公告)号：US09224685B1
公开(公告)日：2015-12-29
申请号：US13416137
申请日：2012-03-09
申请人： Weiqi Ding , Wilson Wong , Shuxian Chen , Jeffrey T. Watt
发明人： Weiqi Ding , Wilson Wong , Shuxian Chen , Jeffrey T. Watt
IPC分类号： H01L23/522 , H01L49/02
CPC分类号： H01L23/5226 , H01L23/522 , H01L23/5223 , H01L23/5225 , H01L28/82 , H01L28/86 , H01L2924/0002 , H01L2924/00
摘要： A metal-oxide-metal (MOM) capacitor structure is disclosed. The MOM capacitor includes a plurality of layers, each layer having a plurality of electrodes. The plurality of electrodes, separated by oxide layers, forms a first plate and a second plate of the MOM capacitor. The plurality of electrodes on each of the layers is coupled to a plurality of electrodes on an adjacent layer through a plurality of vias. A shield layer is coupled to each of the electrodes that forms the second plate of the MOM capacitor on each of the plurality of layers.
摘要翻译：公开了一种金属氧化物金属（MOM）电容器结构。 MOM电容器包括多个层，每层具有多个电极。由氧化物层分隔开的多个电极形成MOM电容器的第一板和第二板。每个层上的多个电极通过多个通孔耦合到相邻层上的多个电极。屏蔽层耦合到在多个层中的每一层上形成MOM电容器的第二板的每个电极。

60. 发明授权

US08860469B1 Apparatus and methods for transmitter output swing calibration 有权
标题翻译：发射机输出摆幅校准的装置和方法
公开(公告)号：US08860469B1
公开(公告)日：2014-10-14
申请号：US13549228
申请日：2012-07-13
申请人： Weiqi Ding , Wilson Wong
发明人： Weiqi Ding , Wilson Wong
IPC分类号： H03B1/00 , H03K3/00
CPC分类号： G11C29/028 , G11C29/022
摘要： Disclosed are apparatus and methods to advantageously calibrate a transmitter output swing. One embodiment relates to a method for calibrating the output swing voltage of a transmitter. A fixed value is provided as the data input, and output swing calibration circuitry is connected to the transmitter buffer circuit. A transmitter current is set to an initial level, and the transmitter current is adjusted until the output swing of the transmitter buffer circuit is calibrated. Another embodiment relates to an integrated circuit which includes a transmitter buffer circuit, output swing calibration circuitry, and switches arranged to electrically connect the transmitter buffer circuit to the output swing calibration circuitry during an output swing calibration mode. Another embodiment relates to an output swing calibration circuit which includes comparison circuitry and logic and control circuitry.
摘要翻译：公开了有利地校准发射机输出摆幅的装置和方法。一个实施例涉及用于校准发射机的输出摆幅电压的方法。提供固定值作为数据输入，输出摆幅校准电路连接到发送器缓冲电路。发射机电流被设置为初始电平，并且调整发射机电流直到校准发射机缓冲器电路的输出摆幅。另一个实施例涉及一种集成电路，其包括发射器缓冲电路，输出摆幅校准电路和布置成在输出摆幅校准模式期间将发射器缓冲电路电连接到输出摆幅校准电路。另一个实施例涉及一种包括比较电路和逻辑和控制电路的输出摆幅校准电路。

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