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51. 发明授权

US07791161B2 Semiconductor devices employing poly-filled trenches 有权
标题翻译：采用多晶填充沟槽的半导体器件
公开(公告)号：US07791161B2
公开(公告)日：2010-09-07
申请号：US11213069
申请日：2005-08-25
申请人： Ronghua Zhu , Vishnu K. Khemka , Amitava Bose
发明人： Ronghua Zhu , Vishnu K. Khemka , Amitava Bose
IPC分类号： H01L29/00
CPC分类号： H01L29/0878 , H01L23/3677 , H01L29/0649 , H01L29/0653 , H01L29/0847 , H01L29/1083 , H01L29/1087 , H01L29/66659 , H01L29/66681 , H01L29/732 , H01L29/7816 , H01L29/7824 , H01L29/7835 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： Structure and method are provided for semiconductor devices. The devices include trenches filled with highly doped polycrystalline semiconductor, extending from the surface into the body of the device for, among other things: (i) reducing substrate current injection, (ii) reducing ON-resistance and/or (iii) reducing thermal impedance to the substrate. For isolated LDMOS devices, the resistance between the lateral isolation wall (tied to the source) and the buried layer is reduced, thereby reducing substrate injection current. When placed in the drain of a lateral device or in the collector of a vertical device, the poly-filled trench effectively enlarges the drain or collector region, thereby lowering the ON-resistance. For devices formed on an oxide isolation layer, the poly-filled trench desirably penetrates this isolation layer thereby improving thermal conduction from the active regions to the substrate. The poly filled trenches are conveniently formed by etch and refill. Significant area savings are also achieved.
摘要翻译：为半导体器件提供了结构和方法。这些器件包括填充有高掺杂多晶半导体的沟槽，其从表面延伸到器件的主体中，其中包括：（i）减少衬底电流注入，（ii）降低导通电阻和/或（iii）减少热对基片的阻抗。对于孤立的LDMOS器件，横向隔离壁（连接到源极）和掩埋层之间的电阻降低，从而降低衬底注入电流。当放置在垂直装置的横向装置或收集器的漏极中时，多晶硅填充沟槽有效地放大了漏极或集电极区域，从而降低了导通电阻。对于形成在氧化物隔离层上的器件，多晶填充沟槽期望地穿透该隔离层，从而改善从有源区到衬底的热传导。多孔填充沟槽通过蚀刻和再填充方便地形成。也实现了显着的面积节省。

52. 发明授权

US07763937B2 Variable resurf semiconductor device and method 有权
标题翻译：可变复用半导体器件及方法
公开(公告)号：US07763937B2
公开(公告)日：2010-07-27
申请号：US11601127
申请日：2006-11-15
申请人： Vishnu K. Khemka , Amitava Bose , Todd C. Roggenbauer , Ronghua Zhu
发明人： Vishnu K. Khemka , Amitava Bose , Todd C. Roggenbauer , Ronghua Zhu
IPC分类号： H01L29/00
CPC分类号： H01L29/063 , H01L29/1083 , H01L29/66659 , H01L29/7835
摘要： Methods and apparatus are provided for semiconductor device (60, 95, 100, 106). The semiconductor device (60, 95, 100, 106), comprises a first region (64, 70) of a first conductivity type extending to a first surface (80), a second region (66) of a second, opposite, conductivity type forming with the first region (70) a first PN junction (65) extending to the first surface (80), a contact region (68) of the second conductivity type in the second region (66) at the first surface (80) and spaced apart from the first PN junction (65) by a first distance (LDS), and a third region (82, 96-98, 108) of the first conductivity type and of a second length (LBR), underlying the second region (66) and forming a second PN junction (63) therewith spaced apart from the first surface (80) and located closer to the first PN junction (65) than to the contact region (68). The breakdown voltage is enhanced without degrading other useful properties of the device (60, 95, 100, 106).
摘要翻译：为半导体器件（60,95,100,106）提供了方法和装置。半导体器件（60,95,100,106）包括延伸到第一表面（80）的第一导电类型的第一区域（64,70），第二相对导电类型的第二区域（66）与所述第一区域（70）形成延伸到所述第一表面（80）的第一PN结（65），在所述第一表面（80）处的所述第二区域（66）中的所述第二导电类型的接触区域（68）与第一PN结（65）间隔开第一距离（LDS），以及第二导电类型和第二长度（LBR）的第三区域（82,96-98,108），位于第二区域并且与第一表面（80）间隔开并且位于比接触区域（68）更靠近第一PN结（65）的位置处形成第二PN结（63）。提高击穿电压，而不会降低器件（60,95,100,106）的其他有用特性。

53. 发明申请

US20090174030A1 LINEARITY CAPACITOR STRUCTURE AND METHOD 有权
标题翻译：线性电容器结构与方法
公开(公告)号：US20090174030A1
公开(公告)日：2009-07-09
申请号：US11969600
申请日：2008-01-04
申请人： Tahir A. Khan , Amitava Bose , Vishnu K. Khemka , Ronghua Zhu
发明人： Tahir A. Khan , Amitava Bose , Vishnu K. Khemka , Ronghua Zhu
IPC分类号： H01L21/283 , H01L29/94
CPC分类号： H01L29/94 , H01L21/86 , H01L29/20 , H01L29/22 , H01L29/66181
摘要： Method (200) and apparatus (30, 50-53) are described for MOS capacitors (MOS CAPs). The apparatus (30, 50-53) comprises a substrate (31) having Ohmically coupled N and P semiconductor regions (32, 34; 54, 56; 92, 94) covered by a dielectric (35, 57, 95). A conductive electrode (36, 58, 96) overlies the dielectric (35, 57, 95) above these N and P regions (32, 34; 54, 56; 92, 94). Use of the Ohmically coupled N and P regions (32, 34; 54, 56; 92, 94) substantially reduces the variation (40, 64, 70, 80) of capacitance with applied voltage associated with ordinary MOS CAPs. When these N and P regions (32, 34; 54, 56; 92, 94) have unequal doping, the capacitance variation (40, 64, 70, 80) may still be substantially compensated by adjusting the properties of the dielectric (57, 95) above the N and P regions (54, 56; 92, 94) and/or relative areas of the N and P regions (54, 56; 92, 94) or both. Accordingly, such MOS CAPS may be more easily integrated with other semiconductor devices with minimal or no disturbance to the established integrated circuit (IC) manufacturing process and without significantly increasing the occupied area beyond that required for a conventional MOS CAP.
摘要翻译：对于MOS电容器（MOS CAP）描述了方法（200）和装置（30,50-53）。装置（30,50-53）包括具有由电介质（35,57,95）覆盖的欧姆耦合的N和P半导体区域（32,34; 54,56; 92,94）的衬底（31）。导电电极（36,58,96）覆盖在这些N和P区域（32,34; 54,56; 92,94）上方的电介质（35,57,95）上。使用欧姆耦合的N和P区域（32,34; 54,56; 92,94）通过与普通MOS CAP相关联的施加电压基本上减小电容的变化（40,64,70,80）。当这些N和P区域（32,34; 54,56; 92,94）具有不同的掺杂时，电容变化（40,64,70,80）仍然可以通过调节电介质的性质（57，（54,56; 92,94）的N区域和/或P区域（54,56; 92,94）或两者的相对区域之间。因此，这样的MOS CAPS可以更容易地与其他半导体器件集成，对所建立的集成电路（IC）制造过程具有最小或没有干扰，并且不会显着地增加超过常规MOS CAP所需的占用面积。

54. 发明授权

US07436025B2 Termination structures for super junction devices 有权
标题翻译：超连接器件的端接结构
公开(公告)号：US07436025B2
公开(公告)日：2008-10-14
申请号：US11540770
申请日：2006-09-29
申请人： Ronghua Zhu , Amitava Bose , Vishnu K. Khemka , Todd C. Roggenbauer
发明人： Ronghua Zhu , Amitava Bose , Vishnu K. Khemka , Todd C. Roggenbauer
IPC分类号： H01L29/76
CPC分类号： H01L29/0634 , H01L29/0653 , H01L29/0692 , H01L29/1045 , H01L29/66659 , H01L29/7835 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device 10 is provided. A first layer 12 has a first dopant type; a second layer 14 is provided over the first layer 12; and a third layer 16 is provided over the second layer and has the first dopant type. A plurality of first and second semiconductor regions 22, 24 are within the third layer. The first semiconductor region 22 has the first dopant type, and the second semiconductor region 24 has the second dopant type. The first and second semiconductor regions 22, 24 are disposed laterally to one another in an alternating pattern to form a super junction, and the super junction terminates with a final second semiconductor region 24, 24′ of the second dopant type.
摘要翻译：提供半导体器件10。第一层12具有第一掺杂剂类型; 在第一层12上设置第二层14; 并且第三层16设置在第二层上并且具有第一掺杂剂类型。多个第一和第二半导体区域22,24在第三层内。第一半导体区域22具有第一掺杂剂类型，第二半导体区域24具有第二掺杂剂类型。第一和第二半导体区域22,24以交替图案彼此横向地设置以形成超结，并且超结终止于第二掺杂剂类型的最终第二半导体区域24,24'。

55. 发明授权

US07329566B2 Semiconductor device and method of manufacture 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07329566B2
公开(公告)日：2008-02-12
申请号：US11142111
申请日：2005-05-31
申请人： Vishnu K. Khemka , Amitava Bose , Ronghua Zhu
发明人： Vishnu K. Khemka , Amitava Bose , Ronghua Zhu
IPC分类号： H01L21/332 , H01L21/336
CPC分类号： H01L29/7393 , H01L29/66325
摘要： A semiconductor component and method of manufacture, including an insulated gate bipolar transistor (IGBT) (100, 200) that includes a semiconductor substrate (110) having a first conductivity type and buried semiconductor region (115) having a second conductivity type located above the semiconductor substrate. The IGBT further includes a first semiconductor region (120) having the first conductivity type located above the buried semiconductor region, a second semiconductor region (130) having the second conductivity type located above at least a portion of the first semiconductor region, an emitter (150) having the second conductivity type disposed in the second semiconductor region, and a collector (170) having the second conductivity type disposed in the first semiconductor region. A sinker region (140) is provided to electrically tie the buried semiconductor region (115) to the second semiconductor region (130). In a particular embodiment, the second semiconductor region and the buried semiconductor region deplete the first semiconductor region in response to a reverse bias potential applied across the semiconductor component.
摘要翻译：一种半导体元件和制造方法，包括绝缘栅双极晶体管（IGBT）（100,200），其包括具有第一导电类型的半导体衬底（110）和具有第二导电类型的掩埋半导体区域（115）半导体衬底。 IGBT还包括具有位于掩埋半导体区域上方的第一导电类型的第一半导体区域（120），具有位于第一半导体区域的至少一部分上方的第二导电类型的第二半导体区域（130），发射极 150），并且具有设置在第一半导体区域中的具有第二导电类型的集电极（170）。提供沉降片区域（140）以将掩埋的半导体区域（115）电连接到第二半导体区域（130）。在特定实施例中，响应于施加在半导体部件上的反向偏置电位，第二半导体区域和掩埋半导体区域耗尽第一半导体区域。

56. 发明授权

US07439584B2 Structure and method for RESURF LDMOSFET with a current diverter 有权
标题翻译：具有电流分流器的RESURF LDMOSFET的结构和方法
公开(公告)号：US07439584B2
公开(公告)日：2008-10-21
申请号：US11363901
申请日：2006-02-28
申请人： Vishnu K. Khemka , Amitava Bose , Todd C. Roggenbauer , Ronghua Zhu
发明人： Vishnu K. Khemka , Amitava Bose , Todd C. Roggenbauer , Ronghua Zhu
IPC分类号： H01L29/76 , H01L29/94
CPC分类号： H01L29/8611 , H01L29/063 , H01L29/0653 , H01L29/1045 , H01L29/1083 , H01L29/7835
摘要： Methods and apparatus are provided for reducing substrate leakage current of RESURF LDMOSFET devices. A semiconductor device comprises a semiconductor substrate (22) of a first type; first and second terminals (39,63) laterally spaced-apart on a surface (35) above the substrate; a first semiconductor region (32) of the first type overlying the substrate and ohmically coupled to the first terminal (39); a second semiconductor region (48) of a second opposite type in proximity to the first region and ohmically coupled to the first terminal; a third semiconductor region (30) of the second type overlying the substrate and ohmically coupled to the second terminal (63) and laterally arranged with respect to the first region; a parasitic vertical device comprising the first region and the substrate, the parasitic vertical device for permitting leakage current to flow from the first terminal to the substrate; a fourth semiconductor region (62) of the first type in proximity to the third region and ohmically coupled to the second terminal, thereby forming in combination with the third region a shorted base-collector region of a lateral transistor extending between the first and second terminals to provide diode action; a channel region (27) of the first type separating the first and third regions at the surface; a gate insulator (43) overlying the channel region; and a gate electrode (42) overlying the gate insulator.
摘要翻译：提供了减少RESURF LDMOSFET器件的衬底漏电流的方法和装置。半导体器件包括第一类型的半导体衬底（22）在衬底上方的表面（35）上横向间隔开的第一和第二端子（39,63）第一类型的第一半导体区域（32），覆盖衬底并欧姆耦合到第一端子（39）; 邻近第一区域的第二相对类型的第二半导体区域（48），并且欧姆耦合到第一端子; 第二类型的第三半导体区域（30），覆盖在所述衬底上并且欧姆耦合到所述第二端子（63）并且相对于所述第一区域横向布置; 包括第一区域和衬底的寄生垂直器件，用于允许漏电流从第一端子流到衬底的寄生垂直器件; 第一类型的第四半导体区域（62），邻近第三区域并且欧姆耦合到第二端子，从而与第三区域组合形成在第一和第二端子之间延伸的横向晶体管的短路基极集电极区域提供二极管动作; 所述第一类型的沟道区域（27）在所述表面处分隔所述第一和第三区域; 栅极绝缘体（43），覆盖所述沟道区域; 以及覆盖栅极绝缘体的栅电极（42）。

57. 发明授权

US07405128B1 Dotted channel MOSFET and method 有权
标题翻译：点通道MOSFET及方法
公开(公告)号：US07405128B1
公开(公告)日：2008-07-29
申请号：US11674888
申请日：2007-02-14
申请人： Vishnu K. Khemka , Amitava Bose , Todd C. Roggenbauer , Ronghua Zhu
发明人： Vishnu K. Khemka , Amitava Bose , Todd C. Roggenbauer , Ronghua Zhu
IPC分类号： H01L21/336
CPC分类号： H01L29/7835 , H01L29/0692 , H01L29/1045 , H01L29/1087 , H01L29/4238 , H01L29/66659 , H01L29/78
摘要： A improved MOSFET (50, 51, 75, 215) has a source (60) and drain (62) in a semiconductor body (56), surmounted by an insulated control gate (66) located over the body (56) between the source (60) and drain (62) and adapted to control a conductive channel (55) extending between the source (60) and drain (62). The insulated gate (66) is perforated by a series of openings (61) through which highly doped regions (69) in the form of a series of (e.g., square) dots (69) of the same conductivity type as the body (56) are provided, located in the channel (55), spaced apart from each other and from the source (60) and drain (62). These channel dots (69) are desirably electrically coupled to a highly doped contact (64) to the body (56). The resulting device (50, 51, 75, 215) has a greater SOA, higher breakdown voltage and higher HBM stress resistance than equivalent prior art devices (20) without the dotted channel. Threshold voltage is not affected.
摘要翻译：改进的MOSFET（50,51,75,215）在半导体本体（56）中具有源极（60）和漏极（62），其被位于源极（56）之间的绝缘控制栅极（66）所覆盖，（60）和漏极（62），并且适于控制在源极（60）和漏极（62）之间延伸的导电通道（55）。绝缘栅极（66）由一系列开口（61）穿孔，通过该开口（61），与体（56）相同导电类型的一系列（例如，正方形）点（69）形式的高度掺杂区域（69）穿过该开口）设置在通道（55）中，彼此间隔开并且与源（60）和排水口（62）间隔开。这些通道点（69）期望地电耦合到主体（56）的高度掺杂的触点（64）。所得到的器件（50,51,75,215）具有比没有点通道的等效现有技术器件（20）更大的SOA，更高的击穿电压和更高的HBM应力电阻。阈值电压不受影响。

58. 发明申请

US20080122025A1 ELECTRONIC DEVICE INCLUDING A CONDUCTIVE STRUCTURE EXTENDING THROUGH A BURIED INSULATING LAYER 有权
标题翻译：电子设备，包括通过绝缘绝缘层延伸的导电结构
公开(公告)号：US20080122025A1
公开(公告)日：2008-05-29
申请号：US11556576
申请日：2006-11-03
申请人： Todd C. Roggenbauer , Vishnu K. Khemka , Ronghua Zhu , Amitava Bose , Paul Hui , Xiaoqiu Huang
发明人： Todd C. Roggenbauer , Vishnu K. Khemka , Ronghua Zhu , Amitava Bose , Paul Hui , Xiaoqiu Huang
IPC分类号： H01L27/00
CPC分类号： H01L27/105 , H01L21/76264 , H01L21/84 , H01L27/1203 , H01L27/13
摘要： An electronic device can include a substrate, a buried insulating layer overlying the substrate, and a semiconductor layer overlying the buried insulating layer, wherein the semiconductor layer is substantially monocrystalline. The electronic device can also include a conductive structure extending through the semiconductor layer and buried insulating layer and abutting the substrate, and an insulating spacer lying between the conductive structure and each of the semiconductor layer and the buried insulating layer.
摘要翻译：电子器件可以包括衬底，覆盖衬底的掩埋绝缘层和覆盖掩埋绝缘层的半导体层，其中半导体层基本上是单晶的。电子器件还可以包括延伸穿过半导体层和掩埋绝缘层并邻接衬底的导电结构，以及位于导电结构与半导体层和埋入绝缘层中的每一个之间的绝缘衬垫。

59. 发明申请

US20080079122A1 Termination structures for super junction devices 有权
公开(公告)号：US20080079122A1
公开(公告)日：2008-04-03
申请号：US11540770
申请日：2006-09-29
申请人： Ronghua Zhu , Amitava Bose , Vishnu K. Khemka , Todd C. Roggenbauer
发明人： Ronghua Zhu , Amitava Bose , Vishnu K. Khemka , Todd C. Roggenbauer
IPC分类号： H01L23/58
CPC分类号： H01L29/0634 , H01L29/0653 , H01L29/0692 , H01L29/1045 , H01L29/66659 , H01L29/7835 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device 10 is provided. A first layer 12 has a first dopant type; a second layer 14 is provided over the first layer 12; and a third layer 16 is provided over the second layer and has the first dopant type. A plurality of first and second semiconductor regions 22, 24 are within the third layer. The first semiconductor region 22 has the first dopant type, and the second semiconductor region 24 has the second dopant type. The first and second semiconductor regions 22, 24 are disposed laterally to one another in an alternating pattern to form a super junction, and the super junction terminates with a final second semiconductor region 24, 24′ of the second dopant type.

60. 发明申请

US20080265291A1 MOSFET DEVICE INCLUDING A SOURCE WITH ALTERNATING P-TYPE AND N-TYPE REGIONS 有权
标题翻译：包括具有替代P型和N型区域的源的MOSFET器件
公开(公告)号：US20080265291A1
公开(公告)日：2008-10-30
申请号：US11742363
申请日：2007-04-30
申请人： Ronghua Zhu , Amitava Bose , Vishnu K. Khemka , Todd C. Roggenbauer
发明人： Ronghua Zhu , Amitava Bose , Vishnu K. Khemka , Todd C. Roggenbauer
IPC分类号： H01L29/94 , H01L21/336
CPC分类号： H01L29/0847 , H01L29/0692 , H01L29/1087 , H01L29/456 , H01L29/7835
摘要： Apparatus and methods are provided for fabricating semiconductor devices with reduced bipolar effects. One apparatus includes a semiconductor body (120) including a surface and a transistor source (300) located in the semiconductor body proximate the surface, and the transistor source includes an area (310) of alternating conductivity regions (3110, 3120). Another apparatus includes a semiconductor body (120) including a first conductivity and a transistor source (500) located in the semiconductor body. The transistor source includes multiple regions (5120) including a second conductivity, wherein the regions and the semiconductor body form an area (510) of alternating regions of the first and second conductivities. One method includes implanting a semiconductor well (120) including a first conductivity in a substrate (110) and implanting a plurality of doped regions (5120) comprising a second conductivity in the semiconductor well. An area (510) comprising regions of alternating conductivities is then formed in the semiconductor well.
摘要翻译：提供了用于制造具有降低的双极效应的半导体器件的装置和方法。一种装置包括半导体本体（120），其包括位于半导体本体附近的表面和晶体管源（300），并且晶体管源包括交替导电区域（3110,3120）的区域（310）。另一种装置包括：半导体本体（120），其包括位于半导体本体中的第一导电性和晶体管源（500）。晶体管源包括包括第二导电性的多个区域（5120），其中所述区域和半导体主体形成第一和第二电导率的交替区域的区域（510）。一种方法包括在衬底（110）中注入包括第一导电性的半导体阱（120），并在半导体阱中注入包含第二导电性的多个掺杂区域（5120）。然后在半导体阱中形成包括交变电导率区域的区域（510）。

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