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51. 发明申请

US20140095891A1 INSTRUCTION SET FOR SHA1 ROUND PROCESSING ON 128-BIT DATA PATHS 有权
标题翻译： 128位数据表上的SHA1加工指令集
公开(公告)号：US20140095891A1
公开(公告)日：2014-04-03
申请号：US13631150
申请日：2012-09-28
申请人： Gilbert M. Wolrich , Kirk S. Yap , Vinodh Gopal , Sean M. Gulley , James D. Guilford
发明人： Gilbert M. Wolrich , Kirk S. Yap , Vinodh Gopal , Sean M. Gulley , James D. Guilford
IPC分类号： G06F21/22
CPC分类号： G06F21/72 , G06F9/30007 , G06F9/30036 , H04L9/0643
摘要： According to one embodiment, a processor includes an instruction decoder to receive a first instruction to process a SHA1 hash algorithm, the first instruction having a first operand, a second operand, and a third operand, the first operand specifying a first storage location storing four SHA states, the second operand specifying a second storage location storing a plurality of SHA1 message inputs in combination with a fifth SHA1 state. The processor further includes an execution unit coupled to the instruction decoder, in response to the first instruction, to perform at least four rounds of the SHA1 round operations on the SHA1 states and the message inputs obtained from the first and second operands, using a combinational logic function specified in the third operand.
摘要翻译：根据一个实施例，处理器包括指令解码器，用于接收处理SHA1散列算法的第一指令，所述第一指令具有第一操作数，第二操作数和第三操作数，所述第一操作数指定存储四个 SHA指出，第二操作数指定存储与第五SHA1状态相结合的多个SHA1消息输入的第二存储位置。所述处理器还包括执行单元，其响应于所述第一指令而耦合到所述指令解码器，以使用所述第一和第二操作数获得的所述SHA1状态和从所述第一和第二操作数获得的所述消息输入执行至少四轮所述SHA1循环操作，逻辑功能在第三个操作数中指定。

52. 发明授权

US09052985B2 Method and apparatus for efficient programmable cyclic redundancy check (CRC) 有权
标题翻译：用于高效可编程循环冗余校验（CRC）的方法和装置
公开(公告)号：US09052985B2
公开(公告)日：2015-06-09
申请号：US11963147
申请日：2007-12-21
申请人： Vinodh Gopal , Erdinc Ozturk , Gilbert M. Wolrich , Wajdi K. Feghali
发明人： Vinodh Gopal , Erdinc Ozturk , Gilbert M. Wolrich , Wajdi K. Feghali
IPC分类号： G06F7/72 , H03M13/09
CPC分类号： G06F7/724 , G06F7/72 , H03M13/09
摘要： A method and apparatus to optimize each of the plurality of reduction stages in a Cyclic Redundancy Check (CRC) circuit to produce a residue for a block of data decreases area used to perform the reduction while maintaining the same delay through the plurality of stages of the reduction logic. A hybrid mix of Karatsuba algorithm, classical multiplications and serial division in various stages in the CRC reduction circuit results in about a twenty percent reduction in area on the average with no decrease in critical path delay.
摘要翻译：一种在循环冗余校验（CRC）电路中优化多个还原级中的每一个以产生数据块的残差的方法和装置减少了用于执行减少的区域，同时通过多个阶段保持相同的延迟还原逻辑。在CRC减少电路中，Karatsuba算法，经典乘法和串行划分的混合混合结果导致平均面积减少了约20％，而关键路径延迟没有减少。

53. 发明申请

US20080240422A1 Efficient advanced encryption standard (AES) Datapath using hybrid rijndael S-Box 失效
标题翻译：高效的高级加密标准（AES）使用混合rijndael S-Box的数据路径
公开(公告)号：US20080240422A1
公开(公告)日：2008-10-02
申请号：US11731159
申请日：2007-03-30
申请人： Erdinc Ozturk , Vinodh Gopal , Gilbert Wolrich , Wajdi K. Feghali , Kirk S. Yap
发明人： Erdinc Ozturk , Vinodh Gopal , Gilbert Wolrich , Wajdi K. Feghali , Kirk S. Yap
IPC分类号： H04L9/00
CPC分类号： H04L9/0631 , G06F9/30007 , H04L2209/12
摘要： The speed at which an AES decrypt operation may be performed in a general purpose processor is increased by providing a separate decrypt data path. The critical path delay of the aes decrypt path is reduced by combining multiply and inverse operations in the Inverse SubBytes transformation. A further decrease in critical path delay in the aes decrypt data path is provided by merging appropriate constants of the inverse mix-column transform into a map function.
摘要翻译：可以通过提供单独的解密数据路径来增加在通用处理器中执行AES解密操作的速度。通过在逆SubBytes变换中组合乘法和逆运算来减少aes解密路径的关键路径延迟。通过将反混合列变换的适当常数合并到映射函数中来提供aes解密数据路径中关键路径延迟的进一步减小。

54. 发明申请

US20080240421A1 Method and apparatus for advanced encryption standard (AES) block cipher 有权
标题翻译：高级加密标准（AES）块密码的方法和装置
公开(公告)号：US20080240421A1
公开(公告)日：2008-10-02
申请号：US11731158
申请日：2007-03-30
申请人： Vinodh Gopal , Erdinc Ozturk , Gilbert Wolrich , Wajdi K. Feghali , Kirk S. Yap
发明人： Vinodh Gopal , Erdinc Ozturk , Gilbert Wolrich , Wajdi K. Feghali , Kirk S. Yap
IPC分类号： H04L9/00
CPC分类号： H04L9/0631 , G06F9/30007 , H04L2209/125
摘要： The speed at which encrypt and decrypt operations may be performed in a general purpose processor is increased by providing a separate encrypt data path and decrypt data path. With separate data paths, each of the data paths may be individually optimized in order to reduce delays in a critical path. In addition, delays may be hidden in a non-critical last round.
摘要翻译：可以通过提供单独的加密数据路径和解密数据路径来增加在通用处理器中执行加密和解密操作的速度。利用单独的数据路径，可以单独优化每个数据路径以减少关键路径中的延迟。此外，延迟可能隐藏在非关键的最后一轮。

55. 发明授权

US09203887B2 Bitstream processing using coalesced buffers and delayed matching and enhanced memory writes 有权
标题翻译：使用合并缓冲区和延迟匹配和增强存储器写入的位流处理
公开(公告)号：US09203887B2
公开(公告)日：2015-12-01
申请号：US13994129
申请日：2011-12-23
申请人： Vinodh Gopal , Jim D. Guilford , Gilbert M. Wolrich , Wajdi K. Feghali , Deniz Karakoyunlu , Erdinc Ozturk , Martin Dixon , Kahraman Akdemir
发明人： Vinodh Gopal , Jim D. Guilford , Gilbert M. Wolrich , Wajdi K. Feghali , Deniz Karakoyunlu , Erdinc Ozturk , Martin Dixon , Kahraman Akdemir
IPC分类号： H04L29/06 , H04W28/06 , H03M7/30
CPC分类号： H04L65/607 , H03M7/30 , H03M7/3086 , H04L65/608 , H04L69/04 , H04L69/22 , H04W28/06
摘要： Methods and apparatus for processing bitstreams and byte streams. According to one aspect, bitstream data is compressed using coalesced string match tokens with delayed matching. A matcher is employed to perform search string match operations using a shortened maximum string length search criteria, resulting in generation of a token stream having data and literal data. A distance match operation is performed on sequentially adjacent tokens to determine if they contain the same distance data. If they do, the len values of the tokens are added through use of a coalesce buffer. Upon detection of a distance non-match, a final coalesced length of a matching string is calculated and output along with the prior matching distance as a coalesced token. Also disclosed is a scheme for writing variable-length tokens into a bitstream under which token data is input into a bit accumulator and written to memory (or cache to be subsequently written to memory) as each token is processed in a manner that eliminates branch mispredict operations associated with detecting whether the bit accumulator is full or close to full.
摘要翻译：用于处理比特流和字节流的方法和装置。根据一个方面，使用具有延迟匹配的合并字符串匹配令牌来压缩比特流数据。使用匹配器来执行搜索字符串匹配操作，使用缩短的最大字符串长度搜索条件，导致生成具有数据和文字数据的令牌流。对顺序相邻的令牌执行距离匹配操作，以确定它们是否包含相同的距离数据。如果这样做，令牌的len值通过使用合并缓冲区来添加。在检测到距离不匹配时，计算匹配串的最终合并长度，并将其与先前匹配距离一起作为合并令牌输出。还公开了一种用于将可变长度令牌写入比特流的方案，在该比特流中，令牌数据被输入到比特累加器中，并且以消除分支错误预测的方式将每个令牌进行处理，并将其写入存储器（或高速缓存以随后写入存储器）检测位累加器是满或接近满的操作。

56. 发明授权

US08346839B2 Efficient advanced encryption standard (AES) datapath using hybrid rijndael S-box 失效
标题翻译：使用混合rijndael S盒的高效加密标准（AES）数据通路
公开(公告)号：US08346839B2
公开(公告)日：2013-01-01
申请号：US11731159
申请日：2007-03-30
申请人： Erdinc Ozturk , Vinodh Gopal , Gilbert Wolrich , Wajdi K. Feghali , Kirk S. Yap
发明人： Erdinc Ozturk , Vinodh Gopal , Gilbert Wolrich , Wajdi K. Feghali , Kirk S. Yap
IPC分类号： G06F7/52
CPC分类号： H04L9/0631 , G06F9/30007 , H04L2209/12
摘要： The speed at which an AES decrypt operation may be performed in a general purpose processor is increased by providing a separate decrypt data path. The critical path delay of the aes decrypt path is reduced by combining multiply and inverse operations in the Inverse SubBytes transformation. A further decrease in critical path delay in the aes decrypt data path is provided by merging appropriate constants of the inverse mix-column transform into a map function.
摘要翻译：可以通过提供单独的解密数据路径来增加在通用处理器中执行AES解密操作的速度。通过在逆SubBytes变换中组合乘法和逆运算来减少aes解密路径的关键路径延迟。通过将反混合列变换的适当常数合并到映射函数中来提供aes解密数据路径中关键路径延迟的进一步减小。

57. 发明授权

US08391475B2 Method and apparatus for advanced encryption standard (AES) block cipher 有权
标题翻译：高级加密标准（AES）块密码的方法和装置
公开(公告)号：US08391475B2
公开(公告)日：2013-03-05
申请号：US11731158
申请日：2007-03-30
申请人： Vinodh Gopal , Erdinc Ozturk , Gilbert Wolrich , Wajdi K. Feghali , Kirk S. Yap
发明人： Vinodh Gopal , Erdinc Ozturk , Gilbert Wolrich , Wajdi K. Feghali , Kirk S. Yap
IPC分类号： H04K1/00
CPC分类号： H04L9/0631 , G06F9/30007 , H04L2209/125
摘要： The speed at which encrypt and decrypt operations may be performed in a general purpose processor is increased by providing a separate encrypt data path and decrypt data path. With separate data paths, each of the data paths may be individually optimized in order to reduce delays in a critical path. In addition, delays may be hidden in a non-critical last round.
摘要翻译：可以通过提供单独的加密数据路径和解密数据路径来增加在通用处理器中执行加密和解密操作的速度。利用单独的数据路径，可以单独优化每个数据路径以减少关键路径中的延迟。此外，延迟可能隐藏在非关键的最后一轮。

58. 发明申请

US20080304659A1 METHOD AND APPARATUS FOR EXPANSION KEY GENERATION FOR BLOCK CIPHERS 有权
标题翻译：用于块式切片机的扩展关键生成的方法和装置
公开(公告)号：US20080304659A1
公开(公告)日：2008-12-11
申请号：US11760733
申请日：2007-06-08
申请人： Erdinc Ozturk , Kirk S. Yap , Gilbert Wolrich , Wajdi K. Feghali , Vinodh Gopal
发明人： Erdinc Ozturk , Kirk S. Yap , Gilbert Wolrich , Wajdi K. Feghali , Vinodh Gopal
IPC分类号： H04L9/28
CPC分类号： H04L9/0631 , G06F9/30007 , H04L2209/12 , H04L2209/24
摘要： A key scheduler performs a key-expansion to generate round keys for AES encryption and decryption just-in-time for each AES round. The key scheduler pre-computes slow operations in a current clock cycle to reduce the critical delay path for computing the round key for a next AES round.
摘要翻译：密钥调度程序执行密钥扩展，以便为每个AES轮次准时生成AES加密和解密的循环密钥。密钥调度器在当前时钟周期内预先计算慢速操作，以减少用于计算下一个AES循环的循环密钥的关键延迟路径。

59. 发明申请

US20140189290A1 INSTRUCTION FOR FAST ZUC ALGORITHM PROCESSING 有权
标题翻译：用于快速ZUC算法处理的指令
公开(公告)号：US20140189290A1
公开(公告)日：2014-07-03
申请号：US13730230
申请日：2012-12-28
申请人： Gilbert M. Wolrich , Vinodh Gopal , Kirk S. Yap , Wajdi K. Feghali
发明人： Gilbert M. Wolrich , Vinodh Gopal , Kirk S. Yap , Wajdi K. Feghali
IPC分类号： G06F15/76
CPC分类号： G06F9/3867 , G06F9/30007 , G06F9/30036 , G06F9/3005 , G06F9/30098 , G06F15/8007 , G09C1/00 , H04L9/0662 , H04L2209/125
摘要： Vector instructions for performing ZUC stream cipher operations are received and executed by the execution circuitry of a processor. The execution circuitry receives a first vector instruction to perform an update to a liner feedback shift register (LFSR), and receives a second vector instruction to perform an update to a state of a finite state machine (FSM), where the FSM receives inputs from re-ordered bits of the LFSR. The execution circuitry executes the first vector instruction and the second vector instruction in a single-instruction multiple data (SIMD) pipeline.
摘要翻译：用于执行ZUC流密码操作的矢量指令由处理器的执行电路接收和执行。执行电路接收第一向量指令以对线性反馈移位寄存器（LFSR）进行更新，并且接收第二向量指令以对有限状态机（FSM）的状态进行更新，其中FSM接收来自重新排列了LFSR的位。执行电路在单指令多数据（SIMD）流水线中执行第一向量指令和第二向量指令。

60. 发明授权

US08520845B2 Method and apparatus for expansion key generation for block ciphers 有权
标题翻译：用于块密码的扩展密钥生成的方法和装置
公开(公告)号：US08520845B2
公开(公告)日：2013-08-27
申请号：US11760733
申请日：2007-06-08
申请人： Erdinc Ozturk , Kirk S. Yap , Gilbert Wolrich , Wajdi K. Feghali , Vinodh Gopal
发明人： Erdinc Ozturk , Kirk S. Yap , Gilbert Wolrich , Wajdi K. Feghali , Vinodh Gopal
IPC分类号： H04L9/00
CPC分类号： H04L9/0631 , G06F9/30007 , H04L2209/12 , H04L2209/24
摘要： A key scheduler performs a key-expansion to generate round keys for AES encryption and decryption just-in-time for each AES round. The key scheduler pre-computes slow operations in a current clock cycle to reduce the critical delay path for computing the round key for a next AES round.
摘要翻译：密钥调度程序执行密钥扩展，以便为每个AES轮次准时生成AES加密和解密的循环密钥。密钥调度器在当前时钟周期内预先计算慢速操作，以减少用于计算下一个AES循环的循环密钥的关键延迟路径。

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