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51. 发明申请

US20170285960A1 HARDWARE APPARATUSES AND METHODS FOR MEMORY COMPRESSION AND DECOMPRESSION 审中-公开
公开(公告)号：US20170285960A1
公开(公告)日：2017-10-05
申请号：US15089456
申请日：2016-04-01
申请人： Kirk S. Yap , Vinodh Gopal , James D. Guilford , Sean M. Gulley
发明人： Kirk S. Yap , Vinodh Gopal , James D. Guilford , Sean M. Gulley
IPC分类号： G06F3/06
CPC分类号： G06F3/064 , G06F12/00 , H03M7/30 , H03M7/3084
摘要： Methods and apparatuses relating to memory compression and decompression are described. In one embodiment, a hardware compression engine is to determine when each section of a plurality of sections of a block of data is a zero value, a full match or a partial match to an entry in a dictionary, or a no match to any entry in the dictionary, encode a tag for each section to indicate the one of the zero value, the full match, the partial match, and the no match, encode a literal when the section is the no match, an index to the entry in the dictionary when the section is the full match, and an index to the entry in the dictionary and non-matching bits when the section is the partial match, and update an entry in the dictionary with a value of a section when the section is the no match.

52. 发明申请

US20170093424A1 Systems, Methods, and Apparatuses for Decompression using Hardware and Software 审中-公开
公开(公告)号：US20170093424A1
公开(公告)日：2017-03-30
申请号：US14866749
申请日：2015-09-25
申请人： Vinodh Gopal , James D. Guilford , Sean M. Gulley , Kirk S. Yap
发明人： Vinodh Gopal , James D. Guilford , Sean M. Gulley , Kirk S. Yap
IPC分类号： H03M7/30
CPC分类号： H03M7/3086 , H03M7/6005 , H03M7/6017
摘要： Detailed herein are embodiments of systems, methods, and apparatuses for decompression using hardware and software. In hardware, an input buffer stores incoming input records from a compressed stream. A plurality of decoders decode at least one input record from the input buffer out output an intermediate record from the decoded data and a subset of the plurality of decoders to output a stream of literals. Finally, a reformat circuit formats an intermediate record into one of two types of tokens.

53. 发明申请

US20140185793A1 INSTRUCTIONS PROCESSORS, METHODS, AND SYSTEMS TO PROCESS SECURE HASH ALGORITHMS 有权
标题翻译：指令处理器，方法和系统来处理安全的哈希算法
公开(公告)号：US20140185793A1
公开(公告)日：2014-07-03
申请号：US13729502
申请日：2012-12-28
申请人： GILBERT M. WOLRICH , Kirk S. Yap , Vinodh Gopal , James D. Guilford
发明人： GILBERT M. WOLRICH , Kirk S. Yap , Vinodh Gopal , James D. Guilford
IPC分类号： H04L9/28
CPC分类号： H04L9/0643 , G06F9/30007 , G06F9/30036 , G06F9/30101 , G06F9/30145 , G06F9/3016 , G06F21/602 , G06F21/64 , G06F21/72
摘要： A method of an aspect includes receiving an instruction. The instruction indicates a first source of a first packed data including state data elements ai, bi, ei, and fi for a current round (i) of a secure hash algorithm 2 (SHA2) hash algorithm. The instruction indicates a second source of a second packed data. The first packed data has a width in bits that is less than a combined width in bits of eight state data elements ai, bi, ci, di, ei, fi, gi, hi of the SHA2 hash algorithm. The method also includes storing a result in a destination indicated by the instruction in response to the instruction. The result includes updated state data elements ai+, bi+, ei+, and fi+ that have been updated from the corresponding state data elements ai, bi, ei, and fi by at least one round of the SHA2 hash algorithm.
摘要翻译：方面的方法包括接收指令。该指令指示包括安全散列算法2（SHA2）散列算法的当前轮（i）的状态数据元素ai，bi，ei和fi的第一打包数据的第一来源。该指令指示第二打包数据的第二来源。第一打包数据具有小于SHA2散列算法的八个状态数据元素ai，bi，ci，di，ei，fi，gi，hi的组合宽度的比特宽度。该方法还包括响应于指令将结果存储在由指令指示的目的地中。结果包括已经通过至少一轮的SHA2散列算法从相应的状态数据元素ai，bi，ei和fi更新的更新的状态数据元素ai +，bi +，ei +和fi +。

54. 发明授权

US09128698B2 Systems, apparatuses, and methods for performing rotate and XOR in response to a single instruction 有权
标题翻译：响应于单个指令执行旋转和异或的系统，设备和方法
公开(公告)号：US09128698B2
公开(公告)日：2015-09-08
申请号：US13631242
申请日：2012-09-28
申请人： Vinodh Gopal , Gilbert M. Wolrich , James D. Guilford , Kirk S. Yap
发明人： Vinodh Gopal , Gilbert M. Wolrich , James D. Guilford , Kirk S. Yap
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/30029 , G06F9/30032 , G06F9/30036 , G06F9/30167
摘要： Disclosed herein are systems, apparatuses, and methods performing in a computer processor of performing a rotate and XOR in response to a single XOR and rotate instruction, wherein the rotate and XOR instruction includes a first and second source operand, a destination operand, and an immediate value.
摘要翻译：这里公开的是在计算机处理器中执行的响应于单个XOR和旋转指令执行旋转和异或的系统，装置和方法，其中旋转和XOR指令包括第一和第二源操作数，目的地操作数和即时价值。

55. 发明申请

US20140189369A1 Instructions Processors, Methods, and Systems to Process Secure Hash Algorithms 有权
标题翻译：指令处理器，方法和系统来处理安全散列算法
公开(公告)号：US20140189369A1
公开(公告)日：2014-07-03
申请号：US13843141
申请日：2013-03-15
申请人： Gilbert M. Wolrich , Kirk S. Yap , Vinodh Gopal , James D. Guilford
发明人： Gilbert M. Wolrich , Kirk S. Yap , Vinodh Gopal , James D. Guilford
IPC分类号： G06F21/72
CPC分类号： H04L9/0643 , G06F9/30007 , G06F9/30036 , G06F9/30101 , G06F9/30145 , G06F9/3016 , G06F21/602 , G06F21/64 , G06F21/72
摘要： A method of an aspect includes receiving an instruction. The instruction indicates a first source of a first packed data including state data elements ai, bi, ei, and fi for a current round (i) of a secure hash algorithm 2 (SHA2) hash algorithm. The instruction indicates a second source of a second packed data. The first packed data has a width in bits that is less than a combined width in bits of eight state data elements ai, bi, ci, di, ei, fi, gi, hi of the SHA2 hash algorithm. The method also includes storing a result in a destination indicated by the instruction in response to the instruction. The result includes updated state data elements ai+, bi+, ei+, and fi+ that have been updated from the corresponding state data elements ai, bi, ei, and fi by at least one round of the SHA2 hash algorithm.
摘要翻译：方面的方法包括接收指令。该指令指示包括安全散列算法2（SHA2）散列算法的当前轮（i）的状态数据元素ai，bi，ei和fi的第一打包数据的第一来源。该指令指示第二打包数据的第二来源。第一打包数据具有小于SHA2散列算法的八个状态数据元素ai，bi，ci，di，ei，fi，gi，hi的组合宽度的比特宽度。该方法还包括响应于指令将结果存储在由指令指示的目的地中。结果包括已经通过至少一轮的SHA2散列算法从相应的状态数据元素ai，bi，ei和fi更新的更新的状态数据元素ai +，bi +，ei +和fi +。

56. 发明申请

US20140095844A1 Systems, Apparatuses, and Methods for Performing Rotate and XOR in Response to a Single Instruction 有权
标题翻译：用于对单个指令进行旋转和异或运算的系统，设备和方法
公开(公告)号：US20140095844A1
公开(公告)日：2014-04-03
申请号：US13631242
申请日：2012-09-28
申请人： Vinodh Gopal , Gilbert M. Wolrich , James D. Guilford , Kirk S. Yap
发明人： Vinodh Gopal , Gilbert M. Wolrich , James D. Guilford , Kirk S. Yap
IPC分类号： G06F9/30
CPC分类号： G06F9/30029 , G06F9/30032 , G06F9/30036 , G06F9/30167
摘要： Disclosed herein are systems, apparatuses, and methods performing in a computer processor of performing a rotate and XOR in response to a single XOR and rotate instruction, wherein the rotate and XOR instruction includes a first and second source operand, a destination operand, and an immediate value.
摘要翻译：这里公开的是在计算机处理器中执行的响应于单个XOR和旋转指令执行旋转和异或的系统，装置和方法，其中旋转和XOR指令包括第一和第二源操作数，目的操作数和即时价值。

57. 发明申请

US20140177823A1 METHODS, SYSTEMS AND APPARATUS TO REDUCE PROCESSOR DEMANDS DURING ENCRYPTION 有权
标题翻译：在加密过程中减少处理器数量的方法，系统和设备
公开(公告)号：US20140177823A1
公开(公告)日：2014-06-26
申请号：US13727141
申请日：2012-12-26
申请人： Vinodh Gopal , Erdinc Ozturk , James D. Guilford
发明人： Vinodh Gopal , Erdinc Ozturk , James D. Guilford
IPC分类号： H04L9/28
CPC分类号： H04L9/0637 , G06F9/00 , G06F9/30032 , G06F21/00 , H04L2209/12
摘要： Methods and apparatus are disclosed to reduce processor demands during encryption. A disclosed example method includes detecting a request for the processor to execute an encryption cipher determining whether the encryption cipher is associated with a byte reflection operation, preventing the byte reflection operation when a buffer associated with the encryption cipher will not cause a carryover condition, and incrementing the buffer via a shift operation before executing the encryption cipher.
摘要翻译：公开了减少加密期间处理器需求的方法和装置。所公开的示例方法包括：检测处理器执行确定加密密码是否与字节反射操作相关联的加密密码的请求，当与加密密码相关联的缓冲器不会导致携带条件时，防止字节反射操作;以及在执行加密密码之前通过移位操作递增缓冲区。

58. 发明申请

US20160085555A1 TECHNOLOGIES FOR EFFICIENT LZ77-BASED DATA DECOMPRESSION 有权
标题翻译：高效的基于LZ77的数据分解技术
公开(公告)号：US20160085555A1
公开(公告)日：2016-03-24
申请号：US14494766
申请日：2014-09-24
申请人： Vinodh Gopal , Sean M. Gulley , James D. Guilford
发明人： Vinodh Gopal , Sean M. Gulley , James D. Guilford
IPC分类号： G06F9/38 , G06F12/02 , G06F12/08 , H03M7/30
CPC分类号： H03M7/3086 , G06F3/0604 , G06F3/064 , G06F3/065 , G06F3/0673 , G06F9/3818 , G06F9/3863 , G06F12/023 , G06F12/0875 , G06F2212/1044 , G06F2212/452 , H03M7/3091 , H03M7/6005 , H03M7/6017
摘要： Technologies for data decompression include a computing device that reads a symbol tag byte from an input stream. The computing device determines whether the symbol can be decoded using a fast-path routine, and if not, executes a slow-path routine to decompress the symbol. The slow-path routine may include data-dependent branch instructions that may be unpredictable using branch prediction hardware. For the fast-path routine, the computing device determines a next symbol increment value, a literal increment value, a data length, and an offset based on the tag byte, without executing an unpredictable branch instruction. The computing device sets a source pointer to either literal data or reference data as a function of the tag byte, without executing an unpredictable branch instruction. The computing device may set the source pointer using a conditional move instruction. The computing device copies the data and processes remaining symbols. Other embodiments are described and claimed.
摘要翻译：用于数据解压缩的技术包括从输入流读取符号标记字节的计算设备。计算设备确定是否可以使用快速路径例程来解码符号，如果不是，则执行慢路径例程来解压缩符号。慢路径例程可以包括使用分支预测硬件可能不可预测的依赖于数据的分支指令。对于快速路径例程，计算设备基于标签字节确定下一个符号递增值，文字增量值，数据长度和偏移量，而不执行不可预测的分支指令。计算设备将源指针设置为文字数据或引用数据作为标记字节的函数，而不执行不可预测的分支指令。计算设备可以使用条件移动指令来设置源指针。计算设备复制数据并处理剩余符号。描述和要求保护其他实施例。

59. 发明授权

US09473168B1 Systems, methods, and apparatuses for compression using hardware and software 有权
标题翻译：使用硬件和软件进行压缩的系统，方法和装置
公开(公告)号：US09473168B1
公开(公告)日：2016-10-18
申请号：US14866746
申请日：2015-09-25
申请人： Vinodh Gopal , James D. Guilford , Gilbert M. Wolrich , Daniel F. Cutter
发明人： Vinodh Gopal , James D. Guilford , Gilbert M. Wolrich , Daniel F. Cutter
IPC分类号： H03M7/00 , H03M7/30
CPC分类号： H03M7/3082 , H03M7/3086 , H03M7/40
摘要： Detailed herein are embodiments of systems, methods, and apparatuses for compression using hardware and software. Embodiments include compressor hardware to operate on two streams with one of the streams being an offset of the other stream. Additionally, in some embodiments, the output of the compressor hardware is submitted to software for further processing.
摘要翻译：这里详细描述了使用硬件和软件进行压缩的系统，方法和装置的实施例。实施例包括在两个流之间操作的压缩器硬件，其中一个流是另一个流的偏移。另外，在一些实施例中，压缩机硬件的输出被提交给软件进行进一步的处理。

60. 发明授权

US08947270B2 Apparatus and method to accelerate compression and decompression operations 有权
标题翻译：加速压缩和减压操作的装置和方法
公开(公告)号：US08947270B2
公开(公告)日：2015-02-03
申请号：US13931877
申请日：2013-06-29
申请人： Vinodh Gopal , James D. Guilford , Gilbert M. Wolrich
发明人： Vinodh Gopal , James D. Guilford , Gilbert M. Wolrich
IPC分类号： H03M7/00 , G06F9/30
CPC分类号： H03M7/3086 , G06F9/30145 , G06F9/30178
摘要： A processor is described that includes an instruction execution pipeline having an instruction fetch unit to fetch and decode an instruction. The processor also has an execution unit to execute the instruction. The execution unit has a state machine and content addressable memory (CAM) circuitry. The state machine is to receive a pointer to a stream of DEFLATE encoded information, fetch a section of the DEFLATE encoded information and apply the section of the DEFLATE encoded information to the CAM to obtain decoded DEFLATE information.
摘要翻译：描述了一种处理器，其包括具有用于获取和解码指令的指令获取单元的指令执行流水线。处理器还具有执行指令的执行单元。执行单元具有状态机和内容可寻址存储器（CAM）电路。状态机将接收指向DEFLATE编码信息流的指针，获取DEFLATE编码信息的一部分，并将DEFLATE编码信息的部分应用于CAM以获得解码的DEFLATE信息。

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