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51. 发明授权

US06828638B2 Decoupling capacitors for thin gate oxides 有权
标题翻译：薄栅氧化物去耦电容器
公开(公告)号：US06828638B2
公开(公告)日：2004-12-07
申请号：US09469406
申请日：1999-12-22
申请人： Ali Keshavarzi , Vivek K. De , Tanay Karnik , Rajendran Nair
发明人： Ali Keshavarzi , Vivek K. De , Tanay Karnik , Rajendran Nair
IPC分类号： H01L2976
CPC分类号： H01L27/0805 , H01L29/94 , H01L2924/0002 , H01L2924/00
摘要： In some embodiments, the invention involves a die having a first conductor carrying a power supply voltage and a second conductor carrying a ground voltage. A semiconductor capacitor operating in depletion mode is coupled between the first and second conductors to provide decoupling capacitance between the first and second conductors, the semiconductor capacitor having a gate voltage. Various configurations may be used including: n+ gate poly and n+ source/drain regions in an n-body; p+ gate poly and n+ source/drain regions in an n-body; p+ gate poly and p+ source/drain regions in an n-body; p+ gate poly and p+ source/drain regions in a p-body; n+ gate poly and p+ source/drain regions in a p-body; n+ gate poly and n+ source/drain regions in a p-body. The power supply voltage may have a larger absolute value than does a flatband voltage.
摘要翻译：在一些实施例中，本发明涉及具有承载电源电压的第一导体和承载接地电压的第二导体的管芯。以耗尽模式工作的半导体电容器耦合在第一和第二导体之间，以在第一和第二导体之间提供去耦电容，半导体电容器具有栅极电压。可以使用各种构造，包括：n体中的n +栅极多晶硅和n +源极/漏极区域; p +栅极多晶硅和n +源极/漏极区域; p +栅极poly和p +源极/漏极区域在n体中; p体中的p +栅极多晶硅和p +源极/漏极区域; p体中的n +栅极多晶硅和p +源极/漏极区域; p体中的n +栅极多晶硅和n +源极/漏极区域。电源电压可能比平带电压具有更大的绝对值。

52. 发明授权

US06690239B2 High bandwidth, low power, single stage cascode transimpedance amplifier for short haul optical links 失效
标题翻译：用于短距离光链路的高带宽，低功耗，单级共源共栅跨阻放大器
公开(公告)号：US06690239B2
公开(公告)日：2004-02-10
申请号：US10342689
申请日：2003-01-14
申请人： Timothy M. Wilson , Tanay Karnik , Luiz M. Franca-Neto
发明人： Timothy M. Wilson , Tanay Karnik , Luiz M. Franca-Neto
IPC分类号： H03F308
CPC分类号： H03F3/082
摘要： A high bandwidth, single stage, low power cascode transimpedance amplifier for short haul optical links. In one embodiment, an input signal is fed into the source of a common-gate pMOSFET, the output signal is taken at the drain of the common-gate pMOSFET, and bias current is supplied by a pMOSFET and a nMOSFET biased in their triode regions.
摘要翻译：用于短距离光链路的高带宽，单级，低功率共源共栅跨阻放大器。在一个实施例中，输入信号被馈送到共栅极pMOSFET的源极中，输出信号在公共栅极pMOSFET的漏极处获取，并且偏置电流由偏置在其三极管区域中的pMOSFET和nMOSFET提供。

53. 发明授权

US06617890B1 Measuring power supply stability 有权
标题翻译：测量电源稳定性
公开(公告)号：US06617890B1
公开(公告)日：2003-09-09
申请号：US10104393
申请日：2002-03-22
申请人： Tsung-Hao Chen , Peter Hazucha , Atila Alvandpour , Tanay Karnik , Chung-Ping Chen
发明人： Tsung-Hao Chen , Peter Hazucha , Atila Alvandpour , Tanay Karnik , Chung-Ping Chen
IPC分类号： H03K5153
CPC分类号： G01R19/16538 , G06F1/28 , H03K5/08 , H03K5/153
摘要： A system for measuring the stability of a power signal from a power supply includes a threshold violation detector. The threshold violation detector includes a comparator and an indicator. The comparator has a power signal input, a threshold signal input, and a comparison result output, and is configured to compare the power signal on the power signal input with a threshold on the threshold signal input to present a comparison result signal on the comparison result output. The indicator has a threshold violation output and a comparison input that receives the comparison result signal from the comparator. The indicator presents a threshold violation signal on the threshold violation output when the comparison result signal indicates that the power signal has violated the threshold.
摘要翻译：用于测量来自电源的功率信号的稳定性的系统包括阈值违规检测器。阈值违规检测器包括比较器和指示器。比较器具有功率信号输入，阈值信号输入和比较结果输出，并且被配置为将功率信号输入上的功率信号与阈值信号输入上的阈值进行比较，以在比较结果上呈现比较结果信号输出。指示器具有阈值违反输出和比较输入，其从比较器接收比较结果信号。当比较结果信号指示电源信号已经违反阈值时，指示器在阈值违反输出上呈现阈值违反信号。

54. 发明授权

US06483363B1 Storage element with stock node capacitive load 失效
标题翻译：具有堆栈节点容量负载的存储元件
公开(公告)号：US06483363B1
公开(公告)日：2002-11-19
申请号：US09663749
申请日：2000-09-15
申请人： Tanay Karnik , Sriram R. Vangal , Venkat S. Veeramachaneni
发明人： Tanay Karnik , Sriram R. Vangal , Venkat S. Veeramachaneni
IPC分类号： H03K3356
CPC分类号： H03K3/356173 , H03K3/0375 , H03K3/356156
摘要： A storage element includes a forward inverter and a feedback inverter cross-coupled between a storage node and a feedback node. A capacitive load within the feedback inverter is coupled to the storage node when the storage element holds data and is not coupled to the storage node when the storage element is loading. The capacitive load reduces the storage element's susceptibility to soft errors when holding data, and does not appreciably slow the storage element when data is loading. The capacitive load is implemented using the gate capacitance of complementary transistors connected to stack nodes within the feedback inverter. A flip-flop includes cascaded latches, one or more of which have the internal capacitance.
摘要翻译：存储元件包括在存储节点和反馈节点之间交叉耦合的正向反相器和反馈反相器。当存储元件保持数据时，反馈逆变器内的电容性负载被耦合到存储节点，并且当存储元件被加载时，其不耦合到存储节点。容量负载降低了存储元件在保存数据时对软错误的敏感性，并且在数据加载时不会明显减慢存储元件。使用连接到反馈逆变器内的堆叠节点的互补晶体管的栅极电容来实现电容负载。触发器包括级联锁存器，其中一个或多个具有内部电容。

55. 发明授权

US06380781B1 Soft error rate tolerant latch 有权
标题翻译：软错误率容错锁存器
公开(公告)号：US06380781B1
公开(公告)日：2002-04-30
申请号：US09430977
申请日：1999-11-01
申请人： Tanay Karnik , Krishnamurthy Soumyanath , Shekhar Y. Borkar
发明人： Tanay Karnik , Krishnamurthy Soumyanath , Shekhar Y. Borkar
IPC分类号： H03K312
CPC分类号： G01R31/318525 , G01R31/31816
摘要： A latch having increased soft error rate tolerance includes cross-coupled inverters having transistors with varying sizes. Diffusion regions of transistors coupled to storage nodes are kept small to reduce the effect of charge accumulation resulting from particles bombarding the bulk of an integrated circuit die. Transistors having gates coupled to the storage nodes are increased in size to increase the capacitance on the storage nodes. The reduced size of diffusion regions and increased size of gates on storage nodes combine to reduce the effects of accumulated charge. Diffusion region area is further reduced by reducing the size of pass gates that load normal data and scan data. A large capacitor is coupled to a feedback node within the cross-coupled inverters to further reduce the effect of accumulated charge.
摘要翻译：具有增加的软错误率容限的锁存器包括具有不同尺寸的晶体管的交叉耦合反相器。耦合到存储节点的晶体管的扩散区域保持较小，以减少由颗粒轰击集成电路管芯的体积而产生的电荷累积的影响。具有耦合到存储节点的栅极的晶体管的尺寸增加以增加存储节点上的电容。扩散区尺寸减小，存储节点栅极尺寸增大，减少了累积电荷的影响。通过减小加载正常数据和扫描数据的通孔的大小进一步减小扩散区域面积。大电容器耦合到交叉耦合的反相器内的反馈节点，以进一步降低累积电荷的影响。

56. 发明申请

US20200091414A1 MAGNETOELECTRIC SPIN ORBIT LOGIC BASED FULL ADDER 审中-公开
公开(公告)号：US20200091414A1
公开(公告)日：2020-03-19
申请号：US16130912
申请日：2018-09-13
申请人： Huichu Liu , Sasikanth Manipatruni , Daniel Morris , Kaushik Vaidyanathan , Tanay Karnik , Ian Young
发明人： Huichu Liu , Sasikanth Manipatruni , Daniel Morris , Kaushik Vaidyanathan , Tanay Karnik , Ian Young
IPC分类号： H01L43/04 , H01L43/06 , H01L43/10 , G11C11/16 , G11C11/18
摘要： An apparatus is provided which comprises a full adder including magnetoelectric material and spin orbit material. In some embodiments, the adder includes: a 3-bit carry generation structure and a multi-bit sum generation structure coupled to the 3-bit carry generation structure. In some embodiments, the 3-bit carry generation structure includes at least three cells comprising magnetoelectric material and spin orbit material, wherein the 3-bit carry generation structure is to perform a minority logic operation on first, second, and third inputs to generate a carry output. In some embodiments, the multi-bit sum generation structure includes at least four cells comprising magnetoelectric material and spin orbit material, wherein the multi-bit sum generation structure is to perform a minority logic operation on the first, second, and third inputs and the carry output to generate a sum output.

57. 发明授权

US08710869B2 High-speed comparator with asymmetric frequency response 有权
标题翻译：具有不对称频率响应的高速比较器
公开(公告)号：US08710869B2
公开(公告)日：2014-04-29
申请号：US10422238
申请日：2003-04-23
申请人： Peter Hazucha , Tsung-Hao Chen , Tanay Karnik , Chung-Ping Chen
发明人： Peter Hazucha , Tsung-Hao Chen , Tanay Karnik , Chung-Ping Chen
IPC分类号： H03K5/22 , H03K5/24
CPC分类号： H03K5/2481 , H03F3/45183 , H03F2203/45544 , H03F2203/45646
摘要： A comparator to provide an output voltage indicative of comparing an input voltage with a reference voltage, where the comparator has an asymmetric frequency response. With an asymmetric frequency response, the bandwidth of the input voltage may be greater than the bandwidth of the reference voltage. A comparator includes a differential pair of transistors coupled to a current mirror and biased by a current source, where in one embodiment, a capacitor shunts the sources of the differential pair. In a second embodiment, a capacitor couples the input voltage port to the gates of the current mirror transistors. In a third embodiment, the comparator utilizes both capacitors of the first and second embodiments.
摘要翻译：比较器，用于提供指示将输入电压与参考电压进行比较的输出电压，其中比较器具有不对称的频率响应。对于非对称频率响应，输入电压的带宽可能大于参考电压的带宽。比较器包括耦合到电流镜并由电流源偏置的晶体管的差分对，其中在一个实施例中，电容器分流差分对的源极。在第二实施例中，电容器将输入电压端口耦合到电流镜晶体管的栅极。在第三实施例中，比较器利用了第一和第二实施例的两个电容器。

58. 发明授权

US08629667B2 Pulse width modulator with an adjustable waveform generator for controlling duty cycle of a pulse width modulated signal 有权
标题翻译：具有可调波形发生器的脉宽调制器，用于控制脉宽调制信号的占空比
公开(公告)号：US08629667B2
公开(公告)日：2014-01-14
申请号：US13405175
申请日：2012-02-24
申请人： Fabrice Paillet , Peter Hazucha , Gerhard Schrom , Tanay Karnik , Sung T. Moon , Donald S. Gardner
发明人： Fabrice Paillet , Peter Hazucha , Gerhard Schrom , Tanay Karnik , Sung T. Moon , Donald S. Gardner
IPC分类号： G05F1/575 , H03K4/06
CPC分类号： H03K7/08 , H02M3/156
摘要： Disclosed herein are pulse width modulator (PWM) solutions with comparators not relying on a variable reference to adjust duty cycle. In accordance with some embodiments, a pulse width modulator having a comparator with an applied adjustable waveform to generate a bit stream with a controllably adjustable duty cycle is provided.
摘要翻译：这里公开了脉冲宽度调制器（PWM）解决方案，其中比较器不依赖于可变参考来调整占空比。根据一些实施例，提供具有具有应用的可调波形的比较器以产生具有可控制可调整占空比的位流的脉宽调制器。

59. 发明申请

US20120194245A1 PULSE WIDTH MODULATOR 有权
标题翻译：脉冲宽度调制器
公开(公告)号：US20120194245A1
公开(公告)日：2012-08-02
申请号：US13405175
申请日：2012-02-24
申请人： Fabrice Paillet , Peter Hazucha , Gerhard Schrom , Tanay Karnik , Sung T. Moon , Donald S. Gardner
发明人： Fabrice Paillet , Peter Hazucha , Gerhard Schrom , Tanay Karnik , Sung T. Moon , Donald S. Gardner
IPC分类号： H03K3/017
CPC分类号： H03K7/08 , H02M3/156
摘要： Disclosed herein are pulse width modulator (PWM) solutions with comparators not relying on a variable reference to adjust duty cycle. In accordance with some embodiments, a pulse width modulator having a comparator with an applied adjustable waveform to generate a bit stream with a controllably adjustable duty cycle is provided.
摘要翻译：这里公开了脉冲宽度调制器（PWM）解决方案，其中比较器不依赖于可变参考来调整占空比。根据一些实施例，提供具有具有应用的可调波形的比较器以产生具有可控制可调整占空比的位流的脉宽调制器。

60. 发明申请

US20110317508A1 MEMORY WRITE OPERATION METHODS AND CIRCUITS 有权
标题翻译：存储器写操作方法和电路
公开(公告)号：US20110317508A1
公开(公告)日：2011-12-29
申请号：US12823642
申请日：2010-06-25
申请人： JAYDEEP P. KULKARNI , Muhammad M. Khellah , Bibiche M. Geuskens , Arijit Raychowdhury , Tanay Karnik , Vivek K. De
发明人： JAYDEEP P. KULKARNI , Muhammad M. Khellah , Bibiche M. Geuskens , Arijit Raychowdhury , Tanay Karnik , Vivek K. De
IPC分类号： G11C8/08
CPC分类号： G11C8/08 , G11C7/12 , G11C7/20 , G11C11/412 , G11C11/413
摘要： In some embodiments, write wordline boost may be obtained from wordline driver boost and/or from bit line access transistor boost.
摘要翻译：在一些实施例中，可以从字线驱动器升压和/或来自位线存取晶体管升压获得写入字线升压。

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