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51. 发明授权

US09142508B2 Single exposure in multi-damascene process 有权
标题翻译：在多镶嵌过程中单次曝光
公开(公告)号：US09142508B2
公开(公告)日：2015-09-22
申请号：US13170095
申请日：2011-06-27
申请人： Cyprian Uzoh , Vage Oganesian , Ilyas Mohammed , Craig Mitchell , Belgacem Haba
发明人： Cyprian Uzoh , Vage Oganesian , Ilyas Mohammed , Craig Mitchell , Belgacem Haba
IPC分类号： H01L23/52 , H01L23/528 , H01L23/532 , H01L21/768
CPC分类号： H01L21/76831 , H01L21/76807 , H01L21/76834 , H01L21/76852 , H01L21/76885 , H01L21/76897 , H01L23/5226 , H01L23/5283 , H01L23/53209 , H01L23/53238 , H01L23/53252 , H01L2221/1036 , H01L2924/0002 , H01L2924/00
摘要： Methods of fabricating a multi-layer semiconductor device such as a multi-layer damascene or inverted multi-layer damascene structure using only a single or reduced number of exposure steps. The method may include etching a precursor structure formed of materials with differential removal rates for a given removal condition. The method may include removing material from a multi-layer structure under different removal conditions. Further disclosed are multi-layer damascene structures having multiple cavities of different sizes. The cavities may have smooth inner wall surfaces. The layers of the structure may be in direct contact. The cavities may be filled with a conducting metal or an insulator. Multi-layer semiconductor devices using the methods and structures are further disclosed.
摘要翻译：仅使用单个或减少数量的曝光步骤来制造多层半导体器件的方法，例如多层镶嵌或倒置的多层镶嵌结构。该方法可以包括用于对于给定的去除条件蚀刻由具有差异去除速率的材料形成的前体结构。该方法可以包括在不同的去除条件下从多层结构去除材料。还公开了具有不同尺寸的多个空腔的多层镶嵌结构。空腔可以具有平滑的内壁表面。结构的层可以直接接触。空腔可以用导电金属或绝缘体填充。进一步公开了使用这些方法和结构的多层半导体器件。

52. 发明申请

US20120326313A1 SINGLE EXPOSURE IN MULTI-DAMASCENE PROCESS 有权
标题翻译：多元化过程中的单次接触
公开(公告)号：US20120326313A1
公开(公告)日：2012-12-27
申请号：US13170095
申请日：2011-06-27
申请人： Cyprian Uzoh , Vage Oganesian , Ilyas Mohammed , Craig Mitchell , Belgacem Haba
发明人： Cyprian Uzoh , Vage Oganesian , Ilyas Mohammed , Craig Mitchell , Belgacem Haba
IPC分类号： H01L23/52 , H01L21/768
CPC分类号： H01L21/76831 , H01L21/76807 , H01L21/76834 , H01L21/76852 , H01L21/76885 , H01L21/76897 , H01L23/5226 , H01L23/5283 , H01L23/53209 , H01L23/53238 , H01L23/53252 , H01L2221/1036 , H01L2924/0002 , H01L2924/00
摘要： Methods of fabricating a multi-layer semiconductor device such as a multi-layer damascene or inverted multi-layer damascene structure using only a single or reduced number of exposure steps. The method may include etching a precursor structure formed of materials with differential removal rates for a given removal condition. The method may include removing material from a multi-layer structure under different removal conditions. Further disclosed are multi-layer damascene structures having multiple cavities of different sizes. The cavities may have smooth inner wall surfaces. The layers of the structure may be in direct contact. The cavities may be filled with a conducting metal or an insulator. Multi-layer semiconductor devices using the methods and structures are further disclosed.
摘要翻译：仅使用单个或减少数量的曝光步骤来制造多层半导体器件的方法，例如多层镶嵌或倒置的多层镶嵌结构。该方法可以包括用于对于给定的去除条件蚀刻由具有差异去除速率的材料形成的前体结构。该方法可以包括在不同的去除条件下从多层结构去除材料。还公开了具有不同尺寸的多个空腔的多层镶嵌结构。空腔可以具有平滑的内壁表面。结构的层可以直接接触。空腔可以用导电金属或绝缘体填充。进一步公开了使用这些方法和结构的多层半导体器件。

53. 发明授权

US08476774B2 Off-chip VIAS in stacked chips 有权
标题翻译：芯片中的离散VIAS堆叠芯片
公开(公告)号：US08476774B2
公开(公告)日：2013-07-02
申请号：US13316890
申请日：2011-12-12
申请人： Belgacem Haba , Ilyas Mohammed , Vage Oganesian , David Ovrutsky , Laura Wills Mirkarimi
发明人： Belgacem Haba , Ilyas Mohammed , Vage Oganesian , David Ovrutsky , Laura Wills Mirkarimi
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/78 , H01L21/6835 , H01L23/5382 , H01L24/24 , H01L24/48 , H01L24/82 , H01L24/96 , H01L24/97 , H01L25/0657 , H01L25/50 , H01L2221/68377 , H01L2224/16225 , H01L2224/16227 , H01L2224/24145 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2224/9202 , H01L2224/97 , H01L2225/06506 , H01L2225/0651 , H01L2225/06517 , H01L2225/06524 , H01L2225/06541 , H01L2225/06551 , H01L2225/06582 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/15311 , H01L2224/82 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2924/00012
摘要： A microelectronic assembly includes first and second stacked microelectronic elements, each having spaced apart traces extending along a front face and beyond at least a first edge thereof. An insulating region can contact the edges of each microelectronic element and at least portions of the traces of each microelectronic element extending beyond the respective first edges. The insulating region can define first and second side surfaces adjacent the first and second edges of the microelectronic elements. A plurality of spaced apart openings can extend along a side surface of the microelectronic assembly. Electrical conductors connected with respective traces can have portions disposed in respective openings and extending along the respective openings. The electrical conductors may extend to pads or solder balls overlying a face of one of the microelectronic elements.
摘要翻译：微电子组件包括第一和第二堆叠的微电子元件，每个微电子元件具有沿前表面延伸并且至少其第一边缘延伸的间隔开的迹线。绝缘区域可以接触每个微电子元件的边缘，并且每个微电子元件的迹线的至少部分延伸超过相应的第一边缘。绝缘区域可以限定与微电子元件的第一和第二边缘相邻的第一和第二侧表面。多个间隔开的开口可以沿着微电子组件的侧表面延伸。与相应迹线连接的电导体可以具有设置在相应开口中并沿相应开口延伸的部分。电导体可以延伸到覆盖在微电子元件中的一个的表面上的焊盘或焊球。

54. 发明申请

US20110049696A1 OFF-CHIP VIAS IN STACKED CHIPS 有权
标题翻译：堆叠式切片中的切割六边形
公开(公告)号：US20110049696A1
公开(公告)日：2011-03-03
申请号：US12941392
申请日：2010-11-08
申请人： Belgacem Haba , Ilyas Mohammed , Vage Oganesian , David Ovrutsky , Laura Wills Mirkarimi
发明人： Belgacem Haba , Ilyas Mohammed , Vage Oganesian , David Ovrutsky , Laura Wills Mirkarimi
IPC分类号： H01L25/11
CPC分类号： H01L21/78 , H01L21/6835 , H01L23/5382 , H01L24/24 , H01L24/48 , H01L24/82 , H01L24/96 , H01L24/97 , H01L25/0657 , H01L25/50 , H01L2221/68377 , H01L2224/16225 , H01L2224/16227 , H01L2224/24145 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2224/9202 , H01L2224/97 , H01L2225/06506 , H01L2225/0651 , H01L2225/06517 , H01L2225/06524 , H01L2225/06541 , H01L2225/06551 , H01L2225/06582 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/15311 , H01L2224/82 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2924/00012
摘要： A microelectronic assembly includes first and second stacked microelectronic elements, each having spaced apart traces extending along a front face and beyond at least a first edge thereof. An insulating region can contact the edges of each microelectronic element and at least portions of the traces of each microelectronic element extending beyond the respective first edges. The insulating region can define first and second side surfaces adjacent the first and second edges of the microelectronic elements. A plurality of spaced apart openings can extend along a side surface of the microelectronic assembly. Electrical conductors connected with respective traces can have portions disposed in respective openings and extending along the respective openings. The electrical conductors may extend to pads or solder balls overlying a face of one of the microelectronic elements.
摘要翻译：微电子组件包括第一和第二堆叠的微电子元件，每个微电子元件具有沿前表面延伸并且至少其第一边缘延伸的间隔开的迹线。绝缘区域可以接触每个微电子元件的边缘，并且每个微电子元件的迹线的至少部分延伸超过相应的第一边缘。绝缘区域可以限定与微电子元件的第一和第二边缘相邻的第一和第二侧表面。多个间隔开的开口可以沿着微电子组件的侧表面延伸。与相应迹线连接的电导体可以具有设置在相应开口中并沿相应开口延伸的部分。电导体可以延伸到覆盖在微电子元件中的一个的表面上的焊盘或焊球。

55. 发明授权

US08076788B2 Off-chip vias in stacked chips 有权
标题翻译：堆叠芯片中的片外通孔
公开(公告)号：US08076788B2
公开(公告)日：2011-12-13
申请号：US12941392
申请日：2010-11-08
申请人： Belgacem Haba , Ilyas Mohammed , Vage Oganesian , David Ovrutsky , Laura Mirkarimi
发明人： Belgacem Haba , Ilyas Mohammed , Vage Oganesian , David Ovrutsky , Laura Mirkarimi
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/78 , H01L21/6835 , H01L23/5382 , H01L24/24 , H01L24/48 , H01L24/82 , H01L24/96 , H01L24/97 , H01L25/0657 , H01L25/50 , H01L2221/68377 , H01L2224/16225 , H01L2224/16227 , H01L2224/24145 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2224/9202 , H01L2224/97 , H01L2225/06506 , H01L2225/0651 , H01L2225/06517 , H01L2225/06524 , H01L2225/06541 , H01L2225/06551 , H01L2225/06582 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/15311 , H01L2224/82 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2924/00012
摘要： A microelectronic assembly includes first and second stacked microelectronic elements, each having spaced apart traces extending along a front face and beyond at least a first edge thereof. An insulating region can contact the edges of each microelectronic element and at least portions of the traces of each microelectronic element extending beyond the respective first edges. The insulating region can define first and second side surfaces adjacent the first and second edges of the microelectronic elements. A plurality of spaced apart openings can extend along a side surface of the microelectronic assembly. Electrical conductors connected with respective traces can have portions disposed in respective openings and extending along the respective openings. The electrical conductors may extend to pads or solder balls overlying a face of one of the microelectronic elements.
摘要翻译：微电子组件包括第一和第二堆叠的微电子元件，每个微电子元件具有沿前表面延伸并且至少其第一边缘延伸的间隔开的迹线。绝缘区域可以接触每个微电子元件的边缘，并且每个微电子元件的迹线的至少部分延伸超过相应的第一边缘。绝缘区域可以限定与微电子元件的第一和第二边缘相邻的第一和第二侧表面。多个间隔开的开口可以沿着微电子组件的侧表面延伸。与相应迹线连接的电导体可以具有设置在相应开口中并沿相应开口延伸的部分。电导体可以延伸到覆盖在微电子元件中的一个的表面上的焊盘或焊球。

56. 发明授权

US07901989B2 Reconstituted wafer level stacking 有权
标题翻译：重构晶圆级堆叠
公开(公告)号：US07901989B2
公开(公告)日：2011-03-08
申请号：US12143743
申请日：2008-06-20
申请人： Belgacem Haba , Ilyas Mohammed , Vage Oganesian , David Ovrutsky , Laura Wills Mirkarimi
发明人： Belgacem Haba , Ilyas Mohammed , Vage Oganesian , David Ovrutsky , Laura Wills Mirkarimi
IPC分类号： H01L21/00
CPC分类号： H01L21/78 , H01L21/6835 , H01L23/5382 , H01L24/24 , H01L24/48 , H01L24/82 , H01L24/96 , H01L24/97 , H01L25/0657 , H01L25/50 , H01L2221/68377 , H01L2224/16225 , H01L2224/16227 , H01L2224/24145 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2224/9202 , H01L2224/97 , H01L2225/06506 , H01L2225/0651 , H01L2225/06517 , H01L2225/06524 , H01L2225/06541 , H01L2225/06551 , H01L2225/06582 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/15311 , H01L2224/82 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2924/00012
摘要： A stacked microelectronic assembly is fabricated from a structure which includes a plurality of first microelectronic elements having front faces bonded to a carrier. Each first microelectronic element may have a first edge and a plurality of first traces extending along the front face towards the first edge. After exposing at least a portion of the first traces, a dielectric layer is formed over the plurality of first microelectronic elements. After thinning the dielectric layer, a plurality of second microelectronic elements are aligned and joined with the structure such that front faces of the second microelectronic elements are facing the rear faces of the plurality of first microelectronic elements. Processing is repeated to form the desirable number of layers of microelectronic elements. In one embodiment, the stacked layers of microelectronic elements may be notched at dicing lines to expose edges of traces, which may then be electrically connected to leads formed in the notches. Individual stacked microelectronic units may be separated from the stacked microelectronic assembly by any suitable dicing, sawing or breaking technique.
摘要翻译：堆叠的微电子组件由包括多个第一微电子元件的结构制成，所述第一微电子元件具有接合到载体的前表面。每个第一微电子元件可以具有第一边缘和沿前表面朝向第一边缘延伸的多个第一迹线。在暴露至少一部分第一迹线之后，在多个第一微电子元件上形成介电层。在使介电层变薄之后，多个第二微电子元件与该结构对准并接合，使得第二微电子元件的正面面对多个第一微电子元件的后表面。重复处理以形成所需数量的微电子元件层。在一个实施例中，微电子元件的堆叠层可以在切割线处切口以暴露迹线的边缘，其可以然后电连接到形成在凹口中的引线。可以通过任何合适的切割，锯切或断裂技术将单个堆叠的微电子单元与堆叠的微电子组件分开。

57. 发明申请

US20120267777A1 MULTI-CHIP MODULE WITH STACKED FACE-DOWN CONNECTED DIES 有权
标题翻译：多芯片模块与堆叠式倒装连接芯片
公开(公告)号：US20120267777A1
公开(公告)日：2012-10-25
申请号：US13092376
申请日：2011-04-22
申请人： Belgacem Haba , Ilyas Mohammed , Piyush Savalia
发明人： Belgacem Haba , Ilyas Mohammed , Piyush Savalia
IPC分类号： H01L23/498 , H01L21/50 , H01L23/48
CPC分类号： H01L25/18 , H01L23/02 , H01L23/13 , H01L23/367 , H01L23/3675 , H01L23/49827 , H01L23/5386 , H01L24/16 , H01L24/17 , H01L24/32 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/0652 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/04042 , H01L2224/131 , H01L2224/13147 , H01L2224/16225 , H01L2224/16227 , H01L2224/16235 , H01L2224/32145 , H01L2224/32245 , H01L2224/33181 , H01L2224/48106 , H01L2224/48227 , H01L2224/48235 , H01L2224/48465 , H01L2224/73203 , H01L2224/73215 , H01L2224/73253 , H01L2224/73257 , H01L2224/73265 , H01L2225/0651 , H01L2225/06517 , H01L2225/06558 , H01L2225/06589 , H01L2924/00014 , H01L2924/01029 , H01L2924/01322 , H01L2924/07811 , H01L2924/09701 , H01L2924/1431 , H01L2924/1434 , H01L2924/15159 , H01L2924/15174 , H01L2924/15184 , H01L2924/15192 , H01L2924/15311 , H01L2924/18161 , H01L2924/20645 , H05K3/303 , H05K2201/10159 , H01L2924/00012 , H01L2924/014 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A microelectronic assembly can include a substrate having first and second surfaces, at least two logic chips overlying the first surface, and a memory chip having a front surface with contacts thereon, the front surface of the memory chip confronting a rear surface of each logic chip. The substrate can have conductive structure thereon and terminals exposed at the second surface for connection with a component. Signal contacts of each logic chip can be directly electrically connected to signal contacts of the other logic chips through the conductive structure of the substrate for transfer of signals between the logic chips. The logic chips can be adapted to simultaneously execute a set of instructions of a given thread of a process. The contacts of the memory chip can be directly electrically connected to the signal contacts of at least one of the logic chips through the conductive structure of the substrate.
摘要翻译：微电子组件可以包括具有第一和第二表面的衬底，覆盖在第一表面上的至少两个逻辑芯片，以及存储器芯片，其具有在其上的触点的前表面，存储芯片的前表面面对每个逻辑芯片的后表面。衬底可以具有导电结构，并且端子在第二表面处暴露以与部件连接。每个逻辑芯片的信号触点可以通过衬底的导电结构直接电连接到其他逻辑芯片的信号触点，用于在逻辑芯片之间传输信号。逻辑芯片可以适于同时执行一个给定的进程线程的一组指令。存储器芯片的触点可以通过衬底的导电结构直接电连接到至少一个逻辑芯片的信号触点。

58. 发明申请

US20120080807A1 OFF-CHIP VIAS IN STACKED CHIPS 有权
标题翻译：堆叠式切片中的切割六边形
公开(公告)号：US20120080807A1
公开(公告)日：2012-04-05
申请号：US13316890
申请日：2011-12-12
申请人： Belgacem Haba , Ilyas Mohammed , Vage Oganesian , David Ovrutsky , Laura Wills Mirkarimi
发明人： Belgacem Haba , Ilyas Mohammed , Vage Oganesian , David Ovrutsky , Laura Wills Mirkarimi
IPC分类号： H01L23/538
CPC分类号： H01L21/78 , H01L21/6835 , H01L23/5382 , H01L24/24 , H01L24/48 , H01L24/82 , H01L24/96 , H01L24/97 , H01L25/0657 , H01L25/50 , H01L2221/68377 , H01L2224/16225 , H01L2224/16227 , H01L2224/24145 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2224/9202 , H01L2224/97 , H01L2225/06506 , H01L2225/0651 , H01L2225/06517 , H01L2225/06524 , H01L2225/06541 , H01L2225/06551 , H01L2225/06582 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/15311 , H01L2224/82 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2924/00012
摘要： A microelectronic assembly includes first and second stacked microelectronic elements, each having spaced apart traces extending along a front face and beyond at least a first edge thereof. An insulating region can contact the edges of each microelectronic element and at least portions of the traces of each microelectronic element extending beyond the respective first edges. The insulating region can define first and second side surfaces adjacent the first and second edges of the microelectronic elements. A plurality of spaced apart openings can extend along a side surface of the microelectronic assembly. Electrical conductors connected with respective traces can have portions disposed in respective openings and extending along the respective openings. The electrical conductors may extend to pads or solder balls overlying a face of one of the microelectronic elements.
摘要翻译：微电子组件包括第一和第二堆叠的微电子元件，每个微电子元件具有沿前表面延伸并且至少其第一边缘延伸的间隔开的迹线。绝缘区域可以接触每个微电子元件的边缘，并且每个微电子元件的迹线的至少部分延伸超过相应的第一边缘。绝缘区域可以限定与微电子元件的第一和第二边缘相邻的第一和第二侧表面。多个间隔开的开口可以沿着微电子组件的侧表面延伸。与相应迹线连接的电导体可以具有设置在相应开口中并沿相应开口延伸的部分。电导体可以延伸到覆盖在微电子元件中的一个的表面上的焊盘或焊球。

59. 发明授权

US08841765B2 Multi-chip module with stacked face-down connected dies 有权
标题翻译：具有堆叠面朝下连接的模具的多芯片模块
公开(公告)号：US08841765B2
公开(公告)日：2014-09-23
申请号：US13092376
申请日：2011-04-22
申请人： Belgacem Haba , Ilyas Mohammed , Piyush Savalia
发明人： Belgacem Haba , Ilyas Mohammed , Piyush Savalia
IPC分类号： H01L23/34
CPC分类号： H01L25/18 , H01L23/02 , H01L23/13 , H01L23/367 , H01L23/3675 , H01L23/49827 , H01L23/5386 , H01L24/16 , H01L24/17 , H01L24/32 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/0652 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/04042 , H01L2224/131 , H01L2224/13147 , H01L2224/16225 , H01L2224/16227 , H01L2224/16235 , H01L2224/32145 , H01L2224/32245 , H01L2224/33181 , H01L2224/48106 , H01L2224/48227 , H01L2224/48235 , H01L2224/48465 , H01L2224/73203 , H01L2224/73215 , H01L2224/73253 , H01L2224/73257 , H01L2224/73265 , H01L2225/0651 , H01L2225/06517 , H01L2225/06558 , H01L2225/06589 , H01L2924/00014 , H01L2924/01029 , H01L2924/01322 , H01L2924/07811 , H01L2924/09701 , H01L2924/1431 , H01L2924/1434 , H01L2924/15159 , H01L2924/15174 , H01L2924/15184 , H01L2924/15192 , H01L2924/15311 , H01L2924/18161 , H01L2924/20645 , H05K3/303 , H05K2201/10159 , H01L2924/00012 , H01L2924/014 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A microelectronic assembly can include a substrate having first and second surfaces, at least two logic chips overlying the first surface, and a memory chip having a front surface with contacts thereon, the front surface of the memory chip confronting a rear surface of each logic chip. The substrate can have conductive structure thereon and terminals exposed at the second surface for connection with a component. Signal contacts of each logic chip can be directly electrically connected to signal contacts of the other logic chips through the conductive structure of the substrate for transfer of signals between the logic chips. The logic chips can be adapted to simultaneously execute a set of instructions of a given thread of a process. The contacts of the memory chip can be directly electrically connected to the signal contacts of at least one of the logic chips through the conductive structure of the substrate.
摘要翻译：微电子组件可以包括具有第一表面和第二表面的衬底，覆盖在第一表面上的至少两个逻辑芯片，以及存储芯片，其具有在其上的触点的前表面，存储芯片的前表面面对每个逻辑芯片的后表面。衬底可以具有导电结构，并且端子在第二表面处暴露以与部件连接。每个逻辑芯片的信号触点可以通过衬底的导电结构直接电连接到其他逻辑芯片的信号触点，用于在逻辑芯片之间传输信号。逻辑芯片可以适于同时执行一个给定的进程线程的一组指令。存储器芯片的触点可以通过衬底的导电结构直接电连接到至少一个逻辑芯片的信号触点。

60. 发明授权

US08975751B2 Vias in porous substrates 有权
标题翻译：多孔基材中的通孔
公开(公告)号：US08975751B2
公开(公告)日：2015-03-10
申请号：US13092495
申请日：2011-04-22
申请人： Ilyas Mohammed , Belgacem Haba , Cyprian Uzoh , Piyush Savalia
发明人： Ilyas Mohammed , Belgacem Haba , Cyprian Uzoh , Piyush Savalia
IPC分类号： H01L23/52 , H01L21/768 , H01L21/48 , H01L23/14 , H01L23/15 , H01L23/48 , H01L23/498
CPC分类号： H01L21/76877 , H01L21/486 , H01L21/76837 , H01L21/76898 , H01L23/147 , H01L23/15 , H01L23/481 , H01L23/49827 , H01L2924/0002 , H01L2924/09701 , H01L2924/00
摘要： A microelectronic unit can include a substrate having front and rear surfaces and active semiconductor devices therein, the substrate having a plurality of openings arranged in a symmetric or asymmetric distribution across an area of the rear surface, first and second conductive vias connected to first and second pads exposed at the front surface, pluralities of first and second conductive interconnects extending within respective ones of the openings, and first and second conductive contacts exposed for interconnection with an external element. The plurality of first conductive interconnects can be separated from the plurality of second conductive interconnects by at least one of the plurality of openings, the at least one opening at least partially filled with an insulating material. The distribution of the openings can include at least m openings spaced apart in a first direction and n openings spaced apart in a second direction transverse to the first direction.
摘要翻译：微电子单元可以包括其中具有前表面和后表面的基板和其中的有源半导体器件，所述基板具有布置成在后表面的区域上的对称或不对称分布的多个开口，连接到第一和第二导电通孔的第一和第二导电通孔在前表面暴露的焊盘，在相应的一个开口内延伸的多个第一和第二导电互连，以及暴露以与外部元件互连的第一和第二导电触点。多个第一导电互连可以通过所述多个开口中的至少一个与所述多个第二导电互连部分开，所述至少一个开口至少部分地填充有绝缘材料。开口的分布可以包括在第一方向上间隔开的至少m个开口和在横向于第一方向的第二方向上间隔开的n个开口。

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