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51. 发明授权

US5627104A Method to improve interlevel dielectric planarization using SOG 失效
标题翻译：使用SOG改善层间电介质平坦化的方法
公开(公告)号：US5627104A
公开(公告)日：1997-05-06
申请号：US221071
申请日：1994-03-31
申请人： Frank R. Bryant , Charles R. Spinner, III
发明人： Frank R. Bryant , Charles R. Spinner, III
IPC分类号： H01L21/3105 , H01L21/768 , H01L21/44 , H01L21/48
CPC分类号： H01L21/31053 , H01L21/31051 , H01L21/76819
摘要： A method is provided for forming a substantially planarized surface of an integrated circuit, and an integrated circuit formed according to the same. A conductive area is formed over a portion of a dielectric region. A first spin-on-glass layer is formed over the conductive area and exposed dielectric region. A second spin-on-glass layer is formed over the first spin-on-glass layer; wherein the second spin-on-glass layer has a slower etch rate than the first spin-on-glass layer. A partial etchback of the first and second spin-on-glass layers is performed forming a substantially planar surface.
摘要翻译：提供一种用于形成集成电路的基本上平坦化的表面的方法，以及根据该集成电路形成的集成电路。在电介质区域的一部分上形成导电区域。在导电区域和暴露的电介质区域上形成第一旋涂玻璃层。在第一旋涂玻璃层上形成第二旋涂玻璃层; 其中所述第二旋涂玻璃层具有比所述第一旋涂玻璃层更慢的蚀刻速率。执行第一和第二旋涂玻璃层的部分回蚀，形成基本平坦的表面。

52. 发明授权

US5423939A Method for forming contact plugs in integrated circuits 失效
标题翻译：在集成电路中形成接触塞的方法
公开(公告)号：US5423939A
公开(公告)日：1995-06-13
申请号：US110486
申请日：1993-08-23
申请人： Frank R. Bryant , Loi N. Nguyen
发明人： Frank R. Bryant , Loi N. Nguyen
IPC分类号： H01L21/28 , H01L21/768 , B44C1/22
CPC分类号： H01L21/76877 , H01L21/7684
摘要： According to the present invention, a method is provided for forming contact vias in an integrated circuit. Initially, a first protective layer is formed on an insulating layer, and an opening is created through the insulating layer where a contact is to be made. A conductive layer is deposited over the protective layer and partially fills the opening, forming a conductive plug in the opening. A second protective layer is then formed over the conductive plug. Portions of the conductive layer which were formed over the first protective layer are removed. During removal of those portions of the conductive layer, the second protective layer protects the conductive plug from damage. The first and second protective layers are then removed, leaving the conductive plug in the opening in the insulating layer. A conductive contact can now be made by depositing a second conductive layer over the conductive plug.
摘要翻译：根据本发明，提供了一种在集成电路中形成接触孔的方法。首先，在绝缘层上形成第一保护层，并且通过要进行接触的绝缘层形成开口。导电层沉积在保护层上并部分地填充开口，在开口中形成导电塞。然后在导电插塞上形成第二保护层。在第一保护层上形成的导电层的部分被去除。在去除导电层的那些部分期间，第二保护层保护导电插头免受损坏。然后去除第一和第二保护层，将导电塞留在绝缘层中的开口中。现在可以通过在导电插塞上沉积第二导电层来进行导电接触。

53. 发明授权

US5420453A Intermediate structure for forming isolated regions of oxide 失效
标题翻译：用于形成氧化物隔离区的中间结构
公开(公告)号：US5420453A
公开(公告)日：1995-05-30
申请号：US304608
申请日：1994-09-12
申请人： Robert L. Hodges , Frank R. Bryant , Fusen E. Chen
发明人： Robert L. Hodges , Frank R. Bryant , Fusen E. Chen
IPC分类号： H01L21/76 , H01L21/316 , H01L21/32 , H01L21/762 , H01L27/12
CPC分类号： H01L21/76202 , H01L21/32
摘要： A method is provided for forming isolated regions of oxide of an integrated circuit, and an integrated circuit formed according to the same. A pad oxide layer is formed over a portion of a substrate. A first silicon nitride layer is formed over the pad oxide layer. A polysilicon buffer layer is then formed over the first silicon nitride layer. A second silicon nitride layer is formed over the polysilicon layer. A photoresist layer is formed and patterned over the second silicon nitride layer. An opening is etched through the second silicon nitride layer and the polysilicon buffer layer to expose a portion of the first silicon nitride layer. A third silicon nitride region is then formed on at least the polysilicon buffer layer exposed in the opening. The first silicon nitride layer is etched in the opening. A field oxide region is then formed in the opening.
摘要翻译：提供一种用于形成集成电路的隔离氧化物区域的方法和根据该集成电路形成的集成电路。在衬底的一部分上形成衬垫氧化物层。在衬垫氧化物层上形成第一氮化硅层。然后在第一氮化硅层上形成多晶硅缓冲层。在多晶硅层上形成第二氮化硅层。在第二氮化硅层上形成并图案化光致抗蚀剂层。通过第二氮化硅层和多晶硅缓冲层蚀刻开口以暴露第一氮化硅层的一部分。至少在开口中暴露的多晶硅缓冲层上形成第三氮化硅区域。在开口中蚀刻第一氮化硅层。然后在开口中形成场氧化物区域。

54. 发明授权

US5416034A Method of making resistor with silicon-rich silicide contacts for an integrated circuit 失效
标题翻译：制造具有富集硅化物触点的电阻器用于集成电路的方法
公开(公告)号：US5416034A
公开(公告)日：1995-05-16
申请号：US85973
申请日：1993-06-30
申请人： Frank R. Bryant
发明人： Frank R. Bryant
IPC分类号： H01L21/02 , H01L21/20 , H01L21/8244 , H01L27/11 , H01L21/28
CPC分类号： H01L28/24 , H01L27/11 , H01L27/1112 , H01L21/2022 , Y10S257/904
摘要： A method for fabricating a high impedance load device in an integrated circuit. An opening in an insulating layer is formed to expose a first region below the insulating layer. A region of a refractory metal silicide is formed in the opening. Then, the integrated circuit is annealed until a layer of epitaxial silicon from the refractory metal silicide is deposited on the region, wherein the layer of epitaxial silicon separates the first region from the refractory metal silicide.
摘要翻译：一种用于在集成电路中制造高阻抗负载装置的方法。形成绝缘层的开口以露出绝缘层下面的第一区域。在开口中形成难熔金属硅化物的区域。然后，将集成电路退火直到来自难熔金属硅化物的外延硅层沉积在该区域上，其中外延硅层将第一区域与难熔金属硅化物分开。

55. 发明授权

US5403777A Semiconductor bond pad structure and method 失效
标题翻译：半导体焊盘结构及方法
公开(公告)号：US5403777A
公开(公告)日：1995-04-04
申请号：US182845
申请日：1994-01-14
申请人： Frank R. Bryant , Fusen E. Chen
发明人： Frank R. Bryant , Fusen E. Chen
IPC分类号： H01L21/60 , H01L23/485 , H01L21/00 , H01L21/44
CPC分类号： H01L24/05 , H01L24/03 , H01L24/48 , H01L2224/0347 , H01L2224/04042 , H01L2224/05082 , H01L2224/05187 , H01L2224/05556 , H01L2224/05558 , H01L2224/05599 , H01L2224/05624 , H01L2224/05666 , H01L2224/05684 , H01L2224/48463 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/04941 , H01L2924/14
摘要： A method for forming an improved bonding pad structure. A bond pad structure is formed by depositing a barrier layer over an underlying region of a semiconductor device, and then depositing a first conductive layer over the barrier layer. The barrier layer and conductive layer are then patterned and etched to define a conductive region. In a preferred embodiment, the conductive region is formed in the shape of a grid. A second conductive layer is deposited over the conductive region and a portion of the exposed underlying region. The second conductive layer makes a good adhesive contact with the underlying region, thus preventing bond pad lift off.
摘要翻译：一种形成改进的焊盘结构的方法。通过在半导体器件的下面的区域上沉积阻挡层，然后在阻挡层上沉积第一导电层，形成接合焊盘结构。然后对阻挡层和导电层进行图案化和蚀刻以限定导电区域。在优选实施例中，导电区域形成为网格形状。第二导电层沉积在导电区域和暴露的下部区域的一部分上。第二导电层与下面的区域形成良好的粘合剂接触，从而防止粘结垫剥离。

56. 发明授权

US5233135A Interconnect for integrated circuits 失效
标题翻译：集成电路互连
公开(公告)号：US5233135A
公开(公告)日：1993-08-03
申请号：US722702
申请日：1991-06-28
申请人： Fusen E. Chen , Frank R. Bryant , Girish A. Dixit
发明人： Fusen E. Chen , Frank R. Bryant , Girish A. Dixit
IPC分类号： H01L21/3205 , H01L21/768 , H01L23/522 , H01L23/532
CPC分类号： H01L21/76877 , H01L21/76816 , H01L21/76829 , H01L23/53214 , H01L2924/0002
摘要： A technique for forming metal interconnect signal lines provides for planarization of an interlevel dielectric layer. A thin layer of material which can function as an etch stop, such as a metal oxide, is formed over the interlevel dielectric. An alignment process is used to pattern and define openings through the etch stop layer where contacts to underlying conductive regions will be formed. Another insulating layer is formed over the etch stop layer, and patterned to define all interconnect signal lines. When the signal line locations are etched away, the etching process stops on the etch stop layer in regions where the signal lines will be, and continues through to the underlying conductive layer where contacts are needed. A metal refill process can be used to then form interconnects and contacts within the etched holes, followed by an anisotropic etchback to remove any metal which lies on top of the upper insulating layer. This results in interconnect and contacts having upper surfaces which are substantially coplanar with the upper insulating layer in which they are formed.

57. 发明授权

US5065225A Tunneling diffusion barrier for local interconnect and polysilicon high impedance device 失效
标题翻译：用于局部互连和多晶硅高阻抗器件的隧道扩散势垒
公开(公告)号：US5065225A
公开(公告)日：1991-11-12
申请号：US560384
申请日：1990-07-31
申请人： Frank R. Bryant , John L. Walters
发明人： Frank R. Bryant , John L. Walters
IPC分类号： H01L23/532
CPC分类号： H01L23/5329 , H01L23/53271 , H01L2924/0002 , H01L2924/3011
摘要： A semiconductor device is described in which a conductive layer overlaps a dielectric layer forming a composite electrical device deposited over selected portions of a semiconductor substrate chemically isolating the conductive layer portion of the composite electrical device from the substrate, thereby preventing difffusion of dopant material through the dielectric layer into and out of the conductive layer while simultaneously allowing for tunneling of electrons through the dielectric layer to and from the conductive layer and the semiconductor substrate.
摘要翻译：描述了一种半导体器件，其中导电层与形成复合电器件的电介质层重叠，沉积在半导体衬底的选定部分上，从而将复合电器件的导电层部分与衬底化学隔离，从而防止掺杂剂材料通过介电层进出导电层，同时允许电子穿过电介质层穿过导电层和半导体衬底穿过电介质层。

58. 发明授权

US07543917B2 Integrated circuit and method for manufacturing 有权
标题翻译：集成电路及制造方法
公开(公告)号：US07543917B2
公开(公告)日：2009-06-09
申请号：US11540321
申请日：2006-09-29
申请人： Simon Dodd , S. Jonathan Wang , Dennis W. Tom , Frank R. Bryant , Terry E. McMahon , Richard Todd Miller , Gregory T. Hindman
发明人： Simon Dodd , S. Jonathan Wang , Dennis W. Tom , Frank R. Bryant , Terry E. McMahon , Richard Todd Miller , Gregory T. Hindman
IPC分类号： B41J2/05
CPC分类号： B41J2/1628 , B41J2/14129 , B41J2/1603 , B41J2202/13 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a semiconductor device, the method including forming a substrate including a first surface having a non-doped region, forming an insulative material over the first surface of the substrate, forming a first conductive material over the first insulative material, forming an opening in the first conductive material that forms a path to the substrate that is substantially free of the first conductive material and the first insulative material, forming a second insulative material over the first conductive material, and forming a second conductive material over the second insulative material, wherein the second conductive material is formed in the opening and contacts the non-doped region of the substrate.
摘要翻译：一种形成半导体器件的方法，所述方法包括形成包括具有非掺杂区域的第一表面的衬底，在所述衬底的第一表面上形成绝缘材料，在所述第一绝缘材料上形成第一导电材料，形成第在所述第一导电材料中开口，所述第一导电材料形成基本上不含所述第一导电材料和所述第一绝缘材料的路径，在所述第一导电材料上形成第二绝缘材料，以及在所述第二绝缘材料上形成第二导电材料，其中所述第二导电材料形成在所述开口中并接触所述衬底的非掺杂区域。

59. 发明授权

US07056795B2 Thin-film transistor used as heating element for microreaction chamber 有权
公开(公告)号：US07056795B2
公开(公告)日：2006-06-06
申请号：US11028985
申请日：2005-01-03
申请人： Frank R. Bryant
发明人： Frank R. Bryant
IPC分类号： H01L21/336
CPC分类号： H01L29/78696 , B01J19/0093 , B01J2219/00783 , B01J2219/00828 , B01J2219/00853 , B01J2219/00873 , B01L3/5027 , B41J2/14129 , F24V99/00 , G01N25/4826 , G01N2035/00376 , H01L29/66765 , H01L29/78624 , H05B3/26 , H05B2203/013 , H05B2203/017
摘要： The thin film transistor formed of polycrystalline silicon is positioned adjacent a heat reaction chamber. The gate electrode for the transistor is formed within a silicon substrate and a gate dielectric is positioned over the gate electrode. A pass transistor is coupled to the gate electrode, the pass transistor having a source/drain region in the same semiconductor substrate and positioned adjacent to the gate electrode of the thin film heating transistor. When the pass transistor is enabled, a voltage is applied to the gate electrode which causes the current to flow from the drain to the source of the thin film transistor. The current flow passes through a highly resistive region which generates heat that is transmitted to the heat reaction chamber.

60. 发明授权

US06977185B2 Printhead integrated circuit 有权
标题翻译：打印头集成电路
公开(公告)号：US06977185B2
公开(公告)日：2005-12-20
申请号：US10214081
申请日：2002-08-06
申请人： Frank R. Bryant , Joseph M. Torgerson , Angela White Bakkom
发明人： Frank R. Bryant , Joseph M. Torgerson , Angela White Bakkom
IPC分类号： B41J2/05 , B41J2/14 , B41J2/16 , B41J2/175 , H01L21/00
CPC分类号： B41J2/17556 , B41J2/14016 , B41J2/1601 , B41J2/1628 , B41J2/1629 , B41J2/1631 , B41J2/1646 , B41J2202/13
摘要： An integrated circuit is formed on a substrate. The integrated circuit includes a transistor formed in the substrate. The transistor has a gate that forms at least one closed-loop. The integrated circuit also includes an ejection element that is coupled to the transistor wherein the ejection element is disposed over the substrate without an intervening field oxide layer.
摘要翻译：在基板上形成集成电路。集成电路包括形成在衬底中的晶体管。晶体管具有形成至少一个闭环的栅极。集成电路还包括耦合到晶体管的喷射元件，其中喷射元件设置在衬底上，而没有中间场氧化物层。

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