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51. 发明授权

US6108264A Dynamic type semiconductor memory device 失效
标题翻译：动态型半导体存储器件
公开(公告)号：US6108264A
公开(公告)日：2000-08-22
申请号：US234101
申请日：1999-01-19
申请人： Yasushi Takahashi , Takashi Shinoda , Masamichi Ishihara , Tetsu Udagawa , Kazumasa Yanagisawa
发明人： Yasushi Takahashi , Takashi Shinoda , Masamichi Ishihara , Tetsu Udagawa , Kazumasa Yanagisawa
IPC分类号： G11C7/00 , G11C7/06 , G11C11/406
CPC分类号： G11C7/06 , G11C11/406
摘要： An ordinary read/write operation (normal operation) and a refresh operation are separated from one another and the number of read amplification circuits or, in other words, the number of sense amplifiers operating during the normal operation is made smaller than that during the refresh operation. Accordingly, a bit line charge/discharge current during the normal operation can be reduced.
摘要翻译：普通的读/写操作（正常操作）和刷新操作彼此分离，并且读取的放大电路的数量，或者换句话说，使得在正常操作期间操作的读出放大器的数量小于刷新期间的读出放大器的数量操作。因此，可以减少正常工作期间的位线充电/放电电流。

52. 发明授权

US5869888A Semiconductor device with lead structure on principal surface of chip 失效
标题翻译：芯片主表面具有导线结构的半导体器件
公开(公告)号：US5869888A
公开(公告)日：1999-02-09
申请号：US721339
申请日：1996-09-26
申请人： Kunihiro Tsubosaki , Michio Tanimoto , Kunihiko Nishi , Masahiro Ichitani , Shunji Koike , Kazunari Suzuki , Ryosuke Kimoto , Ichiro Anjoh , Taisei Jin , Akihiko Iwaya , Gen Murakami , Masamichi Ishihara , Junichi Arita
发明人： Kunihiro Tsubosaki , Michio Tanimoto , Kunihiko Nishi , Masahiro Ichitani , Shunji Koike , Kazunari Suzuki , Ryosuke Kimoto , Ichiro Anjoh , Taisei Jin , Akihiko Iwaya , Gen Murakami , Masamichi Ishihara , Junichi Arita
IPC分类号： H01L23/31 , H01L23/495 , H01L25/10 , H01L23/48
CPC分类号： H01L24/06 , H01L23/3107 , H01L23/3121 , H01L23/4951 , H01L24/05 , H01L24/49 , H01L25/105 , H01L2224/0401 , H01L2224/04042 , H01L2224/05554 , H01L2224/05624 , H01L2224/06136 , H01L2224/32245 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48253 , H01L2224/4826 , H01L2224/48465 , H01L2224/48624 , H01L2224/48724 , H01L2224/49113 , H01L2224/49171 , H01L2224/73215 , H01L2224/85424 , H01L2225/1029 , H01L24/45 , H01L24/48 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01023 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/07802 , H01L2924/1305 , H01L2924/181 , H01L2924/351 , Y10T29/49121
摘要： A semiconductor device having inner leads secured via insulating adhesive films to the principal surface of a semiconductor chip and electrically connected to the respective external terminals of the semiconductor chip. The semiconductor device that can be about the size of the chip is so configured that an outer lead is continuously extended from each inner lead up to the rear surface opposite to the principal surface of the semiconductor chip in order to hold the leads and an external device in conduction.
摘要翻译：一种半导体器件，其具有通过绝缘粘合剂膜固定到半导体芯片的主表面并与半导体芯片的各个外部端子电连接的内部引线。可以关于芯片尺寸的半导体器件被配置为使得外引线从每个内引线连续地延伸到与半导体芯片的主表面相对的后表面，以便保持引线和外部器件导通。

53. 发明授权

US5701031A Sealed stacked arrangement of semiconductor devices 失效
标题翻译：密封堆叠布置的半导体器件
公开(公告)号：US5701031A
公开(公告)日：1997-12-23
申请号：US280381
申请日：1994-07-25
申请人： Satoshi Oguchi , Masamichi Ishihara , Kazuya Ito , Gen Murakami , Ichiro Anjoh , Toshiyuki Sakuta , Yasunori Yamaguchi , Yasuhiro Kasama , Tetsu Udagawa , Eiji Miyamoto , Youichi Matsuno , Hiroshi Satoh , Atsusi Nozoe
发明人： Satoshi Oguchi , Masamichi Ishihara , Kazuya Ito , Gen Murakami , Ichiro Anjoh , Toshiyuki Sakuta , Yasunori Yamaguchi , Yasuhiro Kasama , Tetsu Udagawa , Eiji Miyamoto , Youichi Matsuno , Hiroshi Satoh , Atsusi Nozoe
IPC分类号： G11C5/00 , H01L23/495 , H01L25/065 , H01L23/28 , H01L23/535 , H01L23/538
CPC分类号： H01L24/06 , G11C5/00 , G11C5/02 , G11C5/06 , H01L23/4951 , H01L23/49537 , H01L23/49575 , H01L25/0652 , H01L2224/0401 , H01L2224/04042 , H01L2224/05554 , H01L2224/06136 , H01L2224/32245 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/4554 , H01L2224/4569 , H01L2224/48091 , H01L2224/48137 , H01L2224/48247 , H01L2224/4826 , H01L2224/49171 , H01L2224/49175 , H01L2224/73215 , H01L2224/73265 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01043 , H01L2924/01047 , H01L2924/01055 , H01L2924/01073 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181
摘要： A pair of DRAM chips 1A and 1B are mounted opposedly to each other with wiring means such as lead frames put therebetween, the lead frames being substantially integral with external terminals 3B. Then, these DRAM chips and lead frames are connected together by the conventional wire bonding method. Plural pairs of the thus-connected DRAM chips and lead frames are stacked and corresponding leads of the lead frames are connected in common to form a laminate. The plural DRAM chips thus mounted are activated selectively in accordance with a predetermined chip selection signal. Additionally, partial DRAM chips capable of partially functioning normally are combined together by utilizing the above chip mounting method to constitute a single DRAM package.
摘要翻译：一对DRAM芯片1A和1B通过诸如引线框架之间的布线装置彼此相对地安装，引线框架与外部端子3B基本上成一体。然后，这些DRAM芯片和引线框架通过常规的引线键合方法连接在一起。堆叠这样连接的DRAM芯片和引线框架的多对，并且引线框架的相应引线共同连接以形成层叠体。这样安装的多个DRAM芯片根据预定的芯片选择信号选择性地被激活。此外，通过利用上述芯片安装方法，能够正常部分正常工作的部分DRAM芯片组合在一起，以构成单个DRAM封装。

54. 发明授权

US5663863A Line arrester 失效
标题翻译：线路避雷器
公开(公告)号：US5663863A
公开(公告)日：1997-09-02
申请号：US550998
申请日：1995-10-31
申请人： Takashi Ohashi , Tatsumi Ichioka , Masamichi Ishihara , Toshiyuki Takagi
发明人： Takashi Ohashi , Tatsumi Ichioka , Masamichi Ishihara , Toshiyuki Takagi
IPC分类号： H01T4/14 , H02H1/00
CPC分类号： H01T4/14
摘要： An improved line arrester is disclosed that includes a non-linear resistor. The arrester includes a pair of arcing horns are respectively provided on an earth side and a line side of the arrester, with an aerial discharge gap being provided therebetween. The aerial discharge gap is in electrical parallel with the resistor. The length of the aerial discharge gap is selected such that flashover does not occur in response to currents smaller than a rated discharge current of the resistor, yet flashover does occur in response to a current that is greater than the rated discharge current, but lower than a critical discharge current of the resistor. With this arrangement the resistor is protected against the lightning surge current greater than the critical discharge current.
摘要翻译：公开了一种改进的线路避雷器，其包括非线性电阻器。避雷器包括一对电弧喇叭，分别设置在避雷器的地侧和线路侧，在它们之间设有空中放电间隙。天线放电间隙与电阻并联。天线放电间隙的长度被选择为使得响应于小于电阻器的额定放电电流的电流而不发生闪络，但是响应于大于额定放电电流的电流而发生闪络，但是低于电阻的临界放电电流。通过这种布置，电阻器可以防止雷电浪涌电流大于临界放电电流。

55. 发明授权

US5546261A Superconducting fault current limiter 失效
标题翻译：超导故障限流器
公开(公告)号：US5546261A
公开(公告)日：1996-08-13
申请号：US218809
申请日：1994-03-28
申请人： Shinji Yoshida , Shuichiro Motoyama , Takashi Ohashi , Masamichi Ishihara
发明人： Shinji Yoshida , Shuichiro Motoyama , Takashi Ohashi , Masamichi Ishihara
IPC分类号： H01F6/06 , H02H9/02
CPC分类号： H02H9/023 , H01F6/06 , H01F2006/001 , Y02E40/69 , Y10S505/85 , Y10S505/872
摘要： A superconducting fault current limiter composed of an induction coil wound around a core made of a soft magnetic material such as soft iron, ferrite or the like, a cylindrical superconductive body arranged in surrounding relationship with the induction coil and a cooling container formed to contain only the superconductive body therein and filled with cooling liquid such as liquid nitrogen or helium to immerse therein the superconductive body.
摘要翻译：一种由感应线圈组成的超导故障限流器，该感应线圈缠绕在由软铁，铁素体等软磁性材料制成的芯部上，与感应线圈相关联设置的圆柱形超导体和仅形成为仅包含的冷却容器其中的超导体填充有诸如液氮或氦的冷却液体以将超导体浸入其中。

56. 发明授权

US5021998A Semiconductor memory device with low-house pads for electron beam test 失效
标题翻译：半导体存储器件，具有用于电子束测试的低屋垫
公开(公告)号：US5021998A
公开(公告)日：1991-06-04
申请号：US339843
申请日：1989-04-18
申请人： Yukihide Suzuki , Masaya Muranaka , Masamichi Ishihara
发明人： Yukihide Suzuki , Masaya Muranaka , Masamichi Ishihara
IPC分类号： G11C29/00 , G11C29/50 , H01L21/66 , H01L21/8242 , H01L27/10 , H01L27/108
CPC分类号： H01L27/10808
摘要： Disclosed are measurement (observation) pads for judging whether or not a dynamic random access memory (DRAM) adopting a shared sense system is functioning as designed. Concretely, measurement pads are formed by the step of forming a second layer of wiring respectively connected to pairs of complementary data lines which are formed by the step of forming a first layer of wiring, and the signal waveforms of the pairs of complementary data lines are measured using the measurement pads. Further, the measurement pads are provided between wiring layers which become fixed potentials in, at least, the operation of measuring data. In addition, each of the measurement pads is used in common by data lines which are respectively connected to two memory cells located in different memory cell mats.
摘要翻译：公开了用于判断采用共享感测系统的动态随机存取存储器（DRAM）是否如此设计的功能的测量（观察）焊盘。具体地，通过形成分别连接到形成第一层布线的步骤形成的互补数据线对的第二层布线的步骤形成测量焊盘，并且互补数据线对的信号波形是使用测量垫测量。此外，至少在测量数据的操作中，测量焊盘设置在成为固定电位的布线层之间。此外，每个测量焊盘由分别连接到位于不同存储单元垫中的两个存储单元的数据线共同使用。

57. 发明授权

US4951122A Resin-encapsulated semiconductor device 失效
标题翻译：树脂封装的半导体器件
公开(公告)号：US4951122A
公开(公告)日：1990-08-21
申请号：US199538
申请日：1988-05-27
申请人： Kunihiro Tsubosaki , Gen Murakami , Toshiyuki Sakuta , Masamichi Ishihara , Satoru Ito , Yasuo Mori
发明人： Kunihiro Tsubosaki , Gen Murakami , Toshiyuki Sakuta , Masamichi Ishihara , Satoru Ito , Yasuo Mori
IPC分类号： H01L23/31 , H01L23/495 , H01L23/498
CPC分类号： H01L24/32 , H01L23/3135 , H01L23/49506 , H01L23/4951 , H01L23/49541 , H01L23/49558 , H01L23/49861 , H01L2224/05554 , H01L2224/32014 , H01L2224/32245 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48247 , H01L2224/48257 , H01L2224/48465 , H01L2224/49175 , H01L2224/73265 , H01L2224/8592 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01047 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/10253 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/1815 , H01L2924/3011 , H01L2924/351
摘要： The present invention relates to a technique in which the pellet fixing parts of a lead frame of the tabless type or the type having no die pads are molded in or coated with a resin beforehand in order to enhance the reliability of a resin-encapsulated IC having become important with enlargement in the size of the chip of a memory IC or the like and reduction in the size of a resin package, and a resin package structure in which the technique of the lead frame having no die pads is applied to flat packaging so as to lessen reflow cracks.
摘要翻译：本发明涉及一种技术，其中预先将无凸型引线框架或不具有模片焊盘的引线框架的芯片固定部件预先模制或涂覆树脂，以提高具有树脂封装的IC的可靠性随着存储器IC等的芯片的尺寸的增大和树脂封装的尺寸的减小而变得重要，并且将没有管芯焊盘的引线框架的技术应用于平面封装的树脂封装结构，因此以减少回流裂纹。

58. 发明授权

US4928281A Semiconductor memory 失效
标题翻译：半导体存储器
公开(公告)号：US4928281A
公开(公告)日：1990-05-22
申请号：US60331
申请日：1987-06-10
申请人： Hinoko Kurosawa , Kazuya Itoh , Hisashi Nakamura , Masamichi Ishihara
发明人： Hinoko Kurosawa , Kazuya Itoh , Hisashi Nakamura , Masamichi Ishihara
IPC分类号： G11C29/00 , G06F11/10 , G11C29/42
CPC分类号： G06F11/1032
摘要： A semiconductor memory includes a memory array which outputs storage data, at least one data unit at a time, each data unit having a plurality of bits including a parity bit, a parity check circuit for performing a parity check on storage data, at least one data unit at a time, input for both to and output from the memory array, and an external terminal for outputting the result of the parity check.
摘要翻译：半导体存储器包括：存储器阵列，其输出存储数据;一次至少一个数据单元，每个数据单元具有包括奇偶校验位的多个位，用于对存储数据执行奇偶校验的奇偶校验电路，至少一个数据单元，用于从存储器阵列输入和输出的外部端子，以及用于输出奇偶校验结果的外部端子。

59. 发明授权

US4922993A Method of forming a zinc sleeve on an insulator pin 失效
标题翻译：在绝缘体销上形成锌套管的方法
公开(公告)号：US4922993A
公开(公告)日：1990-05-08
申请号：US301126
申请日：1989-01-25
申请人： Hiroto Matsuo , Iwaji Kawamoto , Masamichi Ishihara , Takaaki Nakagawa
发明人： Hiroto Matsuo , Iwaji Kawamoto , Masamichi Ishihara , Takaaki Nakagawa
IPC分类号： H01B17/02 , B22D19/00 , C23C6/00 , H01B17/06 , H01B19/00
CPC分类号： B22D19/00 , C23C6/00
摘要： The disclosed method forms a zinc sleeve on an insulator pin by dipping the insulator pin in molten zinc at about 450.degree.-650.degree. C. to heat and wet the insulator pin with the molten zinc, setting the hot and wetted insulator pin in a die having an open-top cavity in such a manner that an annular open-top molding cavity is defined around the insulator, the die being at about 50.degree.-300.degree. C. when receiving the insulator pin, pouring molten zinc in the annular molding cavity through its open top, and solidifying the zinc thus poured.
摘要翻译：所公开的方法通过将绝缘体销浸入熔融锌中约450℃-650℃，从而在绝缘体销上形成锌套管，用熔融锌对绝缘体引脚进行加热和湿润，将热和湿的绝缘体销设置在模具中具有开口空腔，使得围绕绝缘体限定环形开口模制腔，当接纳绝缘体销时，模具处于约50-300℃，将熔融锌浇注到环形模腔中通过其开口顶部，并固化锌浇注。

60. 发明授权

US4912679A Memory including address registers 失效
标题翻译：存储器包括地址寄存器
公开(公告)号：US4912679A
公开(公告)日：1990-03-27
申请号：US144066
申请日：1988-01-15
申请人： Takashi Shinoda , Masamichi Ishihara
发明人： Takashi Shinoda , Masamichi Ishihara
IPC分类号： G11C11/41 , G11C8/06
CPC分类号： G11C8/06
摘要： A microprocessor or the like supplies a plurality of address signals for memory access according to its own operation speed irrespective of the operation speed of a memory. A plurality of registers receives and stores the plurality of address signals which are inputted in an asynchronous state. The memory access is performed according to a sequence signals of the address signals stored in the plurality of registers.
摘要翻译：无论存储器的操作速度如何，微处理器等都根据其自身的操作速度提供用于存储器访问的多个地址信号。多个寄存器接收并存储以异步状态输入的多个地址信号。存储器访问根据存储在多个寄存器中的地址信号的序列信号进行。

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