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51. 发明授权

US06940152B2 Semiconductor storage device and its manufacturing method 有权
标题翻译：半导体存储装置及其制造方法
公开(公告)号：US06940152B2
公开(公告)日：2005-09-06
申请号：US10473573
申请日：2003-02-05
申请人： Masatoshi Arai
发明人： Masatoshi Arai
IPC分类号： H01L21/8246 , H01L21/8247 , H01L27/105 , H01L23/58
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11543
摘要： A plurality of impurity diffusion layers working as bit lines are formed in surface portions of a semiconductor substrate, and a plurality of buried insulating films are formed above the plural impurity diffusion layers on the semiconductor substrate. Gate electrodes of memory devices include a plurality of first polysilicon films, which are formed between the buried insulating films with a trapping film formed below and have top faces at substantially the same level as top faces of the buried insulating films, and a second polysilicon film formed over the plural buried insulating films and the plural first polysilicon films for electrically connecting the plural first polysilicon films to one another.
摘要翻译：在半导体衬底的表面部分形成多个作为位线工作的杂质扩散层，并且在半导体衬底上的多个杂质扩散层的上方形成多个掩埋绝缘膜。存储器件的栅电极包括多个第一多晶硅膜，它们形成在具有下面形成的捕获膜的掩埋绝缘膜之间，并且具有与掩埋绝缘膜的顶面基本相同的顶面，以及第二多晶硅膜形成在多个埋入绝缘膜上，以及多个第一多晶硅膜，用于将多个第一多晶硅膜彼此电连接。

52. 发明申请

US20050156220A1 Semiconductor device and method of manufacturing the same 审中-公开
公开(公告)号：US20050156220A1
公开(公告)日：2005-07-21
申请号：US11081679
申请日：2005-03-17
申请人： Mizuki Segawa , Isao Miyanaga , Toshiki Yabu , Takashi Nakabayashi , Takashi Uehara , Kyoji Yamashita , Takaaki Ukeda , Masatoshi Arai , Takayuki Yamada , Michikazu Matsumoto
发明人： Mizuki Segawa , Isao Miyanaga , Toshiki Yabu , Takashi Nakabayashi , Takashi Uehara , Kyoji Yamashita , Takaaki Ukeda , Masatoshi Arai , Takayuki Yamada , Michikazu Matsumoto
IPC分类号： H01L21/336 , H01L21/762 , H01L27/108 , H01L21/8242
CPC分类号： H01L29/6659 , H01L21/76224 , H01L29/665 , H01L2924/0002 , H01L2924/00
摘要： An isolation which is higher in a stepwise manner than an active area of a silicon substrate is formed. On the active area, an FET including a gate oxide film, a gate electrode, a gate protection film, sidewalls and the like is formed. An insulating film is deposited on the entire top surface of the substrate, and a resist film for exposing an area stretching over the active area, a part of the isolation and the gate protection film is formed on the insulating film. There is no need to provide an alignment margin for avoiding interference with the isolation and the like to a region where a connection hole is formed. Since the isolation is higher in a stepwise manner than the active area, the isolation is prevented from being removed by over-etch in the formation of a connection hole to come in contact with a portion where an impurity concentration is low in the active area. In this manner, the integration of a semiconductor device can be improved and an area occupied by the semiconductor device can be decreased without causing degradation of junction voltage resistance and increase of a junction leakage current in the semiconductor device.

53. 发明授权

US06847119B2 Semiconductor device and method of manufacturing the same 有权
公开(公告)号：US06847119B2
公开(公告)日：2005-01-25
申请号：US10454682
申请日：2003-06-05
申请人： Mizuki Segawa , Isao Miyanaga , Toshiki Yabu , Takashi Nakabayashi , Takashi Uehara , Kyoji Yamashita , Takaaki Ukeda , Masatoshi Arai , Takayuki Yamada , Michikazu Matsumoto
发明人： Mizuki Segawa , Isao Miyanaga , Toshiki Yabu , Takashi Nakabayashi , Takashi Uehara , Kyoji Yamashita , Takaaki Ukeda , Masatoshi Arai , Takayuki Yamada , Michikazu Matsumoto
摘要： An isolation which is higher in a stepwise manner than an active area of a silicon substrate is formed. On the active area, an FET including a gate oxide film, a gate electrode, a gate protection film, sidewalls and the like is formed. An insulating film is deposited on the entire top surface of the substrate, and a resist film for exposing an area stretching over the active area, a part of the isolation and the gate protection film is formed on the insulating film. There is no need to provide an alignment margin for avoiding interference with the isolation and the like to a region where a connection hole is formed. Since the isolation is higher in a stepwise manner than the active area, the isolation is prevented from being removed by over-etch in the formation of a connection hole to come in contact with a portion where an impurity concentration is low in the active area. In this manner, the integration of a semiconductor device can be improved and an area occupied by the semiconductor device can be decreased without causing degradation of junction voltage resistance and increase of a junction leakage current in the semiconductor device.

54. 发明授权

US06709950B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06709950B2
公开(公告)日：2004-03-23
申请号：US09902157
申请日：2001-07-11
申请人： Mizuki Segawa , Isao Miyanaga , Toshiki Yabu , Takashi Nakabayashi , Takashi Uehara , Kyoji Yamashita , Takaaki Ukeda , Masatoshi Arai , Takayuki Yamada , Michikazu Matsumoto
发明人： Mizuki Segawa , Isao Miyanaga , Toshiki Yabu , Takashi Nakabayashi , Takashi Uehara , Kyoji Yamashita , Takaaki Ukeda , Masatoshi Arai , Takayuki Yamada , Michikazu Matsumoto
IPC分类号： H01L29167
CPC分类号： H01L29/6659 , H01L21/76224 , H01L29/665 , H01L2924/0002 , H01L2924/00
摘要： An isolation which is higher in a stepwise manner than an active area of a silicon substrate is formed. On the active area, an FET including a gate oxide film, a gate electrode, a gate protection film, sidewalls and the like is formed. An insulating film is deposited on the entire top surface of the substrate, and a resist film for exposing an area stretching over the active area, a part of the isolation and the gate protection film is formed on the insulating film. There is no need to provide an alignment margin for avoiding interference with the isolation and the like to a region where a connection hole is formed. Since the isolation is higher in a stepwise manner than the active area, the isolation is prevented from being removed by over-etch in the formation of a connection hole to come in contact with a portion where an impurity concentration is low in the active area. In this manner, the integration of a semiconductor device can be improved and an area occupied by the semiconductor device can be decreased without causing degradation of junction voltage resistance and increase of a junction leakage current in the semiconductor device.
摘要翻译：形成了比硅衬底的有源区域更高级的隔离。在有源区域上，形成包括栅极氧化膜，栅电极，栅极保护膜，侧壁等的FET。绝缘膜沉积在基板的整个顶表面上，并且在绝缘膜上形成用于暴露在有源区上延伸的区域，一部分隔离栅极保护膜的抗蚀剂膜。不需要提供用于避免与形成连接孔的区域的隔离等的干涉的取向余量。由于隔离比有源区域以逐步方式更高，所以通过在形成连接孔中的过度蚀刻来防止隔离物与有源区域中杂质浓度低的部分接触。以这种方式，可以改善半导体器件的集成，并且可以降低半导体器件占据的面积，而不会导致半导体器件中的结电阻的劣化和结漏电流的增加。

55. 发明授权

US06597368B1 Morphing image processing system using polygon reduction processing 失效
标题翻译：变形图像处理系统采用多边形缩小处理
公开(公告)号：US06597368B1
公开(公告)日：2003-07-22
申请号：US09626108
申请日：2000-07-26
申请人： Masatoshi Arai , Yoshinori Aoyama
发明人： Masatoshi Arai , Yoshinori Aoyama
IPC分类号： G09G500
CPC分类号： G06T13/20 , G06T2210/44
摘要： A first image before deformation and a second image after deformation are input and formed into polygon models represented with a polygon mesh by a polygon model generation processing part. Polygon reduction processing is performed by a low progression level polygon model generation processing part to generate low progression level polygon models having a reduced number of polygons and metadata containing the reduction process of the number of polygons. A low progression level polygon model morphing processing part specifies corresponding vertices between the low progression level polygon models, and then they are formed into intermediate low progression level polygon models by interpolation. Intermediate images are generated by reproducing processing to the polygon model using the metadata by an intermediate image generation processing part and texture mapping.
摘要翻译：变形前的第一图像和变形后的第二图像通过多边形模型生成处理部分输入并形成由多边形网格表示的多边形模型。通过低级进程级多边形模型生成处理部分执行多边形缩减处理，以生成具有减少的多边形数量的低进度级多边形模型和包含多边形数量的缩减处理的元数据。低级进程级多边形模型变形处理部分指定低级进程级多边形模型之间的对应顶点，然后通过插值形成中间低级进程级多边形模型。通过使用中间图像生成处理部分的元数据和纹理映射将处理再现到多边形模型来生成中间图像。

56. 发明授权

US06597047B2 Method for fabricating a nonvolatile semiconductor device 失效
标题翻译：非易失性半导体器件的制造方法
公开(公告)号：US06597047B2
公开(公告)日：2003-07-22
申请号：US09813305
申请日：2001-03-21
申请人： Masatoshi Arai , Takahiko Hashidzume
发明人： Masatoshi Arai , Takahiko Hashidzume
IPC分类号： H01L2976
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11524
摘要： A silicon dioxide film, located over an active region in a well, is annealed at 1050° C. within an N2O ambient, thereby diffusing nitrogen into the silicon dioxide film and forming a nitrogen-containing silicon dioxide film. Next, two polysilicon films, interposing an ONO film therebetween, are deposited and then those films are patterned. In this manner, a memory gate electrode section, consisting of floating gate electrode, interelectrode insulating film and control gate electrode, is formed on the nitrogen-containing silicon dioxide film as a tunnel insulating film. At the same time, a select gate electrode section is also formed beside the memory gate electrode section. Then, p-type source/drain regions and intermediate diffused region are defined below these electrode sections. In this structure, electrons can be injected through a particular part of the tunnel insulating film and holes are trapped in a limited region of the tunnel insulating film.
摘要翻译：位于阱中的有源区上的二氧化硅膜在N2O环境中在1050℃退火，从而将氮扩散到二氧化硅膜中并形成含氮二氧化硅膜。接下来，沉积两个多晶硅膜，在其间插入ONO膜，然后将这些膜图案化。以这种方式，在作为隧道绝缘膜的含氮二氧化硅膜上形成由浮栅电极，电极间绝缘膜和控制栅电极构成的存储栅电极部。同时，在存储栅电极部分旁边也形成选择栅电极部分。然后，在这些电极部分下方限定p型源极/漏极区域和中间扩散区域。在这种结构中，可以通过隧道绝缘膜的特定部分注入电子，并且孔被捕获在隧道绝缘膜的有限区域中。

57. 发明授权

US06492672B1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US06492672B1
公开(公告)日：2002-12-10
申请号：US09629861
申请日：2000-08-01
申请人： Mizuki Segawa , Toshiki Yabu , Takashi Uehara , Takashi Nakabayashi , Kyoji Yamashita , Takaaki Ukeda , Masatoshi Arai , Takayuki Yamada
发明人： Mizuki Segawa , Toshiki Yabu , Takashi Uehara , Takashi Nakabayashi , Kyoji Yamashita , Takaaki Ukeda , Masatoshi Arai , Takayuki Yamada
IPC分类号： H01L27108
CPC分类号： H01L27/11526 , H01L21/82345 , H01L27/0629 , H01L27/105 , H01L27/11543 , H01L28/40 , Y10S438/957
摘要： A MOS transistor includes a gate oxide film, and a gate electrode which is formed by a lamination of first and second conductor films. A capacitive element includes a lower capacitive electrode formed of the first conductor film, a capacitive film made of an insulating film which is different from the gate oxide film, an upper capacitive electrode formed of the second conductor film on the capacitive film, and a leading electrode of the lower capacitive electrode formed of the second conductor film. At the same number of steps as in the case where the gate oxide film is used as the capacitive film, a semiconductor device can be manufactured with the capacitive film provided, the capacitive film being made of a nitride film or the like that is different from the gate oxide film. Consequently, a capacitive film having a great capacitance value per unit area is used so that the occupied area can be reduced and an increase in manufacturing cost can be controlled. In the semiconductor device in which a transistor, a capacitive element, a resistive film and the like are provided, the occupied area can be reduced and the manufacturing cost can be cut down.
摘要翻译： MOS晶体管包括栅极氧化膜和通过第一和第二导体膜的叠层形成的栅电极。电容元件包括由第一导体膜形成的下部电容电极，由与栅极氧化膜不同的绝缘膜制成的电容膜，由电容膜上的第二导体膜形成的上部电容电极，以及引线电极由第二导电膜形成。以与使用栅极氧化膜作为电容膜的情况相同的步骤，可以制造具有设置的电容膜的半导体器件，电容膜由与氮化物膜不同的氮化物膜等构成栅氧化膜。因此，使用具有每单位面积的大的电容值的电容膜，从而可以减小占用面积并且可以控制制造成本的增加。在其中提供晶体管，电容元件，电阻膜等的半导体器件中，可以减小占用面积并且可以减少制造成本。

58. 发明授权

US06472384B1 Antimicrobial compounds 有权
标题翻译：抗菌化合物
公开(公告)号：US06472384B1
公开(公告)日：2002-10-29
申请号：US09757393
申请日：2001-01-09
申请人： Masatoshi Inukai , Masakatsu Kaneko , Toshio Takatsu , Hitoshi Hotoda , Masatoshi Arai , Shunichi Miyakoshi , Masaaki Kizuka , Yasumasa Ogawa
发明人： Masatoshi Inukai , Masakatsu Kaneko , Toshio Takatsu , Hitoshi Hotoda , Masatoshi Arai , Shunichi Miyakoshi , Masaaki Kizuka , Yasumasa Ogawa
IPC分类号： A61K31553
CPC分类号： C07H19/06 , C12P17/16 , C12P17/162 , C12P17/167 , C12P19/38 , C12P19/40 , Y02P20/55
摘要： The present invention relates to ester, ether and N-alkylcarbamoyl derivatives of compound (Ia) and pharmaceutically acceptable salts thereof. These compounds exhibit excellent antibacterial activity and are useful for the treatment or prevention of bacterial infections. (wherein R1 is a hydrogen atom or a methyl group; R2a is a hydrogen atom, a protecting group for a hydroxy group, or a methyl group; R3 is a hydrogen atom or a protecting group for a hydroxy group; R4a is a hydrogen atom, a hydroxy group or a protected hydroxy group; R5 is a hydrogen atom or a protecting group for a hydroxy group; and X is a methylene group or a sulfur atom). The invention also includes compounds which are related to the aforeidentified compounds.
摘要翻译：本发明涉及化合物（Ia）的酯，醚和N-烷基氨基甲酰基衍生物及其药学上可接受的盐。这些化合物表现出优异的抗菌活性，可用于治疗或预防细菌感染（其中R1为氢原子或甲基; R2a为氢原子，羟基保护基或甲基; R3 是氢原子或羟基的保护基; R4a是氢原子，羟基或保护的羟基; R5是氢原子或羟基的保护基; X是亚甲基或硫原子）。本发明还包括与前述化合物有关的化合物。

59. 发明授权

US06456286B1 Apparatus and method for displaying three-dimensional polygons 有权
标题翻译：用于显示三维多边形的装置和方法
公开(公告)号：US06456286B1
公开(公告)日：2002-09-24
申请号：US09443140
申请日：1999-11-19
申请人： Masatoshi Arai , Ryosuke Miyata
发明人： Masatoshi Arai , Ryosuke Miyata
IPC分类号： G06T1530
CPC分类号： G06T15/00
摘要： A polygon rendering capability detecting part detects the rendering capability of the equipment used so as to calculate the total number of polygons Nap that can be allocated in one frame. A visual quality determining part determines an average area Sp represented by one polygon on a display screen as visual quality, and an optimum polygon number calculating part calculates the optimum number of polygons Np that can be allocated based on the size of a three-dimensional character projected on the display screen while maintaining the visual quality Sp constant. A polygon number adjusting part lowers the progressive polygon level of the three-dimensional character so that the number of polygons of the three-dimensional character is not less than the calculated optimum number of polygons and is the smallest number of polygons to which the number of polygons can be reduced. When the three-dimensional character moves and the Z value is changed, Np is updated so that Sp becomes constant.
摘要翻译：多边形呈现能力检测部分检测所使用的设备的渲染能力，以便计算可以在一帧中分配的多边形Nap的总数。视觉质量确定部件将由显示屏幕上的一个多边形表示的平均面积Sp确定为视觉质量，并且最佳多边形数量计算部分基于三维字符的大小来计算可以分配的最佳数量的多边形Np 投影在显示屏上，同时保持视觉质量Sp恒定。多边形数量调整部降低三维字符的渐进多边形等级，使得三维字符的多边形的数量不小于所计算的最佳多边形数，并且是多边形的最小数目可以减少多边形。当三维字符移动并且Z值改变时，Np被更新，使得Sp变得恒定。

60. 发明授权

US06410641B1 Cured rubber and method of treating cured rubber 有权
公开(公告)号：US06410641B1
公开(公告)日：2002-06-25
申请号：US09777904
申请日：2001-02-07
申请人： Shinichi Sato , Masatoshi Arai
发明人： Shinichi Sato , Masatoshi Arai
IPC分类号： C08L8308
摘要： A curable rubber composition comprising a curable organopolysiloxane or perfluoropolyether group-containing organosilicon compound, a curing agent therefor, and a silica filler having a mean particle size of 0.001-10 &mgr;m is cured into a cured rubber. For improving compression set, the cured rubber is post treated with a hydrolyzable aminosilane or amidosilane having a Si—N bond.

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