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51. 发明授权

US06940752B2 Nonvolatile semiconductor memory device 有权
公开(公告)号：US06940752B2
公开(公告)日：2005-09-06
申请号：US10920161
申请日：2004-08-18
申请人： Tomoharu Tanaka , Hiroshi Nakamura , Ken Takeuchi , Riichiro Shirota , Fumitaka Arai , Susumu Fujimura
发明人： Tomoharu Tanaka , Hiroshi Nakamura , Ken Takeuchi , Riichiro Shirota , Fumitaka Arai , Susumu Fujimura
IPC分类号： G11C7/00 , G11C11/56 , G11C16/34 , G11C16/04
CPC分类号： G11C16/0483 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C16/3404 , G11C16/3409 , G11C16/344 , G11C16/3445 , G11C16/345 , G11C16/3454 , G11C16/3459 , G11C16/3463 , G11C2211/5621
摘要： A NAND cell unit includes a plurality of memory cells which are connected in series. An erase operation is effected on all memory cells. Then, a soft-program voltage, which is opposite in polarity to the erase voltage applied in the erase operation, is applied to all memory cells, thereby setting all memory cells out of an over-erased state. Thereafter, a program voltage of 20V is applied to the control gate of any selected one of the memory cells, 0V is applied to the control gates of the two memory cells provided adjacent to the selected memory cell, and 11V is applied to the control gates of the remaining memory cells. Data is thereby programmed into the selected memory cell. The time for which the program voltage is applied to the selected memory cell is adjusted in accordance with the data to be programmed into the selected memory cell. Hence, data “0” can be correctly programmed into the selected memory cell, multi-value data can be read from any selected memory cell at high speed.

52. 发明授权

US06549464B2 Nonvolatile semiconductor memory device 有权
公开(公告)号：US06549464B2
公开(公告)日：2003-04-15
申请号：US10187285
申请日：2002-07-02
申请人： Tomoharu Tanaka , Hiroshi Nakamura , Ken Takeuchi , Riichiro Shirota , Fumitaka Arai , Susumu Fujimura
发明人： Tomoharu Tanaka , Hiroshi Nakamura , Ken Takeuchi , Riichiro Shirota , Fumitaka Arai , Susumu Fujimura
IPC分类号： G11C1604
CPC分类号： G11C16/0483 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C16/3404 , G11C16/3409 , G11C16/344 , G11C16/3445 , G11C16/345 , G11C16/3454 , G11C16/3459 , G11C16/3463 , G11C2211/5621
摘要： A NAND cell unit comprising a plurality of memory cells which are connected in series. An erase operation is effected on all memory cells. Then, a soft-program voltage, which is opposite in polarity to the erase voltage applied in the erase operation, is applied to all memory cells, thereby setting all memory cells out of an over-erased state. Thereafter, a program voltage of 20V is applied to the control gate of any selected one of the memory cells, 0V is applied to the control gates of the two memory cells provided adjacent to the selected memory cell, and 11V is applied to the control gates of the remaining memory cells. Data is thereby programmed into the selected memory cell. The time for which the program voltage is applied to the selected memory cell is adjusted in accordance with the data to be programmed into the selected memory cell. Hence, data “0” can be correctly programmed into the selected memory cell, multi-value data can be read from any selected memory cell at high speed.

53. 发明授权

US06434055B1 Nonvolatile semiconductor memory device 有权
公开(公告)号：US06434055B1
公开(公告)日：2002-08-13
申请号：US09767152
申请日：2001-01-23
申请人： Tomoharu Tanaka , Hiroshi Nakamura , Ken Takeuchi , Riichiro Shirota , Fumitaka Arai , Susumu Fujimura
发明人： Tomoharu Tanaka , Hiroshi Nakamura , Ken Takeuchi , Riichiro Shirota , Fumitaka Arai , Susumu Fujimura
IPC分类号： G11C1604
摘要： A NAND cell unit comprising a plurality of memory cells which are connected in series. An erase operation is effected on all memory cells. Then, a soft-program voltage, which is opposite in polarity to the erase voltage applied in the erase operation, is applied to all memory cells, thereby setting all memory cells out of an over-erased state. Thereafter, a program voltage of 20V is applied to the control gate of any selected one of the memory cells, 0V is applied to the control gates of the two memory cells provided adjacent to the selected memory cell, and 11V is applied to the control gates of the remaining memory cells. Data is thereby programmed into the selected memory cell. The time for which the program voltage is applied to the selected memory cell is adjusted in accordance with the data to be programmed into the selected memory cell. Hence, data “0” can be correctly programmed into the selected memory cell, multi-value data can be read from any selected memory cell at high speed.

54. 发明授权

US6151249A NAND-type EEPROM having bit lines and source lines commonly coupled through enhancement and depletion transistors 失效
标题翻译： NAND型EEPROM具有通常通过增强和耗尽晶体管耦合的位线和源极线
公开(公告)号：US6151249A
公开(公告)日：2000-11-21
申请号：US210288
申请日：1994-03-18
申请人： Riichiro Shirota , Masaki Momodomi
发明人： Riichiro Shirota , Masaki Momodomi
IPC分类号： G11C17/00 , G11C16/02 , G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/0483
摘要： In an EEPROM including a plurality of NAND memory cells each constituted by connecting memory cells each having a floating gate and a control gate in series with each other, first selection transistors respectively coupled between the same bit line and terminals, on one side, of each pair constituted by two NAND memory cells of the plurality of memory cells, and second selection transistors respectively coupled between terminals on the other side and source lines (SL), the first or second selection transistors are constituted by an enhancement transistor and a depletion transistor which are coupled in series with each other, and the arrangements of the depletion transistor and enhancement transistor of the first selection transistors are reversed to those of the second selection transistors in the same NAND memory cells.
摘要翻译：在包括多个NAND存储单元的EEPROM中，每个NAND存储单元通过将每个具有浮置栅极和控制栅极的存储单元彼此串联构成，第一选择晶体管分别耦合在每个相同位线和端子之间分别由多个存储单元中的两个NAND存储器单元构成的第一选择晶体管和分别耦合在另一侧的端子和源极线（SL）之间的第二选择晶体管，第一或第二选择晶体管由增强晶体管和耗尽型晶体管构成，彼此串联耦合，并且第一选择晶体管的耗尽晶体管和增强晶体管的布置与相同NAND存储器单元中的第二选择晶体管的布置相反。

55. 发明授权

US06828627B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US06828627B2
公开(公告)日：2004-12-07
申请号：US10742952
申请日：2003-12-23
申请人： Akira Goda , Kazuhiro Shimizu , Riichiro Shirota , Norihisa Arai , Naoki Koido , Seiichi Aritome , Tohru Maruyama , Hiroaki Hazama , Hirohisa Iizuka
发明人： Akira Goda , Kazuhiro Shimizu , Riichiro Shirota , Norihisa Arai , Naoki Koido , Seiichi Aritome , Tohru Maruyama , Hiroaki Hazama , Hirohisa Iizuka
IPC分类号： H01L2972
CPC分类号： H01L27/11521 , G11C16/0483 , H01L27/115 , H01L29/42324
摘要： A semiconductor device exhibits a stable driving force and high performance reliability. The semiconductor device has at least one transistor having a gate insulating film formed on a element region in a semiconductor substrate, a gate electrode formed on the gate insulating film, and a diffused layer in element regions on both sides of the gate electrode. The device also has a barrier insulating film formed so as to cover the transistor and the diffused layer. The height from a surface of the semiconductor substrate to the barrier insulating film is greater than the height from the surface, of the interface between the gate insulating film and the gate electrode.
摘要翻译：半导体器件具有稳定的驱动力和高性能的可靠性。半导体器件具有至少一个晶体管，其具有形成在半导体衬底中的元件区域上的栅极绝缘膜，形成在栅极绝缘膜上的栅极电极和在栅电极两侧的元件区域中的扩散层。该器件还具有形成为覆盖晶体管和扩散层的阻挡绝缘膜。从半导体衬底的表面到阻挡绝缘膜的高度大于栅极绝缘膜和栅电极之间的界面的表面的高度。

56. 发明授权

US06703669B1 Semiconductor device having serially connected memory cell transistors provided between two current terminals 有权
标题翻译：具有串联连接的存储单元晶体管的半导体器件设置在两个电流端子之间
公开(公告)号：US06703669B1
公开(公告)日：2004-03-09
申请号：US09714228
申请日：2000-11-17
申请人： Akira Goda , Kazuhiro Shimizu , Riichiro Shirota , Norihisa Arai , Naoki Koido , Seiichi Aritome , Tohru Maruyama , Hiroaki Hazama , Hirohisa Iizuka
发明人： Akira Goda , Kazuhiro Shimizu , Riichiro Shirota , Norihisa Arai , Naoki Koido , Seiichi Aritome , Tohru Maruyama , Hiroaki Hazama , Hirohisa Iizuka
IPC分类号： H01L29788
CPC分类号： H01L27/11521 , G11C16/0483 , H01L27/115 , H01L29/42324
摘要： A semiconductor device exhibits a stable driving force and high performance reliability. The semiconductor device has at least one transistor having a gate insulating film formed on a element region in a semiconductor substrate, a gate electrode formed on the gate insulating film, and a diffused layer in element regions on both sides of the gate electrode. The device also has a barrier insulating film formed so as to cover the transistor and the diffused layer. The height from a surface of the semiconductor substrate to the barrier insulating film is greater than the height from the surface, of the interface between the gate insulating film and the gate electrode.
摘要翻译：半导体器件具有稳定的驱动力和高性能的可靠性。半导体器件具有至少一个晶体管，其具有形成在半导体衬底中的元件区域上的栅极绝缘膜，形成在栅极绝缘膜上的栅极电极和在栅电极两侧的元件区域中的扩散层。该器件还具有形成为覆盖晶体管和扩散层的阻挡绝缘膜。从半导体衬底的表面到阻挡绝缘膜的高度大于栅极绝缘膜和栅电极之间的界面的表面的高度。

57. 发明授权

US06680230B2 Semiconductor device and method of fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06680230B2
公开(公告)日：2004-01-20
申请号：US10201111
申请日：2002-07-24
申请人： Norihisa Arai , Fumitaka Arai , Seiichi Aritome , Akira Shimizu , Riichiro Shirota
发明人： Norihisa Arai , Fumitaka Arai , Seiichi Aritome , Akira Shimizu , Riichiro Shirota
IPC分类号： H01L21336
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11546
摘要： A method of fabricating a semiconductor device which has a cell array with non-volatile memory transistors and a peripheral circuit including a first transistor and a second transistor as driven by a lower voltage than the first transistor is disclosed. The method includes the steps of forming over a semiconductor substrate a first gate dielectric film for use in the first transistor, selectively etching the first gate dielectric film in the cell array region to expose the substrate, forming over the exposed substrate a second gate dielectric film which is for use as a tunnel dielectric film of the memory transistors, forming a first gate electrode material film over the first and second gate dielectric films, selectively etching the first gate electrode material film and its underlying first gate dielectric film in the second transistor region, forming over the exposed substrate a third gate dielectric film which is for use in the second transistor, forming a second gate electrode material film over the third gate dielectric film, and forming gates of the respective transistors while letting the gates at least partly include the first and second gate electrode material films.
摘要翻译：公开了一种制造半导体器件的方法，该半导体器件具有具有非易失性存储晶体管的单元阵列和包括由比第一晶体管低的电压驱动的第一晶体管和第二晶体管的外围电路。该方法包括以下步骤：在半导体衬底上形成用于第一晶体管的第一栅极电介质膜，选择性地蚀刻电池阵列区域中的第一栅极电介质膜以暴露衬底，在暴露的衬底上形成第二栅极电介质膜其用作存储晶体管的隧道电介质膜，在第一和第二栅极电介质膜上形成第一栅电极材料膜，在第二晶体管区域中选择性地蚀刻第一栅电极材料膜及其下面的第一栅极电介质膜在暴露的衬底上形成用于第二晶体管的第三栅极电介质膜，在第三栅极电介质膜上形成第二栅电极材料膜，并且在使栅极至少部分地包括第一和第二栅电极材料膜。

58. 发明授权

US06462373B2 Nonvolatile semiconductor memory device having tapered portion on side wall of charge accumulation layer 失效
标题翻译：非易失性半导体存储器件在电荷累积层的侧壁上具有锥形部分
公开(公告)号：US06462373B2
公开(公告)日：2002-10-08
申请号：US09725564
申请日：2000-11-30
申请人： Kazuhiro Shimizu , Riichiro Shirota , Naoki Koido , Seiichi Aritome , Hiroaki Tsunoda , Tadashi Iguchi , Kazuhito Narita , Kunihiro Terasaka , Hirohisa Iizuka
发明人： Kazuhiro Shimizu , Riichiro Shirota , Naoki Koido , Seiichi Aritome , Hiroaki Tsunoda , Tadashi Iguchi , Kazuhito Narita , Kunihiro Terasaka , Hirohisa Iizuka
IPC分类号： H01L29788
CPC分类号： H01L27/11526 , H01L27/115 , H01L27/11521 , H01L27/11534
摘要： In a nonvolatile semiconductor memory device, a charge accumulation layer is formed between adjacent two device isolation regions, at least a portion of the charge accumulation layer sandwiched with the device isolation regions has side walls each having a taper angle of 80 degrees or more and less than 90 degrees so that the charge accumulation layer at a lower end has a width wider than that at an upper end, a size of an opening of each of the device isolation regions is 0.25 &mgr;m or less, and a gate length of a memory cell is 0.2 &mgr;m or less.
摘要翻译：在非易失性半导体存储器件中，在相邻的两个器件隔离区域之间形成电荷累积层，夹在器件隔离区域的电荷累积层的至少一部分具有各自具有80度以上的锥角的侧壁使得下端的电荷累积层的宽度比上端的宽度宽，器件隔离区域的开口尺寸为0.25μm以下，存储单元的栅极长度为0.2μm以下。

59. 发明授权

US06611010B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US06611010B2
公开(公告)日：2003-08-26
申请号：US09726582
申请日：2000-12-01
申请人： Akira Goda , Kazuhiro Shimizu , Yuji Takeuchi , Riichiro Shirota , Seiichi Aritome
发明人： Akira Goda , Kazuhiro Shimizu , Yuji Takeuchi , Riichiro Shirota , Seiichi Aritome
IPC分类号： H01L2710
CPC分类号： H01L21/76877 , H01L21/76885 , H01L23/5226 , H01L27/10885 , H01L27/10888 , H01L27/115 , H01L2924/0002 , H01L2924/00
摘要： In a bit line contact section, a contact hole is formed through a silicon oxide film, and a contact plug made of a polysilicon film doped with impurities is buried in the contact hole. The silicon oxide film is formed with a wiring groove overlapping the contact hole. A bit line made of a metal film is buried in the wiring groove. The contact plug extends through the bit line, and has its upper surface substantially coplanar with an upper surface of the bit line. The contact plug is in contact with the bit line only on its side surfaces.
摘要翻译：在位线接触部分中，通过氧化硅膜形成接触孔，并且在接触孔中埋设由掺杂杂质的多晶硅膜制成的接触塞。氧化硅膜形成有与接触孔重叠的布线槽。由金属膜制成的位线埋在布线槽中。接触插塞延伸穿过位线，并且其上表面与位线的上表面基本上共面。接触插塞仅在其侧面与位线接触。

60. 发明申请

US20060157801A1 Nonvolatile semiconductor memory device and method for manufacturing the same 失效
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20060157801A1
公开(公告)日：2006-07-20
申请号：US11302203
申请日：2005-12-14
申请人： Akira Goda , Riichiro Shirota , Kazuhiro Shimizu , Hiroaki Hazama , Hirohisa Iizuka , Seiichi Aritome , Wakako Moriyama
发明人： Akira Goda , Riichiro Shirota , Kazuhiro Shimizu , Hiroaki Hazama , Hirohisa Iizuka , Seiichi Aritome , Wakako Moriyama
IPC分类号： H01L29/76
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11529 , H01L27/11543 , Y10S257/909
摘要： A method for manufacturing a nonvolatile semiconductor memory device having a step of forming a first gate electrode on a peripheral circuit portion and a second gate electrode on a memory cell portion, a step of introducing impurity into the peripheral circuit portion and memory cell portion, a step of forming a first insulating film above at least the memory cell portion, and a step of annealing the semiconductor substrate into which the impurity has been introduced. The first gate electrode has a first gate length. The second gate electrode has a second gate length shorter than the first gate length.
摘要翻译：一种非易失性半导体存储器件的制造方法，具有在存储单元部分的外围电路部分和第二栅电极上形成第一栅电极的步骤，将杂质引入外围电路部分和存储单元部分的步骤，在至少所述存储单元部分之上形成第一绝缘膜的步骤，以及对其中引入了所述杂质的所述半导体衬底进行退火的步骤。第一栅电极具有第一栅极长度。第二栅电极具有比第一栅极长度短的第二栅极长度。

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