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51. 发明申请

US20110182130A1 LOW CURRENT WIDE VREF RANGE INPUT BUFFER 有权
标题翻译：低电流VREF范围输入缓冲器
公开(公告)号：US20110182130A1
公开(公告)日：2011-07-28
申请号：US13082514
申请日：2011-04-08
申请人： Timothy B. Cowles , Steve Casper
发明人： Timothy B. Cowles , Steve Casper
IPC分类号： G11C7/02 , H03K3/00
CPC分类号： H03K19/018528
摘要： A low-current input buffer is disclosed. The buffer uses self-biased N and P channel differential pairs with their outputs tied together. The self-biasing assists in reducing current consumption. The combination of N and P-channel differential pairs results in symmetry across a wide range of reference and supply voltages.
摘要翻译：公开了一种低电流输入缓冲器。缓冲器使用自偏置N和P通道差分对，其输出端连接在一起。自偏置有助于减少电流消耗。 N和P沟道差分对的组合导致了宽范围的参考电压和电源电压的对称性。

52. 发明授权

US07952169B2 Isolation circuit 有权
标题翻译：隔离电路
公开(公告)号：US07952169B2
公开(公告)日：2011-05-31
申请号：US12468482
申请日：2009-05-19
申请人： Timothy B. Cowles , Aron T. Lunde
发明人： Timothy B. Cowles , Aron T. Lunde
IPC分类号： H01L23/44 , H01L29/00
CPC分类号： G01R31/2884
摘要： An isolation circuit, comprising a first transistor having a gate, a first source/drain terminal, and a second source/drain terminal, a first pad coupled to the gate of the first transistor, the first pad operable to receive an enable signal, a second pad coupled to the first source/drain of the first transistor, the second pad operable to receive a ground potential, a first fuse device coupling the second source/drain terminal to a node, a second fuse device coupling the node to the first pad, a third pad operable to receive a signal to be applied to at least one die, and a second transistor operable to selectively transfer the signal received at the third pad to the at least one die in response to a control signal provided by the node.
摘要翻译：一种隔离电路，包括具有栅极的第一晶体管，第一源极/漏极端子和第二源极/漏极端子，耦合到第一晶体管的栅极的第一焊盘，第一焊盘可操作以接收使能信号，第二焊盘，其耦合到第一晶体管的第一源极/漏极，第二焊盘可操作以接收接地电位;将第二源极/漏极端子耦合到节点的第一熔丝器件;将节点耦合到第一焊盘的第二熔丝器件第三焊盘，其可操作以接收要施加到至少一个管芯的信号;以及第二晶体管，其可操作以响应于由所述节点提供的控制信号选择性地将在第三焊盘处接收的信号传输到至少一个管芯。

53. 发明申请

US20090296512A1 Apparatus for writing to mutiple banks of a memory device 有权
标题翻译：用于写入存储器件的多个存储体的装置
公开(公告)号：US20090296512A1
公开(公告)日：2009-12-03
申请号：US12462433
申请日：2009-08-04
申请人： Timothy B. Cowles , Jeffrey P. Wright
发明人： Timothy B. Cowles , Jeffrey P. Wright
IPC分类号： G11C8/12
CPC分类号： G11C11/406 , G11C7/1015 , G11C7/1072 , G11C8/12 , G11C11/40611 , G11C11/40615 , G11C29/26 , G11C2029/2602
摘要： In a multi-bank memory system such as a synchronous dynamic random access memory (SDRAM), a method of writing data to the banks is provided. This method allows for writing to any number of banks. More particularly, this method allows for writing to a selected number of banks between one and all banks. In addition, the method retains the discrete nature of the selected banks by allowing any row in each bank to be accessed regardless of the rows activated in other banks. As a result, rows of different memory banks that are intended to store similar data may be accessed simultaneously for purposes of writing the data in test and non-test modes. This allows for quicker writing to the SDRAM without the errors that may be created by other fast writing modes, such as data compression.
摘要翻译：在诸如同步动态随机存取存储器（SDRAM）的多存储体存储器系统中，提供了将数据写入存储体的方法。这种方法允许写入任意数量的银行。更具体地说，这种方法允许写入一个和所有银行之间的选定数量的银行。此外，该方法通过允许每个存储体中的任何行被访问而保留所选存储体的离散性质，而不管其他存储体中激活的行如何。因此，为了将数据写入测试和非测试模式的目的，可以同时访问旨在存储类似数据的不同存储体的行。这允许更快地写入SDRAM，而不会由其他快速写入模式（如数据压缩）创建的错误。

54. 发明授权

US07378290B2 Isolation circuit 有权
标题翻译：隔离电路
公开(公告)号：US07378290B2
公开(公告)日：2008-05-27
申请号：US10929898
申请日：2004-08-30
申请人： Timothy B. Cowles , Aron T. Lunde
发明人： Timothy B. Cowles , Aron T. Lunde
IPC分类号： H01L21/66
CPC分类号： G01R31/2884
摘要： An isolation circuit includes a first pad adapted to receive a control signal and a second pad adapted to receive another signal. A third pad is coupled to a microelectronic die and a device is provided to transfer the other signal from the second pad to the third pad in response to the control signal.
摘要翻译：隔离电路包括适于接收控制信号的第一焊盘和适于接收另一信号的第二焊盘。第三焊盘耦合到微电子管芯，并且提供设备以响应于控制信号将另一信号从第二焊盘传送到第三焊盘。

55. 发明授权

US07289384B2 Method for writing to multiple banks of a memory device 失效
标题翻译：写入存储器设备的多个组的方法
公开(公告)号：US07289384B2
公开(公告)日：2007-10-30
申请号：US10850011
申请日：2004-05-19
申请人： Timothy B. Cowles , Jeffrey P. Wright
发明人： Timothy B. Cowles , Jeffrey P. Wright
IPC分类号： G11C8/00
CPC分类号： G11C11/406 , G11C7/1015 , G11C7/1072 , G11C8/12 , G11C11/40611 , G11C11/40615 , G11C29/26 , G11C2029/2602
摘要： In a multi-bank memory system such as a synchronous dynamic random access memory (SDRAM), a method of writing data to the banks is provided. This method allows for writing to any number of banks. More particularly, this method allows for writing to a selected number of banks between one and all banks. In addition, the method retains the discrete nature of the selected banks by allowing any row in each bank to be accessed regardless of the rows activated in other banks. As a result, rows of different memory banks that are intended to store similar data may be accessed simultaneously for purposes of writing the data in test and non-test modes. This allows for quicker writing to the SDRAM without the errors that may be created by other fast writing modes, such as data compression.
摘要翻译：在诸如同步动态随机存取存储器（SDRAM）的多存储体存储器系统中，提供了将数据写入存储体的方法。这种方法允许写入任意数量的银行。更具体地说，这种方法允许写入一个和所有银行之间的选定数量的银行。此外，该方法通过允许每个存储体中的任何行被访问而保留所选存储体的离散性质，而不管其他存储体中激活的行如何。因此，为了将数据写入测试和非测试模式的目的，可以同时访问旨在存储类似数据的不同存储体的行。这允许更快地写入SDRAM，而不会由其他快速写入模式（如数据压缩）创建的错误。

56. 发明授权

US07079439B2 Low power auto-refresh circuit and method for dynamic random access memories 失效
公开(公告)号：US07079439B2
公开(公告)日：2006-07-18
申请号：US10868741
申请日：2004-06-14
申请人： Timothy B. Cowles , Brian M. Shirley , Greg A. Blodgett
发明人： Timothy B. Cowles , Brian M. Shirley , Greg A. Blodgett
IPC分类号： G11C7/00
CPC分类号： G11C11/40611 , G11C11/406 , G11C11/40615 , G11C2211/4065 , G11C2211/4067
摘要： A power saving circuit disables input buffers for command and address signals during an auto-refresh of a DRAM. The input buffers are re-enabled at the end of the auto-refresh in a manner that does not cause spurious commands to be generated. The power saving circuit prevents spurious commands by biasing internal command signals to a “no operation” command whenever the input buffers for the command signals are disabled. The DRAM may also be placed in a mode in which it automatically transitions to a low power precharge mode at the end of the auto-refresh to further reduce power consumed by the DRAM.

57. 发明授权

US07006394B2 Apparatus and method for semiconductor device repair with reduced number of programmable elements 失效
公开(公告)号：US07006394B2
公开(公告)日：2006-02-28
申请号：US10862532
申请日：2004-06-07
申请人： Timothy B. Cowles , Todd A. Merritt
发明人： Timothy B. Cowles , Todd A. Merritt
IPC分类号： G11C7/00
CPC分类号： G11C29/812 , G11C29/787
摘要： An apparatus and method using a reduced number of nonvolatile programming elements for enabling redundant memory blocks in a semiconductor memory is disclosed. A redundancy selection module may be configured using N fuses to configure and select 2N−1 repair modules. Programming fuses effectively separates the repair modules into two sets, those with an even address and those with an odd address. Each repair module contains fuses programmed with a selected address, such that the repair module may respond when an address input matches the selected address. However, the least significant bit is left out of the programming. As a result, repair modules in the even set respond to even addresses matching the selected address and repair modules in the odd set respond to odd addresses matching the selected address. Similar arrangements may be used to reduce the number of enable fuses and disable fuses required for each repair module.

58. 发明授权

US07006393B2 Method and apparatus for semiconductor device repair with reduced number of programmable elements 失效
标题翻译：减少可编程元件数量的半导体器件修复方法和装置
公开(公告)号：US07006393B2
公开(公告)日：2006-02-28
申请号：US10862284
申请日：2004-06-07
申请人： Todd A. Merritt , Timothy B. Cowles , Vikram K. Bollu
发明人： Todd A. Merritt , Timothy B. Cowles , Vikram K. Bollu
IPC分类号： G11C7/00
CPC分类号： G11C29/806 , G11C29/81
摘要： An apparatus and method using a reduced number of fuses for enabling redundant memory blocks in a semiconductor memory is disclosed. In one embodiment, a redundancy selection module may be configured using selection fuses, wherein each selection fuse selects a pair of repair modules. In another embodiment, a redundancy selection module may be configured using selection fuses, wherein each selection fuse may select a power of two (i.e., 1, 2, 4, 8, etc.) number of repair modules. Each repair module includes fuses programmed with a selected address, such that the repair module may respond when an address input matches the selected address. However, the Least Significant Bit (LSB) is uninvolved in the address programming. Instead, the LSB is compared to the values of the selection fuses. As a result, repair modules select a redundant memory block based on a combination of the selected address comparison and the separate LSB comparison.
摘要翻译：公开了一种使用减少数量的保险丝来实现半导体存储器中的冗余存储块的装置和方法。在一个实施例中，可以使用选择熔丝配置冗余选择模块，其中每个选择熔丝选择一对修复模块。在另一个实施例中，冗余选择模块可以使用选择熔丝来配置，其中每个选择熔丝可以选择两个（即1,2,4,8等）数量的修复模块的功率。每个修理模块包括用所选地址编程的保险丝，使得当地址输入与选择的地址匹配时，修复模块可以响应。但是，最低有效位（LSB）不涉及地址编程。而是将LSB与选择保险丝的值进行比较。因此，修复模块基于所选地址比较和单独的LSB比较的组合来选择冗余存储块。

59. 发明授权

US06816994B2 Low power buffer implementation 失效
标题翻译：低功耗缓冲器实现
公开(公告)号：US06816994B2
公开(公告)日：2004-11-09
申请号：US10175857
申请日：2002-06-21
申请人： Aaron Schoenfeld , Greg A. Blodgett , Timothy B. Cowles
发明人： Aaron Schoenfeld , Greg A. Blodgett , Timothy B. Cowles
IPC分类号： G06F1750
CPC分类号： G06F1/10 , G06F1/3203 , G06F1/3225 , G06F1/3275 , H03K19/0016 , Y02D10/14
摘要： A lower current input buffer is used for waking up a plurality of higher-current buffers. The lower current buffer monitors a wake-up signal and, when present, enables the higher current buffers. A higher current buffer is used to detect the sleep mode and disable the higher current buffers. A delay circuit may be used to balance the propagation delay through the circuit.

60. 发明授权

US06801469B2 Method of providing voltage to a circuit 有权
标题翻译：向电路提供电压的方法
公开(公告)号：US06801469B2
公开(公告)日：2004-10-05
申请号：US10644107
申请日：2003-08-20
申请人： Timothy B. Cowles
发明人： Timothy B. Cowles
IPC分类号： G11C700
CPC分类号： G11C17/18 , G11C17/16 , G11C2207/105
摘要： As part of anti-fuse circuitry for a memory device, a preferred exemplary embodiment of the current invention provides a direct connection between an anti-fuse and a contact pad used to provide voltage to that anti-fuse. The contact pad also serves as a voltage source for at least one other part of the memory device. At least one circuit coupled to the anti-fuse is temporarily isolated from it in the event that a voltage present at the pad would damage the circuit or cause the circuit to improperly read the status of the anti-fuse. The contact pad is available during a probe stage of the in-process memory device, but once the device is packaged, access to that contact pad is prevented. At the back end of the production process, the anti-fuse may be accessed through a second pad, whose electrical communication with the anti-fuse is regulated.
摘要翻译：作为用于存储器件的反熔丝电路的一部分，本发明的优选示例性实施例提供了用于向该抗熔丝提供电压的反熔丝和接触焊盘之间的直接连接。接触垫还用作存储器件的至少另一部分的电压源。在存在于焊盘处的电压会损坏电路或导致电路不正确地读取反熔丝的状态的情况下，耦合到反熔丝的至少一个电路与其暂时隔离。接触垫在进程内存储器件的探针级期间可用，但一旦器件被封装，则可以防止接触该接触垫。在生产过程的后端，可以通过第二焊盘访问抗熔丝，其中第二焊盘与抗熔丝进行电连接。

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