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51. 发明申请

US20050145983A1 Structures and methods of anti-fuse formation in SOI 有权
公开(公告)号：US20050145983A1
公开(公告)日：2005-07-07
申请号：US11055106
申请日：2005-02-11
申请人： Claude Bertin , Ramachandra Divakaruni , Russell Houghton , Jack Mandelman , William Tonti
发明人： Claude Bertin , Ramachandra Divakaruni , Russell Houghton , Jack Mandelman , William Tonti
IPC分类号： H01L21/82 , H01L21/334 , H01L23/525 , H01L27/108 , H01L27/12 , H01L29/00
CPC分类号： H01L23/5252 , H01L27/10829 , H01L27/10897 , H01L27/1203 , H01L29/66181 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An anti-fuse structure that can be programmed at low voltage and current and which potentially consumes very little chip spaces and can be formed interstitially between elements spaced by a minimum lithographic feature size is formed on a composite substrate such as a silicon-on-insulator wafer by etching a contact through an insulator to a support semiconductor layer, preferably in combination with formation of a capacitor-like structure reaching to or into the support layer. The anti-fuse may be programmed either by the selected location of conductor formation and/or damaging a dielectric of the capacitor-like structure. An insulating collar is used to surround a portion of either the conductor or the capacitor-like structure to confine damage to the desired location. Heating effects voltage and noise due to programming currents are effectively isolated to the bulk silicon layer, permitting programming during normal operation of the device. Thus the potential for self-repair without interruption of operation is realized.

52. 发明授权

US06266272B1 Partially non-volatile dynamic random access memory formed by a plurality of single transistor cells used as DRAM cells and EPROM cells 有权
标题翻译：由用作DRAM单元和EPROM单元的多个单晶体管单元形成的部分非易失性动态随机存取存储器
公开(公告)号：US06266272B1
公开(公告)日：2001-07-24
申请号：US09364841
申请日：1999-07-30
申请人： Toshiaki Kirihata , Daniel Storaska , Chandrasekhar Narayan , William Tonti , Claude Bertin , Nick van Heel
发明人： Toshiaki Kirihata , Daniel Storaska , Chandrasekhar Narayan , William Tonti , Claude Bertin , Nick van Heel
IPC分类号： G11C1450
CPC分类号： G11C16/02 , G11C11/005
摘要： A Partially Non-Volatile Dynamic Random Access Memory (PNDRAM) uses a DRAM array formed by a plurality of single transistor (1T) cells or two transistor (2T) cells. The cells are electrically programmable as a non-volatile memory. This results in a single chip design featuring both, a dynamic random access memory (DRAM) and an electrically programmable-read-only-memory (EPROM). The DRAM and the EPROM integrated in the PNDRAM can be easily reconfigured at any time, whether during manufacturing or in the field. The PNDRAM has multiple applications such as combining a main memory with ID, BIOS, or operating system information in a single chip.
摘要翻译：部分非易失性动态随机存取存储器（PNDRAM）使用由多个单晶体管（1T）单元或两个晶体管（2T）单元形成的DRAM阵列。电池可电可编程为非易失性存储器。这导致具有动态随机存取存储器（DRAM）和电可编程只读存储器（EPROM）的单芯片设计。集成在PNDRAM中的DRAM和EPROM可以随时重新配置，无论是在制造还是在现场。 PNDRAM具有多个应用，例如将主内存与ID，BIOS或操作系统信息组合在一个芯片中。

53. 发明授权

US5307942A Electronic, especially telecommunication equipment rack 失效
标题翻译：电子，特别是电信设备机架
公开(公告)号：US5307942A
公开(公告)日：1994-05-03
申请号：US981591
申请日：1992-11-25
申请人： Guy Quelfeter , Rene Femenia , Denis Le Jeune , Remi Verdurand , Claude Bertin
发明人： Guy Quelfeter , Rene Femenia , Denis Le Jeune , Remi Verdurand , Claude Bertin
IPC分类号： H05K7/18 , A47F5/00
CPC分类号： H05K7/186
摘要： Each upright of an electronic, especially telecommunication equipment rack comprises an outer profile and an inner profile delimiting a hollow interior volume used to run connections along equipment supported by said uprights. The profiles are such that the interior volume has in the heightwise and depthwise directions an opening accessible from the front side of the rack providing easy access to the connections along all of their path between the points at which they enter and leave the interior volume.
摘要翻译：电子，特别是电信设备机架的每个立柱包括外轮廓和内轮廓，其限定用于沿着由所述立柱支撑的设备运行连接的中空内部容积。轮廓使得内部容积在高度方向和深度方向具有从机架的前侧可接近的开口，其提供了在它们进入和离开内部容积的点之间沿着它们的所有路径的连接的容易的接近。

54. 发明申请

US20070210845A1 Storage elements using nanotube switching elements 有权
公开(公告)号：US20070210845A1
公开(公告)日：2007-09-13
申请号：US11651263
申请日：2007-01-09
申请人： Claude Bertin
发明人： Claude Bertin
IPC分类号： H03K3/289
CPC分类号： B82Y10/00 , G11C13/025 , Y10S977/936 , Y10S977/94
摘要： Data storage circuits and components of such circuits constructed using nanotube switching elements. The storage circuits may be stand-alone devices or cells incorporated into other devices or circuits. The data storage circuits include or can be used in latches, master-slave flip-flops, digital logic circuits, memory devices and other circuits. In one aspect of the invention, a master-slave flip-flop is constructed using one or more nanotube switching element-based storage devices. The master storage element or the slave storage element or both may be constructed using nanotube switching elements, for example, using two nanotube switching element-based inverters. The storage elements may be volatile or non-volatile. An equilibration device is provided for protecting the stored data from fluctuations on the inputs. Input buffers and output buffers for data storage circuits of the invention may also be constructed using nanotube switching elements.

55. 发明申请

US20060061389A1 Integrated nanotube and field effect switching device 有权
标题翻译：集成纳米管和场效应开关器件
公开(公告)号：US20060061389A1
公开(公告)日：2006-03-23
申请号：US11033089
申请日：2005-01-10
申请人： Claude Bertin
发明人： Claude Bertin
IPC分类号： H03K19/20
CPC分类号： G11C13/025 , B82Y10/00 , G11C23/00 , G11C2213/17 , H01H1/0094 , H03K17/545 , H03K19/08 , Y10S977/70 , Y10S977/94
摘要： Hybrid switching devices integrate nanotube switching elements with field effect devices, such as NFETs and PFETs. A switching device forms and unforms a conductive channel from the signal input to the output subject to the relative state of the control input. In embodiments of the invention, the conductive channel includes a nanotube channel element and a field modulatable semiconductor channel element. The switching device may include a nanotube switching element and a field effect device electrically disposed in series. According to one aspect of the invention, an integrated switching device is a four-terminal device with a signal input terminal, a control input terminal, a second input terminal, and an output terminal. The devices may be non-volatile. The devices can form the basis for a hybrid NT-FET logic family and can be used to implement any Boolean logic circuit.
摘要翻译：混合开关器件将纳米管开关元件与场效应器件（例如NFET和PFET）集成。开关装置根据控制输入的相对状态，将导电通道从输入到输出的信号输入形成和取消。在本发明的实施例中，导电通道包括纳米管通道元件和场可调制半导体通道元件。开关装置可以包括串联电配置的纳米管开关元件和场效应器件。根据本发明的一个方面，集成开关装置是具有信号输入端子，控制输入端子，第二输入端子和输出端子的四端子装置。这些设备可能是非易失性的。这些器件可以构成混合型NT-FET逻辑系列的基础，可用于实现任何布尔逻辑电路。

56. 发明申请

US20060044035A1 Storage elements using nanotube switching elements 失效
标题翻译：使用纳米管开关元件的存储元件
公开(公告)号：US20060044035A1
公开(公告)日：2006-03-02
申请号：US11032983
申请日：2005-01-10
申请人： Claude Bertin
发明人： Claude Bertin
IPC分类号： H03K3/289
CPC分类号： B82Y10/00 , G11C13/025 , Y10S977/936 , Y10S977/94
摘要： Data storage circuits and components of such circuits constructed using nanotube switching elements. The storage circuits may be stand-alone devices or cells incorporated into other devices or circuits. The data storage circuits include or can be used in latches, master-slave flip-flops, digital logic circuits, memory devices and other circuits. In one aspect of the invention, a master-slave flip-flop is constructed using one or more nanotube switching element-based storage devices. The master storage element or the slave storage element or both may be constructed using nanotube switching elements, for example, using two nanotube switching element-based inverters. The storage elements may be volatile or non-volatile. An equilibration device is provided for protecting the stored data from fluctuations on the inputs. Input buffers and output buffers for data storage circuits of the invention may also be constructed using nanotube switching elements.
摘要翻译：使用纳米管开关元件构造的这种电路的数据存储电路和部件。存储电路可以是并入设备或电路中的独立设备或单元。数据存储电路包括或可用于锁存器，主从触发器，数字逻辑电路，存储器件和其它电路。在本发明的一个方面，使用一个或多个基于纳米管开关元件的存储装置来构造主从触发器。主存储元件或从存储元件或二者可以使用例如使用两个基于纳米管开关元件的反相器的纳米管开关元件来构造。存储元件可以是挥发性的或非挥发性的。提供了一种平衡装置，用于保护存储的数据免受输入上的波动。本发明的数据存储电路的输入缓冲器和输出缓冲器也可以使用纳米管开关元件构成。

57. 发明申请

US20050282515A1 Receiver circuit using nanotube-based switches and transistors 有权
标题翻译：使用基于纳米管的开关和晶体管的接收器电路
公开(公告)号：US20050282515A1
公开(公告)日：2005-12-22
申请号：US11033213
申请日：2005-01-10
申请人： Claude Bertin
发明人： Claude Bertin
IPC分类号： G11C13/02 , H04B1/16
CPC分类号： G11C13/025 , B82Y10/00 , G11C23/00 , G11C2213/17 , H01L51/0048 , H01L51/0591 , Y10S977/70
摘要： Receiver circuits using nanotube-based switches and transistors. A receiver circuit includes a differential input having a first and second input link, a differential output having a first and second output link, and first and second switching elements in electrical communication with the input links and the output links. Each switching element has an input node, an output node, a nanotube channel element, and a control structure disposed in relation to the nanotube channel element to controllably form and unform an electrically conductive channel between said input node and said output node. First and second MOS transistors are each in electrical communication with a reference signal and with the output node of a corresponding one of the first and second switching elements.
摘要翻译：使用基于纳米管的开关和晶体管的接收器电路。接收器电路包括具有第一和第二输入链路的差分输入，具有第一和第二输出链路的差分输出以及与输入链路和输出链路电连通的第一和第二开关元件。每个开关元件具有输入节点，输出节点，纳米管通道元件和相对于纳米管通道元件设置的控制结构，以在所述输入节点和所述输出节点之间可控制地形成和取消导电通道。第一和第二MOS晶体管各自与参考信号电连通，并且与第一和第二开关元件中相应的一个的输出节点电连通。

58. 发明申请

US20050280436A1 Nanotube-based logic driver circuits 失效
标题翻译：基于纳米管的逻辑驱动电路
公开(公告)号：US20050280436A1
公开(公告)日：2005-12-22
申请号：US11033216
申请日：2005-01-10
申请人： Claude Bertin
发明人： Claude Bertin
IPC分类号： G11C13/02 , H03K19/003 , H03K19/02
CPC分类号： G11C13/025 , B82Y10/00 , G11C23/00 , G11C2213/16 , H03K19/02
摘要： Nanotube based logic driver circuits. These include pull-up driver circuits, push-pull driver circuits, tristate driver circuits, among others. Under one embodiment, an off-chip driver circuit includes a differential input having first and second signal links, each coupled to a respective one of two differential, on-chip signals. At least one output link is connectable to an off-chip impedance load, and at least one switching element has an input node, an output node, a nanotube channel element, and a control structure disposed in relation to the nanotube channel element to controllably form and unform an electrically conductive channel between said input node and said output node. The input node is coupled to a reference signal and the control structure is coupled to the first and second signal links. The output node is coupled to the output link, and the channel element is sized to carry sufficient current to drive said off-chip impedance load.
摘要翻译：基于纳米管的逻辑驱动电路。这些包括上拉驱动电路，推挽驱动电路，三态驱动电路等。在一个实施例中，片外驱动器电路包括具有第一和第二信号链路的差分输入，每个信号链路耦合到两个差分片上信号中的相应一个。至少一个输出链路可连接到片外阻抗负载，并且至少一个开关元件具有输入节点，输出节点，纳米管通道元件和相对于纳米管通道元件设置的可控制地形成的控制结构并且在所述输入节点和所述输出节点之间取消导电通道。输入节点耦合到参考信号，并且控制结构耦合到第一和第二信号链路。输出节点耦合到输出链路，并且信道单元的大小适于承载足够的电流以驱动所述片外阻抗负载。

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