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51. 发明申请

US20100157668A1 Memory device and method of operating and fabricating the same 有权
标题翻译：存储器件及其操作和制造方法
公开(公告)号：US20100157668A1
公开(公告)日：2010-06-24
申请号：US12659159
申请日：2010-02-26
申请人： Chang-Hyun Lee , Byeong-In Choi
发明人： Chang-Hyun Lee , Byeong-In Choi
IPC分类号： G11C16/00 , H01L29/788
CPC分类号： H01L27/115 , H01L27/11568
摘要： A memory transistor including a substrate, a tunnel insulating pattern on the substrate, a charge storage pattern on the tunnel insulating pattern, a blocking insulating pattern on the charge storage pattern, and a gate electrode on the blocking insulating pattern, the blocking insulating pattern surrounding the gate electrode and methods of operating and fabricating the same. A nonvolatile memory may further include a plurality of memory transistors in series and a plurality of auxiliary structures between each of the plurality of unit transistors in series. Each of the plurality of auxiliary structures may be a dummy mask pattern or an assistant gate structure.
摘要翻译：一种存储晶体管，包括衬底，衬底上的隧道绝缘图案，隧道绝缘图案上的电荷存储图案，电荷存储图案上的阻挡绝缘图案，以及阻挡绝缘图案上的栅电极，阻挡绝缘图案周围栅电极及其操作和制造方法。非易失性存储器还可以包括串联的多个存储晶体管和多个单元晶体管中的每一个之间的多个辅助结构。多个辅助结构中的每一个可以是虚拟掩模图案或辅助栅极结构。

52. 发明申请

US20090294837A1 Nonvolatile Memory Devices Having a Fin Shaped Active Region 失效
标题翻译：具有鳍形活动区域的非易失性存储器件
公开(公告)号：US20090294837A1
公开(公告)日：2009-12-03
申请号：US12536740
申请日：2009-08-06
申请人： Chang-Hyun Lee , Jung-Dal Choi , Chang-Seok Kang , Yoo-Cheol Shin , Jong-Sun Sel
发明人： Chang-Hyun Lee , Jung-Dal Choi , Chang-Seok Kang , Yoo-Cheol Shin , Jong-Sun Sel
IPC分类号： H01L29/792 , H01L29/78
CPC分类号： H01L27/115 , H01L27/11521
摘要： A nonvolatile memory device includes a semiconductor substrate and a device isolation layer on the semiconductor substrate. A fin-shaped active region is formed between portions of the device isolation layer. A sidewall protection layer is formed on the sidewall of the fin-shaped active region where source and drain regions are formed. Thus, it may be possible to reduce the likelihood of an undesirable connection between an interconnection layer connected to the source and drain regions and a lower sidewall of the active region so that charge leakage from the interconnection layer to a substrate can be prevented or reduced. The sidewall protection layer may be formed using the device isolation layer. Alternatively, an insulating layer having an etch selectivity with respect to an interlayer insulating layer may be formed on the device isolation layer so as to cover the sidewall of the active region.
摘要翻译：非易失性存储器件包括半导体衬底和半导体衬底上的器件隔离层。翅片形有源区形成在器件隔离层的各部分之间。侧壁保护层形成在形成源区和漏区的鳍状有源区的侧壁上。因此，可以降低连接到源极和漏极区域的互连层和有源区域的下侧壁之间的不期望的连接的可能性，从而可以防止或减少从互连层到衬底的电荷泄漏。侧壁保护层可以使用器件隔离层形成。或者，可以在器件隔离层上形成具有相对于层间绝缘层的蚀刻选择性的绝缘层，以覆盖有源区的侧壁。

53. 发明申请

US20090253244A1 Nonvolatile Memory Devices Having Gate Structures Doped by Nitrogen and Methods of Fabricating the Same 有权
标题翻译：具有由氮掺杂的栅极结构的非易失性存储器件及其制造方法
公开(公告)号：US20090253244A1
公开(公告)日：2009-10-08
申请号：US12488061
申请日：2009-06-19
申请人： Chang-Hyun Lee , Dong-Gun Park
发明人： Chang-Hyun Lee , Dong-Gun Park
IPC分类号： H01L21/336 , H01L21/762
CPC分类号： H01L21/265 , B82Y10/00 , H01L21/28202 , H01L21/28273 , H01L21/28282 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L29/42324 , H01L29/513 , H01L29/66825 , H01L29/66833 , H01L29/7881 , H01L29/7885 , H01L29/792
摘要： Nonvolatile memory devices are provided including an integrated circuit substrate and a charge storage pattern on the integrated circuit substrate. The charge storage pattern has a sidewall and a tunnel insulating layer is provided between the charge storage pattern and the integrated circuit substrate. A gate pattern is provided on the charge storage pattern. A blocking insulating layer is provided between the charge storage pattern and the gate pattern. The sidewall of the charge storage pattern includes a first nitrogen doped layer. Related methods of fabricating nonvolatile memory devices are also provided herein.
摘要翻译：在集成电路基板上提供集成电路基板和电荷存储图案的非易失性存储器件。电荷存储图案具有侧壁，并且在电荷存储图案和集成电路基板之间设置隧道绝缘层。在电荷存储图案上提供栅极图案。在电荷存储图案和栅极图案之间设置隔离绝缘层。电荷存储图案的侧壁包括第一氮掺杂层。本文还提供了制造非易失性存储器件的相关方法。

54. 发明申请

US20090250747A1 NON-VOLATILE MEMORY DEVICES HAVING A MULTI-LAYERED CHARGE STORAGE LAYER 有权
标题翻译：具有多层电荷存储层的非易失性存储器件
公开(公告)号：US20090250747A1
公开(公告)日：2009-10-08
申请号：US12422862
申请日：2009-04-13
申请人： Chang-Hyun Lee , Kyu-Charn Park
发明人： Chang-Hyun Lee , Kyu-Charn Park
IPC分类号： H01L29/792
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/115 , H01L27/11526 , H01L27/11546
摘要： A non-volatile memory device includes a substrate having a first region and a second region. A first gate electrode is disposed on the first region. A multi-layered charge storage layer is interposed between the first gate electrode and the substrate, the multi-layered charge storage including a tunnel insulation, a trap insulation, and a blocking insulation layer which are sequentially stacked. A second gate electrode is placed on the substrate of the second region, the second gate electrode including a lower gate and an upper gate connected to a region of an upper surface of the lower gate. A gate insulation layer is interposed between the second gate electrode and the substrate. The first gate electrode and the upper gate of the second gate electrode comprise a same material.
摘要翻译：非易失性存储器件包括具有第一区域和第二区域的衬底。第一栅电极设置在第一区域上。在第一栅电极和基板之间插入多层电荷存储层，多层电荷存储包括依次堆叠的隧道绝缘，阱绝缘和阻挡绝缘层。第二栅极被放置在第二区域的衬底上，第二栅极包括下栅极和连接到下栅极的上表面区域的上栅极。栅极绝缘层介于第二栅电极和衬底之间。第二栅电极的第一栅电极和上栅极包括相同的材料。

55. 发明申请

US20080265307A1 NON-VOLATILE SEMICONDUCTOR MEMORY DEVICES 有权
公开(公告)号：US20080265307A1
公开(公告)日：2008-10-30
申请号：US12133858
申请日：2008-06-05
申请人： Chang-Hyun Lee , Jung-Dal Choi , Byoung-Woo Ye
发明人： Chang-Hyun Lee , Jung-Dal Choi , Byoung-Woo Ye
IPC分类号： H01L29/792
CPC分类号： H01L27/11521 , B82Y10/00 , H01L21/28273 , H01L21/28282 , H01L27/115 , H01L27/11524 , H01L27/11568 , H01L29/42324 , H01L29/42332 , H01L29/513 , H01L29/7881 , H01L29/792
摘要： A non-volatile memory device includes a tunneling insulating layer on a semiconductor substrate, a charge storage layer, a blocking insulating layer, and a gate electrode. The charge storage layer is on the tunnel insulating layer and has a smaller band gap than the tunnel insulating layer and has a greater band gap than the semiconductor substrate. The blocking insulating layer is on the charge storage layer and has a greater band gap than the charge storage layer and has a smaller band gap than the tunnel insulating layer. The gate electrode is on the blocking insulating layer.

56. 发明申请

US20080106934A1 Memory device and method of operating and fabricating the same 有权
标题翻译：存储器件及其操作和制造方法
公开(公告)号：US20080106934A1
公开(公告)日：2008-05-08
申请号：US11898252
申请日：2007-09-11
申请人： Chang-Hyun Lee , Byeong-In Choi
发明人： Chang-Hyun Lee , Byeong-In Choi
IPC分类号： H01L29/788 , G11C11/40 , H01L21/3205
CPC分类号： H01L27/115 , H01L27/11568
摘要： A memory transistor including a substrate, a tunnel insulating pattern on the substrate, a charge storage pattern on the tunnel insulating pattern, a blocking insulating pattern on the charge storage pattern, and a gate electrode on the blocking insulating pattern, the blocking insulating pattern surrounding the gate electrode and methods of operating and fabricating the same. A nonvolatile memory may further include a plurality of memory transistors in series and a plurality of auxiliary structures between each of the plurality of unit transistors in series. Each of the plurality of auxiliary structures may be a dummy mask pattern or an assistant gate structure.
摘要翻译：一种存储晶体管，包括衬底，衬底上的隧道绝缘图案，隧道绝缘图案上的电荷存储图案，电荷存储图案上的阻挡绝缘图案，以及阻挡绝缘图案上的栅电极，阻挡绝缘图案周围栅电极及其操作和制造方法。非易失性存储器还可以包括串联的多个存储晶体管和多个单元晶体管中的每一个之间的多个辅助结构。多个辅助结构中的每一个可以是虚拟掩模图案或辅助栅极结构。

57. 发明申请

US20070284645A1 Non-volatile memory devices having a multi-layered charge storage layer and methods of forming the same 有权
标题翻译：具有多层电荷存储层的非易失性存储器件及其形成方法
公开(公告)号：US20070284645A1
公开(公告)日：2007-12-13
申请号：US11799685
申请日：2007-05-02
申请人： Chang-Hyun Lee , Kyu-Charn Park
发明人： Chang-Hyun Lee , Kyu-Charn Park
IPC分类号： G11C7/00
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/115 , H01L27/11526 , H01L27/11546
摘要： A non-volatile memory device includes a substrate having a first region and a second region. A first gate electrode is disposed on the first region. A multi-layered charge storage layer is interposed between the first gate electrode and the substrate, the multi-layered charge storage including a tunnel insulation, a trap insulation, and a blocking insulation layer which are sequentially stacked. A second gate electrode is placed on the substrate of the second region, the second gate electrode including a lower gate and an upper gate connected to a region of an upper surface of the lower gate. A gate insulation layer is interposed between the second gate electrode and the substrate. The first gate electrode and the upper gate of the second gate electrode comprise a same material.
摘要翻译：非易失性存储器件包括具有第一区域和第二区域的衬底。第一栅电极设置在第一区域上。在第一栅电极和基板之间插入多层电荷存储层，多层电荷存储包括依次堆叠的隧道绝缘，阱绝缘和阻挡绝缘层。第二栅极被放置在第二区域的衬底上，第二栅极包括下栅极和连接到下栅极的上表面区域的上栅极。栅极绝缘层介于第二栅电极和衬底之间。第二栅电极的第一栅电极和上栅极包括相同的材料。

58. 发明授权

US07271436B2 Flash memory devices including a pass transistor 有权
标题翻译：包括传输晶体管的闪存器件
公开(公告)号：US07271436B2
公开(公告)日：2007-09-18
申请号：US11021232
申请日：2004-12-23
申请人： Chang-Hyun Lee , Sang-Pil Sim , Seung-Keun Lee
发明人： Chang-Hyun Lee , Sang-Pil Sim , Seung-Keun Lee
IPC分类号： H01L29/76 , H01L29/788 , H01L29/94 , H01L31/00
CPC分类号： H01L27/11546 , H01L27/105 , H01L27/11526 , H01L29/6656 , H01L29/66659 , H01L29/7835
摘要： Flash memory integrated circuit devices include an integrated circuit substrate. A cell array on the integrated circuit substrate includes a plurality of cell transistors. A bit line is coupled to ones of the plurality of cell transistors and a first pass transistor is coupled to the bit line. The first pass transistor has a first diffusion structure configured to provide a breakdown voltage higher than that of a second diffusion structure. One or more second pass transistor(s) are coupled to the first pass transistor. The second pass transistor(s) have the second diffusion structure. The second diffusion structure may have a resistance smaller than a resistance of the first diffusion structure.
摘要翻译：闪存集成电路器件包括集成电路基板。集成电路基板上的单元阵列包括多个单元晶体管。位线耦合到多个单元晶体管中的一个，并且第一传输晶体管耦合到位线。第一传输晶体管具有第一扩散结构，其被配置为提供比第二扩散结构高的击穿电压。一个或多个第二传输晶体管耦合到第一传输晶体管。第二传输晶体管具有第二扩散结构。第二扩散结构可以具有小于第一扩散结构的电阻的电阻。

59. 发明授权

US07240581B2 Installation structure of brake pedal 失效
标题翻译：制动踏板的安装结构
公开(公告)号：US07240581B2
公开(公告)日：2007-07-10
申请号：US10911724
申请日：2004-08-04
申请人： Chang-Hyun Lee
发明人： Chang-Hyun Lee
IPC分类号： G05G1/14 , B60K28/10 , B60D1/28
CPC分类号： G05G1/30 , G05G1/327 , G05G1/60 , Y10T74/20528 , Y10T74/20888
摘要： An installation structure releases a brake pedal in a vehicle collision. A pedal arm has a groove coupled with a pipe. A front portion of the groove has a smaller width than the pipe. Alternatively, a pedal arm is hingedly mounted on a support member. A connector secures the pedal arm to the support member for normal operation, and permits separation of the pedal arm from the support member in response to a reward force resulting from a collision impact. The support member has a cylindrical member, and the pedal arm defines a forward facing opening, force-fit onto the cylindrical member. The opening has a width smaller than the cylindrical member. Alternatively, the connector has two support plates on a pipe of the cylindrical member, at both sides of the pedal arm. The plates have rear-facing grooves, and coupling members protruding from the pedal arm are received in the grooves.
摘要翻译：安装结构在车辆碰撞中释放制动踏板。踏板臂具有与管道连接的凹槽。槽的前部具有比管更小的宽度。或者，踏板臂铰接地安装在支撑构件上。连接器将踏板臂固定到支撑构件以进行正常操作，并且允许踏板臂与支撑构件响应于碰撞冲击产生的奖励力而分离。支撑构件具有圆柱形构件，并且踏板臂限定向前的开口，并将其压配合到圆柱形构件上。开口的宽度比圆柱形件小。或者，连接器在踏板臂的两侧在圆柱形构件的管道上具有两个支撑板。这些板具有后置凹槽，并且从踏板臂突出的联接构件容纳在凹槽中。

60. 发明申请

US20060180851A1 Non-volatile memory devices and methods of operating the same 审中-公开
标题翻译：非易失性存储器件及其操作方法
公开(公告)号：US20060180851A1
公开(公告)日：2006-08-17
申请号：US11402389
申请日：2006-04-12
申请人： Chang-Hyun Lee , Jung-Dal Choi
发明人： Chang-Hyun Lee , Jung-Dal Choi
IPC分类号： H01L29/788
CPC分类号： G11C16/12 , G11C16/14 , G11C16/26 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11526 , H01L27/11529 , H01L29/40114 , H01L29/42332 , H01L29/513 , H01L29/7782 , H01L29/792 , H01L29/7923
摘要： Non-volatile memory devices and methods of operating the same are disclosed. A non-volatile memory device includes a semiconductor substrate. A tunnel insulating layer and a gate electrode are on the semiconductor substrate. A multiple tunnel insulation layer with a plurality of layers, a charge storage insulation layer, and a multiple blocking insulation layer with a plurality of layers are sequentially stacked between the gate electrode and the tunnel insulating layer. A first diffusion region and a second diffusion region in the semiconductor substrate are adjacent to opposite respective sides of the gate electrode. When a voltage is applied to the gate electrode and the semiconductor substrate to form a voltage level difference therebetween, a minimum field in the tunnel insulation layer is stronger than a minimum field in the blocking insulation layer. A minimum field established at a blocking insulation layer can be stronger than a minimum field established at a tunnel insulation layer, and the migration probability of charges through the tunnel insulation layer can be higher than that of charges through the blocking insulation layer. Therefore, it may be possible to use lower operation voltages, obtain higher program and erase speeds, and/or obtain a greater difference between threshold values of a program threshold voltage and an erase threshold voltage. As a result, a multi-valued non-volatile memory device may be formed therefrom.
摘要翻译：公开了非易失性存储器件及其操作方法。非易失性存储器件包括半导体衬底。隧道绝缘层和栅电极位于半导体衬底上。具有多个层的多重隧道绝缘层，电荷存储绝缘层和具有多个层的多重阻挡绝缘层依次堆叠在栅电极和隧道绝缘层之间。半导体衬底中的第一扩散区域和第二扩散区域与栅电极的相对的相对侧相邻。当向栅电极和半导体衬底施加电压以形成其间的电压电平差时，隧道绝缘层中的最小场强比阻挡绝缘层中的最小场强。在阻挡绝缘层处建立的最小场强可以比在隧道绝缘层处建立的最小场强更强，并且通过隧道绝缘层的电荷的迁移概率可以高于通过阻挡绝缘层的电荷的迁移概率。因此，可以使用较低的操作电压，获得更高的编程和擦除速度，和/或获得程序阈值电压和擦除阈值电压的阈值之间的较大差异。结果，可以从其形成多值非易失性存储器件。

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