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51. 发明申请

US20110303915A1 Compressively Stressed FET Device Structures 有权
标题翻译：压缩式FET器件结构
公开(公告)号：US20110303915A1
公开(公告)日：2011-12-15
申请号：US12813311
申请日：2010-06-10
申请人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
IPC分类号： H01L27/088 , H01L21/8234
CPC分类号： H01L21/823431 , H01L21/823412 , H01L21/823807 , H01L21/823821 , H01L29/66795 , H01L29/7843 , H01L29/7846 , H01L29/785
摘要： Methods for fabricating FET device structures are disclosed. The methods include receiving a fin of a Si based material, and converting a region of the fin into an oxide element. The oxide element exerts pressure onto the fin where a Fin-FET device is fabricated. The exerted pressure induces compressive stress in the device channel of the Fin-FET device. The methods also include receiving a rectangular member of a Si based material and converting a region of the member into an oxide element. The methods further include patterning the member that N fins are formed in parallel, while being abutted by the oxide element, which exerts pressure onto the N fins. Fin-FET devices are fabricated in the compressed fins, which results in compressively stressed device channels. FET devices structures are also disclosed. An FET devices structure has a Fin-FET device with a fin of a Si based material. An oxide element is abutting the fin and exerts pressure onto the fin. The Fin-FET device channel is compressively stressed due to the pressure on the fin. A further FET device structure has Fin-FET devices in a row each having fins. An oxide element extending perpendicularly to the row of fins is abutting the fins and exerts pressure onto the fins. Device channels of the Fin-FET devices are compressively stressed due to the pressure on the fins.
摘要翻译：公开了用于制造FET器件结构的方法。所述方法包括接收Si基材料的翅片，以及将鳍片的区域转换为氧化物元件。氧化物元件在制造Fin-FET器件的鳍片上施加压力。施加的压力在Fin-FET器件的器件沟道中引起压应力。所述方法还包括接收Si基材料的矩形构件并将所述构件的区域转换为氧化物元件。所述方法进一步包括在与N个翅片施加压力的同时被N型翅片平行地形成的构件图案化。 Fin-FET器件制造在压缩鳍片中，这导致压缩应力器件通道。还公开了FET器件结构。 FET器件结构具有具有Si基材料的翅片的Fin-FET器件。氧化物元件邻接翅片并对翅片施加压力。 Fin-FET器件通道由于鳍上的压力而受到压缩应力。另外的FET器件结构具有各自具有鳍片的Fin-FET器件。垂直于翅片排延伸的氧化物元件邻接散热片并对翅片施加压力。 Fin-FET器件的器件通道由于鳍片上的压力而受到压缩应力。

52. 发明授权

US09461169B2 Device and method for fabricating thin semiconductor channel and buried strain memorization layer 有权
标题翻译：用于制造薄半导体沟道和埋层应变记忆层的器件和方法
公开(公告)号：US09461169B2
公开(公告)日：2016-10-04
申请号：US12789792
申请日：2010-05-28
申请人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
IPC分类号： H01L21/00 , H01L21/84 , H01L29/78 , H01L21/02 , H01L21/265
CPC分类号： H01L29/7847 , H01L21/02532 , H01L21/02664 , H01L21/26506 , H01L29/7841 , H01L29/785
摘要： A device and method for inducing stress in a semiconductor layer includes providing a substrate having a dielectric layer formed between a first semiconductor layer and a second semiconductor layer and processing the second semiconductor layer to form an amorphized material. A stress layer is deposited on the first semiconductor layer. The wafer is annealed to memorize stress in the second semiconductor layer by recrystallizing the amorphized material.
摘要翻译：用于在半导体层中诱发应力的装置和方法包括提供具有形成在第一半导体层和第二半导体层之间的介电层的衬底，并且处理第二半导体层以形成非晶化材料。应力层沉积在第一半导体层上。将晶片退火以通过使非晶化材料重结晶来在第二半导体层中记忆应力。

53. 发明授权

US08552487B2 SOI trench DRAM structure with backside strap 有权
标题翻译：具有背面带的SOI沟槽DRAM结构
公开(公告)号：US08552487B2
公开(公告)日：2013-10-08
申请号：US13568601
申请日：2012-08-07
申请人： Bruce B. Doris , Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
发明人： Bruce B. Doris , Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
IPC分类号： H01L27/108
CPC分类号： H01L27/1203 , H01L27/10829 , H01L27/10867
摘要： A semiconductor structure includes a SOI substrate having a top silicon layer overlying an insulation layer, which overlies a bottom silicon layer; a capacitor disposed at least partially in the insulation layer; a device disposed at least partially on the top silicon layer, which device is coupled to a doped portion of the top silicon layer; a backside strap of first epitaxially-deposited material, at least a first portion of the backside strap underlying the doped portion, the backside strap being coupled to the doped portion of the top silicon layer at a first end of the backside strap and to the capacitor at a second end of the backside strap; and second epitaxially-deposited material that at least partially overlies the doped portion of the top silicon layer, the second epitaxially-deposited material further at least partially overlying the first portion.
摘要翻译：半导体结构包括：SOI衬底，其具有覆盖在底部硅层上的绝缘层的顶部硅层; 至少部分地设置在绝缘层中的电容器; 至少部分地设置在顶部硅层上的器件，该器件耦合到顶部硅层的掺杂部分; 第一外延沉积材料的背面带，位于掺杂部分下面的背侧带的至少第一部分，背面带在背面带的第一端处耦合到顶部硅层的掺杂部分，并且连接到电容器在背面带的第二端; 以及第二外延沉积材料，其至少部分地覆盖在顶部硅层的掺杂部分上，第二外延沉积材料进一步至少部分地覆盖在第一部分上。

54. 发明授权

US08343819B2 Extremely thin semiconductor-on-insulator (ETSOI) integrated circuit with on-chip resistors and method of forming the same 有权
标题翻译：具有片上电阻的非常薄的绝缘体上半导体（ETSOI）集成电路及其形成方法
公开(公告)号：US08343819B2
公开(公告)日：2013-01-01
申请号：US12687273
申请日：2010-01-14
申请人： Bruce B. Doris , Kangguo Cheng , Ali Khakifirooz , Ghavam G. Shahidi
发明人： Bruce B. Doris , Kangguo Cheng , Ali Khakifirooz , Ghavam G. Shahidi
IPC分类号： H01L21/00
CPC分类号： H01L27/1214 , H01L21/84 , H01L27/1203 , H01L27/13
摘要： An electrical device is provided that in one embodiment includes a semiconductor-on-insulator (SOI) substrate having a semiconductor layer with a thickness of less than 10 nm. A semiconductor device having a raised source region and a raised drain region of a single crystal semiconductor material of a first conductivity is present on a first surface of the semiconductor layer. A resistor composed of the single crystal semiconductor material of the first conductivity is present on a second surface of the semiconductor layer. A method of forming the aforementioned electrical device is also provided.
摘要翻译：提供了一种电气装置，其在一个实施例中包括具有厚度小于10nm的半导体层的绝缘体上半导体（SOI）基板。在半导体层的第一表面上存在具有第一导电性的单晶半导体材料的升高的源极区域和升高的漏极区域的半导体器件。由第一导电性的单晶半导体材料构成的电阻器存在于半导体层的第二表面上。还提供了形成上述电气装置的方法。

55. 发明申请

US20120299075A1 SOI Trench Dram Structure With Backside Strap 有权
标题翻译：具有背面表带的SOI沟槽结构
公开(公告)号：US20120299075A1
公开(公告)日：2012-11-29
申请号：US13568601
申请日：2012-08-07
申请人： Bruce B. Doris , Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
发明人： Bruce B. Doris , Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
IPC分类号： H01L27/108
CPC分类号： H01L27/1203 , H01L27/10829 , H01L27/10867
摘要： In one exemplary embodiment, a semiconductor structure including: a SOI substrate having a top silicon layer overlying an insulation layer, the insulation layer overlies a bottom silicon layer; a capacitor disposed at least partially in the insulation layer; a device disposed at least partially on the top silicon layer, the device is coupled to a doped portion of the top silicon layer; a backside strap of first epitaxially-deposited material, at least a first portion of the backside strap underlies the doped portion, the backside strap is coupled to the doped portion of the top silicon layer at a first end of the backside strap and to the capacitor at a second end of the backside strap; and second epitaxially-deposited material that at least partially overlies the doped portion of the top silicon layer, the second epitaxially-deposited material further at least partially overlies the first portion.
摘要翻译：在一个示例性实施例中，一种半导体结构，包括：具有覆盖绝缘层的顶部硅层的SOI衬底，所述绝缘层覆盖在底部硅层上; 至少部分地设置在绝缘层中的电容器; 至少部分地设置在顶部硅层上的器件，该器件耦合到顶部硅层的掺杂部分; 第一外延沉积材料的背面带，背面带的至少第一部分位于掺杂部分的下面，背侧带在背面带的第一端和电容器处耦合到顶部硅层的掺杂部分在背面带的第二端; 以及至少部分地覆盖在顶部硅层的掺杂部分上的第二外延沉积材料，第二外延沉积材料还至少部分地覆盖在第一部分上。

56. 发明授权

US08318568B2 Tunnel field effect transistor 有权
标题翻译：隧道场效应晶体管
公开(公告)号：US08318568B2
公开(公告)日：2012-11-27
申请号：US12760287
申请日：2010-04-14
申请人： Bruce B. Doris , Kangguo Cheng , Wilfried E. Haensch , Ali Khakifirooz , Isaac Lauer , Ghavam G. Shahidi
发明人： Bruce B. Doris , Kangguo Cheng , Wilfried E. Haensch , Ali Khakifirooz , Isaac Lauer , Ghavam G. Shahidi
IPC分类号： H01L21/336
CPC分类号： H01L21/26586 , H01L29/665 , H01L29/66636 , H01L29/66659 , H01L29/78
摘要： A method for fabricating an FET device characterized as being a tunnel FET (TFET) device is disclosed. The method includes processing a gate-stack, and processing the adjoining source and drain junctions, which are of a first conductivity type. A hardmask is formed covering the gate-stack and the junctions. A tilted angle ion implantation is performed which is received by a first portion of the hardmask, and it is not received by a second portion of the hardmask due to the shadowing of the gate-stack. The implanted portion of the hardmask is removed and one of the junctions is exposed. The junction is etched away, and a new junction, typically in-situ doped to a second conductivity type, is epitaxially grown into its place. A device characterized as being an asymmetrical TFET is also disclosed. The source and drain junctions of the TFET are of different conductivity types, and the TFET also includes spacer formations in a manner that the spacer formation on one side of the gate-stack is thinner than on the other side of the gate-stack.
摘要翻译：公开了一种用于制造FET器件的方法，其特征在于是隧道FET（TFET）器件。该方法包括处理栅极堆叠，以及处理第一导电类型的邻接的源极和漏极结。形成覆盖栅极堆叠和结的硬掩模。执行由硬掩模的第一部分接收的倾斜角度离子注入，并且由于栅极堆叠的阴影而不被硬掩模的第二部分接收。去除硬掩模的注入部分，并露出其中一个接头。该结被蚀刻掉，并且通常原位掺杂到第二导电类型的新结，外延生长到其位置。还公开了一种特征为不对称TFET的器件。 TFET的源极和漏极结具有不同的导电类型，并且TFET还包括间隔物结构，使得栅极堆叠的一侧上的间隔物形成比栅极堆叠的另一侧更薄。

57. 发明申请

US20120286329A1 SOI FET with embedded stressor block 审中-公开
标题翻译：具有嵌入式应力块的SOI FET
公开(公告)号：US20120286329A1
公开(公告)日：2012-11-15
申请号：US13106900
申请日：2011-05-13
申请人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
IPC分类号： H01L29/06 , H01L21/336
CPC分类号： H01L29/66772 , H01L29/7848 , H01L29/78654
摘要： A method and a structure are disclosed relating to strained body UTSOI FET devices. The method includes forming voids in the source/drain regions that penetrate down into the substrate below the insulating layer. The voids are epitaxially filled with a semiconductor material of a differing lattice constant than the one of the SOI layer, thus becoming a stressor block, and imparts a strain onto the FET device body.
摘要翻译：公开了与应变体UTSOI FET器件有关的方法和结构。该方法包括在源极/漏极区域中形成穿透绝缘层下方的衬底中的空隙。空隙被外延填充有与SOI层不同的晶格常数的半导体材料，因此成为应力块，并且在FET器件本体上施加应变。

58. 发明申请

US20120276695A1 Strained thin body CMOS with Si:C and SiGe stressor 审中-公开
标题翻译：应变薄体CMOS与Si：C和SiGe应力
公开(公告)号：US20120276695A1
公开(公告)日：2012-11-01
申请号：US13098352
申请日：2011-04-29
申请人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
IPC分类号： H01L21/8238
CPC分类号： H01L27/1211 , H01L21/823807 , H01L21/823814 , H01L21/823821 , H01L21/845
摘要： A method is disclosed which is characterized as being process integration of raised source/drain and strained body for ultra thin planar and FinFET CMOS devices. NFET and PFET devices have their source/drain raised by selective epitaxy with in-situ p-type doped SiGe for the PFET device, and in-situ n-type doped Si:C for the NFET device. Such raised source/drains offer low parasitic resistance and they impart a strain onto the device bodies of the correct sign for respective carrier, electron or hole, mobility enhancement.
摘要翻译：公开了一种方法，其特征在于用于超薄平面和FinFET CMOS器件的凸起源极/漏极和应变体的处理集成。 NFET和PFET器件通过用于PFET器件的原位p型掺杂SiGe的选择性外延以及用于NFET器件的原位n型掺杂Si：C来提高其源极/漏极。这种升高的源极/漏极提供低的寄生电阻，并且它们对于相应的载流子，电子或空穴，迁移率增强赋予了正确符号的器件体上的应变。

59. 发明申请

US20120267722A1 Compressively Stressed FET Device Structures 审中-公开
标题翻译：压缩式FET器件结构
公开(公告)号：US20120267722A1
公开(公告)日：2012-10-25
申请号：US13540801
申请日：2012-07-03
申请人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
IPC分类号： H01L27/088
CPC分类号： H01L21/823431 , H01L21/823412 , H01L21/823807 , H01L21/823821 , H01L29/66795 , H01L29/7843 , H01L29/7846 , H01L29/785
摘要： An FET device structure has a Fin-FET device with a fin of a Si based material. An oxide element is abutting the fin and exerts pressure onto the fin. The Fin-FET device channel is compressively stressed due to the pressure on the fin. A further FET device structure has Fin-FET devices in a row. An oxide element extending perpendicularly to the row of fins is abutting the fins and exerts pressure onto the fins. Device channels of the Fin-FET devices are compressively stressed due to the pressure on the fins.
摘要翻译： FET器件结构具有具有Si基材料的翅片的Fin-FET器件。氧化物元件邻接翅片并对翅片施加压力。 Fin-FET器件通道由于鳍上的压力而受到压缩应力。另外的FET器件结构具有Fin-FET器件。垂直于翅片排延伸的氧化物元件邻接散热片并对翅片施加压力。 Fin-FET器件的器件通道由于鳍片上的压力而受到压缩应力。

60. 发明申请

US20120012933A1 FORMATION METHOD AND STRUCTURE FOR A WELL-CONTROLLED METALLIC SOURCE/DRAIN SEMICONDUCTOR DEVICE 有权
标题翻译：一种良好控制的金属源/漏极半导体器件的形成方法和结构
公开(公告)号：US20120012933A1
公开(公告)日：2012-01-19
申请号：US12838844
申请日：2010-07-19
申请人： KANGGUO CHENG , Bruce B. Doris , Ali Khakifirooz , Ghavam G. Shahidi
发明人： KANGGUO CHENG , Bruce B. Doris , Ali Khakifirooz , Ghavam G. Shahidi
IPC分类号： H01L29/78 , H01L21/84
CPC分类号： H01L29/7839 , H01L29/665 , H01L29/6653 , H01L29/66772 , H01L29/66795
摘要： A device and method for forming a semiconductor device include growing a raised semiconductor region on a channel layer adjacent to a gate structure. A space is formed between the raised semiconductor region and the gate structure. A metal layer is deposited on at least the raised semiconductor region. The raised semiconductor region is silicided to form a silicide into the channel layer which extends deeper into the channel layer at a position corresponding to the space.
摘要翻译：用于形成半导体器件的器件和方法包括在与栅极结构相邻的沟道层上生长凸起的半导体区域。在凸起的半导体区域和栅极结构之间形成空间。在至少凸起的半导体区域上沉积金属层。凸起的半导体区域被硅化以在通道层中形成硅化物，该沟道层在对应于空间的位置处更深地延伸到沟道层中。

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