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    • 52. 发明申请
    • Light emissive display device
    • 发光显示装置
    • US20050116615A1
    • 2005-06-02
    • US10953974
    • 2004-09-29
    • Shoichiro MatsumotoKazunobu Mameno
    • Shoichiro MatsumotoKazunobu Mameno
    • H01J1/62H01J63/04H01L27/32
    • H01L27/322H01L27/3213H01L27/3216H01L27/3218H01L27/326
    • In a display device using, for example, an organic EL element as a light emissive element, a single pixel is formed of subpixels of four colors, R, G, B, and W, arranged in two rows and two columns. Each pixel is substantially quadrangular in shape, and at least one of the subpixels in the pixel has an area different from the areas of the other subpixels. The subpixels of the colors horizontally adjoining in the same row have the same height, and the subpixels of the colors vertically adjoining in the same column have the same width. Even when the area ratio of the subpixels is varied by changing the position of the intersecting point of divisional lines dividing a pixel into four subpixels, the design can easily be modified by satisfying the above relationship, and a display device with a high luminance and a long life can easily be obtained with any area ratio.
    • 在使用例如有机EL元件作为发光元件的显示装置中,单个像素由排列成两列和两列的四种颜色的子像素R,G,B和W形成。 每个像素的形状基本上是四边形,并且像素中的至少一个子像素具有与其他子像素的区域不同的面积。 在同一行中水平相邻的颜色的子像素具有相同的高度,并且在同一列中垂直相邻的颜色的子像素具有相同的宽度。 即使通过改变将像素分割为四个子像素的分割线的交点的位置来改变子像素的面积比,也可以通过满足上述关系来容易地改变设计,并且可以容易地通过满足上述关系来修改该设计,以及具有高亮度和 任何面积比都可以很容易地获得长寿命。
    • 55. 发明授权
    • Voltage generation circuit and display unit comprising voltage generation circuit
    • 电压产生电路和显示单元包括电压产生电路
    • US06498527B2
    • 2002-12-24
    • US09745995
    • 2000-12-26
    • Shoichiro Matsumoto
    • Shoichiro Matsumoto
    • G05F302
    • H01L27/0629
    • A voltage generation circuit including a capacitor, an n-channel MOS transistor, a p-channel MOS transistor and the like. The n-channel transistor has a source terminal connected to a node and a drain terminal employed as an output terminal for a negative voltage, the p-channel MOS transistor has a source terminal connected to the aforementioned node and a drain terminal employed as a ground terminal, gate terminals of the n-channel MOS transistor and the p-channel transistor are connected in common, and clock signals inverted in phase to each other are applied to the common node and a first terminal of the capacitor.
    • 包括电容器,n沟道MOS晶体管,p沟道MOS晶体管等的电压产生电路。 n沟道晶体管具有连接到节点的源极端子和用作负电压的输出端子的漏极端子,p沟道MOS晶体管具有连接到上述节点的源极端子和用作接地的漏极端子 端子,n沟道MOS晶体管和p沟道晶体管的栅极端子共同连接,并且相位反相的时钟信号彼此相加,施加到公共节点和电容器的第一端子。