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51. 发明申请

US20130235688A1 LOOK-UP TABLE CIRCUIT 有权
标题翻译：查看表电路
公开(公告)号：US20130235688A1
公开(公告)日：2013-09-12
申请号：US13606041
申请日：2012-09-07
申请人： Masato ODA , Shinichi Yasuda
发明人： Masato ODA , Shinichi Yasuda
IPC分类号： G11C5/14
CPC分类号： G11C5/148
摘要： One embodiment provides a look-up table circuit, including: 2i memories, a half of which constituting a first memory group, the other half of which constituting a second memory group; first to i-th input terminals to which first to i-th input signals are input, respectively; a first output terminal; a switch group that selectively connects one of the memories to the first output terminal according to the first to i-th input signals; a first power-off switch that shuts off power supply to the first memory group in response to one of the first to i-th input signals; and a second power-off switch that shuts off power supply to the second memory group in response to the one of the first to i-th input signals.
摘要翻译：一个实施例提供了一种查找表电路，包括：2i个存储器，其中一半构成第一存储器组，另一半构成第二存储器组; 分别输入第一至第i输入信号的第一至第i输入端子; 第一输出端子; 开关组，根据第一至第i输入信号有选择地将一个存储器连接到第一输出端; 第一断电开关，其响应于第一至第i输入信号中的一个切断对第一存储器组的电源; 以及第二断电开关，其响应于所述第一至第i输入信号之一而切断对所述第二存储器组的电源。

52. 发明授权

US08456892B2 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US08456892B2
公开(公告)日：2013-06-04
申请号：US13223930
申请日：2011-09-01
申请人： Shinichi Yasuda
发明人： Shinichi Yasuda
IPC分类号： G11C11/00 , G11C7/02
CPC分类号： G11C13/003 , G11C13/0004 , G11C13/0007 , G11C13/0069 , G11C2213/74 , G11C2213/79
摘要： According to one embodiment, a semiconductor integrated circuit includes first and second resistance change type memory element and first and second switches. The first resistance change type memory element includes a first terminal connected to a first power supply and a second terminal connected to a first node. The second resistance change type memory element includes a third terminal connected to the first node and a fourth terminal connected to a second power supply. The first switch includes one end of a first current path connected to a first program power supply and the other end of the first current path connected to the first node. The second switch includes one end of a second current path connected to the first node and the other end of the second current path connected to a second program power supply.
摘要翻译：根据一个实施例，半导体集成电路包括第一和第二电阻变化型存储元件以及第一和第二开关。第一电阻变化型存储元件包括连接到第一电源的第一端子和连接到第一节点的第二端子。第二电阻变化型存储元件包括连接到第一节点的第三端子和连接到第二电源的第四端子。第一开关包括连接到第一程序电源的第一电流通路的一端和连接到第一节点的第一电流通路的另一端。第二开关包括连接到第一节点的第二电流路径的一端和连接到第二节目电源的第二电流路径的另一端。

53. 发明申请

US20130055189A1 METHOD FOR IMPLEMENTING CIRCUIT DESIGN FOR INTEGRATED CIRCUIT AND COMPUTER READABLE MEDIUM 失效
标题翻译：用于集成电路和计算机可读介质实现电路设计的方法
公开(公告)号：US20130055189A1
公开(公告)日：2013-02-28
申请号：US13561483
申请日：2012-07-30
申请人： Kumiko Nomura , Shinichi Yasuda , Shinobu Fujita , Keiko Abe , Tetsufumi Tanamoto , Kazutaka Ikegami , Masato Oda
发明人： Kumiko Nomura , Shinichi Yasuda , Shinobu Fujita , Keiko Abe , Tetsufumi Tanamoto , Kazutaka Ikegami , Masato Oda
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F17/5031 , G06F17/5054 , G06F17/5081
摘要： In one embodiment, a method for implementing a circuit design for an integrated circuit includes: (a) obtaining a first wiring to satisfy a given operating frequency; (b) calculating a maximum bypass wiring length based on the given operating frequency and a critical path of the first wiring; (c) obtaining a second wiring by bypassing the first wiring using wires other than wires of the first wiring in a first wiring group, wherein wiring of the integrated circuit is categorized into a plurality of wiring groups, and the first wiring is included in the first wiring group of the categorized wiring groups; and (d) replacing the first wiring with the second wiring, if a difference between the second wiring and the first wiring is not larger than the maximum bypass wiring length, and not replacing the first wiring if said difference is larger than the maximum bypass wiring length.
摘要翻译：在一个实施例中，一种用于实现集成电路的电路设计的方法包括：（a）获得第一布线以满足给定的工作频率; （b）基于给定的工作频率和第一布线的关键路径计算最大旁路布线长度; （c）通过在第一布线组中使用不同于第一布线的布线的旁路第一布线来获得第二布线，其中集成电路的布线被分类为多个布线组，并且第一布线包括在第一布线中分类布线组的第一接线组; 以及（d）如果所述第二布线和所述第一布线之间的差不大于所述最大旁路布线长度，则用所述第二布线代替所述第一布线，并且如果所述差大于所述最大旁路布线，则不更换所述第一布线长度。

54. 发明申请

US20130027093A1 PLL 失效
公开(公告)号：US20130027093A1
公开(公告)日：2013-01-31
申请号：US13461101
申请日：2012-05-01
申请人： Hiroki NOGUCHI , Keiko Abe , Shinichi Yasuda , Shinobu Fujita
发明人： Hiroki NOGUCHI , Keiko Abe , Shinichi Yasuda , Shinobu Fujita
IPC分类号： H03L7/08 , H03B19/00
CPC分类号： H03L7/14 , H03L2207/18
摘要： One embodiment provides a phase-locked loop (PLL), in which a sequencer controls a loop filter such that, when a signal indicating turning-off of a power supply of the PLL is input thereto, or when a signal indicating turning-on of the power supply of the PLL is input thereto, a resistance value of a first resistance change device in the loop filter is a first resistance value, and that, after the PLL is stabilized, the resistance value of the first resistance change device is a second resistance value which is higher than the first resistance value.
摘要翻译：一个实施例提供了一种锁相环（PLL），其中定序器控制环路滤波器，使得当指示关闭PLL的电源的信号被输入时，或者当指示接通 PLL的电源被输入到其中，环路滤波器中的第一电阻改变装置的电阻值是第一电阻值，并且在PLL稳定之后，第一电阻改变装置的电阻值是第二电阻值电阻值高于第一电阻值。

55. 发明申请

US20120235705A1 NONVOLATILE CONFIGURATION MEMORY 失效
标题翻译：非易失性配置存储器
公开(公告)号：US20120235705A1
公开(公告)日：2012-09-20
申请号：US13419205
申请日：2012-03-13
申请人： Keiko Abe , Shinichi Yasuda , Kumiko Nomura , Shinobu Fujita
发明人： Keiko Abe , Shinichi Yasuda , Kumiko Nomura , Shinobu Fujita
IPC分类号： H03K19/177 , G11C16/04
CPC分类号： H03K19/1776 , G11C11/412 , G11C14/0063
摘要： According to one embodiment, a memory includes a first P-channel FET having a gate connected to a second output node, a source applied to a first potential, and a drain connected to the first output node, a second P-channel FET having a gate connected to a first output node, a source applied to the first potential, and a drain connected to the second output node, a first N-channel FET having a control gate connected to a first word line, a source applied to a second potential lower than the first potential, a drain connected to the first output node, and a threshold changed by data in a storage layer, and a second N-channel FET having a control gate connected to a second word line, a source applied to the second potential, a drain connected to the second output node, and a threshold changed by data in a storage layer.
摘要翻译：根据一个实施例，存储器包括：第一P沟道FET，其具有连接到第二输出节点的栅极，施加到第一电位的源极和连接到第一输出节点的漏极;第二P沟道FET，其具有连接到第一输出节点的源极，施加到第一电位的源极和连接到第二输出节点的漏极，具有连接到第一字线的控制栅极的第一N沟道FET，施加到第二电位的源极低于第一电位的漏极，连接到第一输出节点的漏极和由存储层中的数据改变的阈值，以及具有连接到第二字线的控制栅极的第二N沟道FET，施加到第二电压的源极电位，连接到第二输出节点的漏极以及由存储层中的数据改变的阈值。

56. 发明申请

US20110309881A1 THREE-DIMENSIONAL SEMICONDUCTOR INTEGRATED CIRCUIT 有权
标题翻译：三维半导体集成电路
公开(公告)号：US20110309881A1
公开(公告)日：2011-12-22
申请号：US13223898
申请日：2011-09-01
申请人： Shinichi Yasuda , Keiko Abe , Shinobu Fujita
发明人： Shinichi Yasuda , Keiko Abe , Shinobu Fujita
IPC分类号： H01L25/065
CPC分类号： H03K19/20 , G11C5/02 , H01L23/642 , H01L24/48 , H01L24/49 , H01L25/0657 , H01L25/18 , H01L2224/48091 , H01L2224/49113 , H01L2225/06513 , H01L2225/06527 , H01L2225/06531 , H01L2225/06541 , H01L2225/06565 , H01L2225/06568 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01023 , H01L2924/01028 , H01L2924/01033 , H01L2924/13091 , H01L2924/14 , H01L2924/19041 , H01L2924/19104 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要： According to one embodiment, a three-dimensional semiconductor integrated circuit includes first, second and third chips which are stacked, and a common conductor which connects the first, second and third chips from one another. The first chip includes a first multi-leveling circuit, the second chip includes a second multi-leveling circuit, and the third chip includes a decoding circuit. The first multi-leveling circuit includes a first inverter to which binary first data is input and which outputs one of first and second potentials and a first capacitor which is connected between an output terminal of the first inverter and the common conductor. The second multi-leveling circuit includes a second inverter to which binary second data is input and which outputs one of third and fourth potentials and a second capacitor which is connected between an output terminal of the second inverter and the common conductor.
摘要翻译：根据一个实施例，三维半导体集成电路包括堆叠的第一，第二和第三芯片，以及将第一，第二和第三芯片彼此连接的公共导体。第一芯片包括第一多电平电路，第二芯片包括第二多电平电路，第三芯片包括解码电路。第一多电平电路包括输入二进制第一数据并输出第一和第二电位之一的第一反相器和连接在第一反相器的输出端和公共导体之间的第一电容器。第二多电平电路包括输入二进制第二数据并输出第三和第四电位之一的第二反相器和连接在第二反相器的输出端和公共导体之间的第二电容器。

57. 发明授权

US07949984B2 Method and apparatus for designing a three-dimensional integrated circuit 有权
标题翻译：用于设计三维集成电路的方法和装置
公开(公告)号：US07949984B2
公开(公告)日：2011-05-24
申请号：US12047547
申请日：2008-03-13
申请人： Tetsufumi Tanamoto , Shinichi Yasuda , Shinobu Fujita
发明人： Tetsufumi Tanamoto , Shinichi Yasuda , Shinobu Fujita
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F17/5068
摘要： A method of designing a three-dimensional integrated circuit includes dividing two-dimensional layout data of a circuit formed on a semiconductor substrate into a plurality of layout block data in order to re-arrange in different layers, generating layout block data reversing one of the layout block data of two folded layers arranged vertically adjacent to each other, alternately arranging the reversed layout block data and non-reverse block layout data to form a plurality of layers vertically overlapped, selecting at least one from interconnects included in a plurality of layout block data of the circuit and ranging over plural layers so as to be mutually and functionally collected together with respect to at least one of time delay, interconnect length and block configuration, and re-arranging the selected interconnect using a via connecting an upper layer and an under layer of the folded interconnect.
摘要翻译：一种设计三维集成电路的方法包括将形成在半导体衬底上的电路的二维布局数据划分成多个布局块数据，以便重新排列在不同的层中，生成布局块数据，交替布置反向布局块数据和非反向块布局数据以形成垂直重叠的多个层的两个折叠层的布局块数据，从包括在多个布局块中的互连中选择至少一个层电路的数据并且跨越多个层，以便相对于时间延迟，互连长度和块配置中的至少一个而相互和功能地收集在一起，并且使用连接上层和第二层的通孔重新布置所选择的互连折叠互连的下层。

58. 发明授权

US07694645B2 Rotary atomization head painting device 失效
标题翻译：旋转喷雾头喷涂装置
公开(公告)号：US07694645B2
公开(公告)日：2010-04-13
申请号：US10568413
申请日：2005-02-09
申请人： Shinichi Yasuda , Yukinori Miyamoto
发明人： Shinichi Yasuda , Yukinori Miyamoto
IPC分类号： B05C5/02
CPC分类号： B05B5/0415 , B05B5/0422 , B05B12/08 , B05B12/149 , B05B13/0452
摘要： An air source (11) is connected to an air motor (3) through an electropneumatic converter (12) which is connected to a rotational controller (13). Upon changing settings in a target rotational speed (N0) or paint discharge rate (Q0), in order to supply a necessary air pressure for rotationally driving the air motor (3) in a steady state with new setting conditions, the rotation controller (13) selects a steady value (is) from a rotational data selection processing table, and outputs to the electropneumatic converter (12) the newly selected steady value (is) as an input current value (i). By so doing, the rotational speed of the air motor (3) is quickly controlled toward the changed target rotational speed (N0).
摘要翻译：空气源（11）通过连接到旋转控制器（13）的电动气动转换器（12）连接到气动马达（3）。在改变目标转速（N0）或油漆喷射速度（Q0）的设定值时，为了在新的设定条件下稳定地提供用于旋转地驱动气动马达（3）的空气压力，旋转控制器）从旋转数据选择处理表中选择稳定值（is），并将新选择的稳定值（is）输出到电动气压转换器（12）作为输入电流值（i）。通过这样做，气动马达（3）的旋转速度被快速地控制到改变的目标转速（N0）。

59. 发明申请

US20090327379A1 RANDOM NUMBER GENERATING DEVICE 有权
标题翻译：随机数生成装置
公开(公告)号：US20090327379A1
公开(公告)日：2009-12-31
申请号：US12130567
申请日：2008-05-30
申请人： Mari Matsumoto , Ryuji Ohba , Shinichi Yasuda , Shinobu Fujita
发明人： Mari Matsumoto , Ryuji Ohba , Shinichi Yasuda , Shinobu Fujita
IPC分类号： G06F7/58
CPC分类号： G06F7/588 , H03K3/84
摘要： A random number generating device includes: a pulse voltage generator configured to generate a pulse voltage having an amplitude of 26 mV or more; a random noise generating element including source and drain regions formed at a distance from each other on a semiconductor substrate, a tunnel insulating film formed on a portion of the semiconductor substrate located between the source region and the drain region, and a gate electrode formed above the tunnel insulating film and to which the pulse voltage is applied, the random noise generating element configured to generate a random noise contained in a current flowing between the source region and the drain region; and a random number generating unit configured to generate a random number signal based on the random noise.
摘要翻译：随机数生成装置包括：脉冲电压发生器，被配置为产生具有26mV或更大幅度的脉冲电压; 包括形成在半导体衬底上彼此间隔一定距离的源极和漏极区域的随机噪声产生元件，形成在位于源极区域和漏极区域之间的半导体衬底的一部分上的隧道绝缘膜以及形成在栅极电极上的栅电极隧道绝缘膜，并且施加脉冲电压，所述随机噪声产生元件被配置为产生包含在源极区域和漏极区域之间的电流中的随机噪声; 以及随机数生成单元，被配置为基于随机噪声生成随机数信号。

60. 发明申请

US20090108896A1 Semiconductor Integrated Circuit Apparatus 失效
标题翻译：半导体集成电路设备
公开(公告)号：US20090108896A1
公开(公告)日：2009-04-30
申请号：US11859878
申请日：2007-09-24
申请人： Shinichi Yasuda , Keiko Abe
发明人： Shinichi Yasuda , Keiko Abe
IPC分类号： H03K3/289
CPC分类号： H03K3/0375
摘要： It is made possible to provide a flip-flop circuit capable of implementing the error correction function with a small area increase as far as possible and a pipeline system using such a flip-flop circuit. A flip-flop circuit includes: a flip-flop configured to operate based on a rising edge or a falling edge of a first clock signal; a decision circuit configured to compare an input of the flip-flop with an output thereof and output a request signal when the input of the flip-flop is different from the output thereof; and a control circuit configured to receive a second clock signal from outside and generate the first clock signal and a confirmation signal. When the request signal is sent from the decision circuit after the flip-flop has been activated, the control circuit inverts the first clock signal, sends the confirmation to the decision circuit, and makes the decision circuit cancel the request signal.
摘要翻译：可以提供一种能够尽可能地实现小面积增加的误差校正功能的触发器电路和使用这种触发器电路的流水线系统。触发器电路包括：触发器，被配置为基于第一时钟信号的上升沿或下降沿进行操作; 判定电路，被配置为当触发器的输入与其输出不同时，将触发器的输入与其输出进行比较并输出请求信号; 以及控制电路，被配置为从外部接收第二时钟信号并产生第一时钟信号和确认信号。当在触发器被激活之后请求信号从判决电路发送时，控制电路使第一时钟信号反相，将确认发送到判定电路，并使判定电路取消请求信号。

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