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    • 51. 发明授权
    • Linear full-rate phase detector and clock and data recovery circuit
    • 线性全速率相位检测器和时钟和数据恢复电路
    • US06909852B2
    • 2005-06-21
    • US09784419
    • 2001-02-15
    • Jun Cao
    • Jun Cao
    • H03K19/21H03L7/087H03L7/14H04B10/12H04B10/158H04L7/033H04L25/06H04B10/00
    • H04L7/033H03K19/215H03L7/087H03L7/14H04B10/25H04L25/063
    • Method and apparatus for recovering a clock and data from a data signal. One method of the invention includes receiving the data signal having a first data rate and receiving a clock signal having a first clock frequency, and alternating between a first level and a second level. The data signal is stored when the clock signal alternates from the first level to the second level, and the stored data signal is provided as a first signal a first amount of time later. The first signal is stored when the clock signal alternates from the first level to the second level, and the stored first signal is provided as a second signal a second amount of time later. A third signal is provided by delaying the first signal for a third amount of time. The third signal is stored when the clock signal alternates from the second level to the first level, and the stored third signal is provided as a fourth signal a fourth amount of time later. A fifth signal is provided by delaying the data signal a fifth amount of time. An error signal is generated by taking the exclusive-OR of the first and fifth signals; and a reference signal is generated by taking the exclusive-OR of the second and fourth signals. The first data rate is equal to the first clock frequency.
    • 从数据信号中恢复时钟和数据的方法和装置。 本发明的一种方法包括接收具有第一数据速率的数据信号并接收具有第一时钟频率的时钟信号,并且在第一电平和第二电平之间交替。 当时钟信号从第一电平交替到第二电平时,存储数据信号,并且将所存储的数据信号作为第一信号提供第一时间量。 当时钟信号从第一电平交替到第二电平时,存储第一信号,并且将所存储的第一信号作为第二信号提供第二数量的时间。 通过将第一信号延迟第三个时间量来提供第三信号。 当时钟信号从第二电平交替到第一电平时,第三信号被存储,并且存储的第三信号作为第四信号提供第四个时间。 通过将数据信号延迟第五时间来提供第五信号。 通过获取第一和第五信号的异或来产生误差信号; 并且通过获取第二和第四信号的异或来产生参考信号。 第一个数据速率等于第一个时钟频率。
    • 52. 发明授权
    • Phase-locked loop circuit
    • 锁相环电路
    • US06909762B2
    • 2005-06-21
    • US10843181
    • 2004-05-11
    • Jun CaoAfshin Momtaz
    • Jun CaoAfshin Momtaz
    • H03L7/00H03L7/095H03L7/10H03D3/24
    • H03L7/10H03L7/095Y10S331/02
    • Method and circuitry for improving the accuracy and efficiency of a phase-locked loop. More specifically, the present invention relates to a method and device for monitoring the frequency discrepancy between two signals in conjunction with at least one data signal so as to improve the accuracy and efficiency of a phase-locked loop. In one embodiment of the present invention, two counters are used to check the frequency differential between a VCO signal and an external reference or input signal. An adjustable threshold is provided to determine whether the frequencies of the two signals are considered to be in a frequency-locked mode. A pair of flip-flops is used to minimize any erroneous detection of frequency discrepancy by validating two consecutive results of the frequency differential check. In addition, a data present signal is used to control the transition between the phase-locked mode and the frequency-locked mode to minimize the potential data loss.
    • 用于提高锁相环的精度和效率的方法和电路。 更具体地,本发明涉及一种用于监视两个信号之间的频率差异与至少一个数据信号的方法和装置,以便提高锁相环的精度和效率。 在本发明的一个实施例中,使用两个计数器来检查VCO信号和外部基准或输入信号之间的频率差。 提供可调阈值以确定两个信号的频率是否被认为处于频率锁定模式。 一对触发器用于通过验证频率差分检查的两个连续结果来最小化频率差异的任何错误检测。 另外,使用数据存在信号来控制锁相模式和锁频模式之间的转换,以最小化潜在的数据丢失。
    • 54. 发明授权
    • CMOS lock detect with double protection
    • CMOS锁定检测双重保护
    • US06760394B1
    • 2004-07-06
    • US09632665
    • 2000-08-07
    • Jun CaoAfshin Momtaz
    • Jun CaoAfshin Momtaz
    • H03D324
    • H03L7/10H03L7/095Y10S331/02
    • Method and circuitry for improving the accuracy and efficiency of a phase-locked loop. More specifically, the present invention relates to a method and device for monitoring the frequency discrepancy between two signals in conjunction with at least one data signal so as to improve the accuracy and efficiency of a phase-locked loop. In one embodiment of the present invention, two counters are used to check the frequency differential between a VCO signal and an external reference or input signal. An adjustable threshold is provided to determine whether the frequencies of the two signals are considered to be in a frequency-locked mode. A pair of flip-flops is used to minimize any erroneous detection of frequency discrepancy by validating two consecutive results of the frequency differential check. In addition, a data present signal is used to control the transition between the phase-locked mode and the frequency-locked mode to minimize the potential data loss.
    • 用于提高锁相环的精度和效率的方法和电路。 更具体地,本发明涉及一种用于监视两个信号之间的频率差异与至少一个数据信号的方法和装置,以便提高锁相环的精度和效率。 在本发明的一个实施例中,使用两个计数器来检查VCO信号和外部基准或输入信号之间的频率差。 提供可调阈值以确定两个信号的频率是否被认为处于频率锁定模式。 一对触发器用于通过验证频率差分检查的两个连续结果来最小化频率差异的任何错误检测。 另外,使用数据存在信号来控制锁相模式和锁频模式之间的转换,以最小化潜在的数据丢失。
    • 55. 发明授权
    • Quantized queue length arbiter
    • 量化队列长度仲裁器
    • US06420901B2
    • 2002-07-16
    • US09826160
    • 2001-04-05
    • Yao-Ching LiuWilliam DaiJason ChaoJun Cao
    • Yao-Ching LiuWilliam DaiJason ChaoJun Cao
    • G06F738
    • G06F5/065G06F13/1642G06F13/364
    • A queue length arbiter system provides for selecting from a plurality of N queues requiring access to a resource. The system includes: an arbitration circuit; and a plurality of weight circuits each being associated with a corresponding one of the queues, and being operative to store a corresponding weight count value, and also being operative to initialize the corresponding weight count value to a corresponding initial weight value determined based on a length value indicative of a number of data portions enqueued at the corresponding queue at an initial time, and being further operative to decrease the corresponding weight count value in response to a corresponding one of a plurality of grant signals, and also being operative to generate a corresponding one of a plurality of weight count signals, the corresponding weight count signal carrying the corresponding weight count value. The arbitration circuit includes: a plurality of weight checking circuits associated with corresponding ones of the queues, each checking circuit being operative to generate a corresponding one of a plurality of select signals indicative of a corresponding selected one of the queues in response to each of the weight count signals, the corresponding selected queue being determined based on the weight count values; and a resolving circuit responsive to each of the select signals, and being operative to choose one of the weight checking circuits, and also being operative to provide the grant signals, the grant signals indicating a granted queue that is selected by the chosen weight circuit.
    • 队列长度仲裁系统提供从需要访问资源的多个N队列中进行选择。 该系统包括:仲裁电路; 以及多个加权电路,每个加权电路各自与相应的一个队列相关联,并且可操作以存储对应的权重计数值,并且还可操作以将相应的权重计数值初始化为基于长度确定的对应的初始权重值 指示在初始时间在对应队列中入队的数据部分的数量的值,并且还可操作以响应于多个授权信号中的相应一个来减少对应的权重计数值,并且还可操作以产生对应的 多个重量计数信号中的一个,相应的重量计数信号携带相应的重量计数值。 仲裁电路包括:与对应的队列相关联的多个加权检查电路,每个检查电路可操作以响应于每个所述队列中的每一个产生指示对应的所选择的一个队列的多个选择信号中的对应的一个 重量计数信号,基于重量计数值确定相应的选择队列; 以及响应于每个选择信号的解析电路,并且可操作以选择权重检验电路中的一个,并且还可操作以提供授权信号,所述授权信号指示由所选权重电路选择的授权队列。
    • 56. 发明授权
    • Load balancing in link aggregation and trunking
    • 链路聚合和中继中的负载均衡
    • US06363077B1
    • 2002-03-26
    • US09249837
    • 1999-02-12
    • David WongCheng-chung ShihJun CaoWilliam Dai
    • David WongCheng-chung ShihJun CaoWilliam Dai
    • H04L1256
    • H04L47/10H04L47/125
    • A communications network switch includes a plurality of network ports for transmitting and receiving packets to and from network nodes via network links, each of the packets having a destination address and a source address, the switch being operative to communicate with at least one trunking network device via at least one trunk formed by a plurality of aggregated network links. The communications network switch provides a method and apparatus for balancing the loading of aggregated network links of the trunk, thereby increasing the data transmission rate through the trunk. The switch includes: a packet buffer for temporarily storing a packet received at a source port of the network ports, the packet having a source address value, and a destination address value indicating a destination node that is communicatively coupled with the switch via a data path including a trunk; a packet routing unit for determining a destination trunked port associated with the packet, the destination trunked port including a subset of the plurality of network ports, the destination trunked port being coupled to the destination node via the data path; and load balancing unit for selecting a destination port associated with the packet from the subset of network ports; whereby transmission loading of the aggregated network links of the trunk is balanced. In varying embodiments, the load balancing unit is operative to select destination ports from the subsets of network ports as a function of source port ID values, source addresses, and destination addresses.
    • 通信网络交换机包括多个网络端口,用于经由网络链路向网络节点发送和接收分组,每个分组具有目的地地址和源地址,该交换机可操作以与至少一个中继网络设备 经由由多个聚合网络链路形成的至少一个中继线。 通信网络交换机提供了一种用于平衡中继聚合网络链路负载的方法和装置,从而增加了通过中继线的数据传输速率。 交换机包括:用于临时存储在网络端口的源端口处接收到的分组的分组缓冲器,该分组具有源地址值,以及指示通过数据路径与交换机通信地耦合的目的地节点的目的地地址值 包括一个树干; 分组路由单元,用于确定与所述分组相关联的目的地中继端口,所述目的地中继端口包括所述多个网络端口的子集,所述目的地中继端口经由所述数据路径耦合到所述目的地节点; 以及负载平衡单元,用于从所述网络端口的子集中选择与所述分组相关联的目的地端口; 从而使主干的聚合网络链路的传输负载平衡。 在不同的实施例中,负载平衡单元用于根据源端口ID值,源地址和目的地址从网络端口子集中选择目的地端口。
    • 59. 发明授权
    • Terminal device capable of link layer encryption and decryption and data processing method thereof
    • 能够进行链路层加密和解密的终端设备及其数据处理方法
    • US09009466B2
    • 2015-04-14
    • US13995641
    • 2011-06-17
    • Qin LiJun CaoManxia Tie
    • Qin LiJun CaoManxia Tie
    • H04L29/06H04L9/08
    • H04L63/0428H04L9/08H04L63/162
    • There are a terminal device capable of link layer encryption and decryption and a data process method thereof, and the terminal device includes a link layer processing module including a control module, a data frame encryption module, a data frame decryption module, a key management module, an algorithm module, a transmission port and a reception port; and the control module is connected with the transmission port through the data frame encryption module, the reception port is connected with the control module through the data frame decryption module, the control module is connected with the key management module, the data frame encryption module is connected with the data frame decryption module through the key management module, and the data frame encryption module is connected with the data frame decryption module through the algorithm module.
    • 存在能够进行链路层加密和解密的终端设备及其数据处理方法,并且终端设备包括链路层处理模块,该链路层处理模块包括控制模块,数据帧加密模块,数据帧解密模块,密钥管理模块 算法模块,传输端口和接收端口; 控制模块通过数据帧加密模块与传输端口连接,接收端口通过数据帧解密模块与控制模块连接,控制模块与密钥管理模块连接,数据帧加密模块为 通过密钥管理模块与数据帧解密模块相连,数据帧加密模块通过算法模块与数据帧解密模块连接。