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51. 发明申请

US20080258814A1 VARIABLE GAIN AMPLIFIER AND METHOD FOR ACHIEVING VARIABLE GAIN AMPLIFICATION WITH HIGH BANDWIDTH AND LINEARITY 失效
标题翻译：用于实现具有高带宽和线性的可变增益放大的可变增益放大器和方法
公开(公告)号：US20080258814A1
公开(公告)日：2008-10-23
申请号：US12135720
申请日：2008-06-09
申请人： Namik K. Kocaman , Jun Cao
发明人： Namik K. Kocaman , Jun Cao
IPC分类号： H03F3/45
CPC分类号： H03G3/3084 , H03G1/0088
摘要： Various example embodiments are disclosed. According to one example embodiment, a high bandwidth, fine granularity variable gain amplifier (“VGA”) may comprise an attenuator, a gain block and a gain adjustment control. The attenuator may comprise at least one pair of attenuator differential input nodes and at least one pair of attenuator differential output nodes. The gain block may comprise at least one pair of gain block differential input nodes coupled to the at least one pair of attenuator differential output nodes and at least one pair of gain block differential output nodes. The gain adjustment control may be configured to adjust a gain of the gain block.
摘要翻译：公开了各种示例性实施例。根据一个示例实施例，高带宽精细可变增益放大器（“VGA”）可以包括衰减器，增益块和增益调整控制。衰减器可以包括至少一对衰减器差分输入节点和至少一对衰减器差分输出节点对。所述增益块可以包括耦合到所述至少一对衰减器差分输出节点和至少一对增益块差分输出节点的至少一对增益块差分输入节点。增益调整控制可以被配置为调整增益块的增益。

52. 发明授权

US07362174B2 Current-controlled CMOS (C3MOS) wideband input data amplifier for reduced differential and common-mode reflection 有权
标题翻译：电流控制CMOS（C3MOS）宽带输入数据放大器，用于降低差分和共模反射
公开(公告)号：US07362174B2
公开(公告)日：2008-04-22
申请号：US11320402
申请日：2005-12-28
申请人： Jun Cao
发明人： Jun Cao
IPC分类号： H03F3/45
CPC分类号： H03F3/601 , C08G61/02 , C08G61/124 , C08G61/126 , C09K11/06 , C09K2211/1416 , C09K2211/1425 , C09K2211/1433 , C09K2211/145 , C09K2211/1458 , C09K2211/1466 , C09K2211/1483 , C09K2211/1491 , C09K2211/186 , H01L51/0039 , H01L51/0052 , H01L51/0053 , H01L51/0054 , H01L51/0056 , H01L51/0059 , H01L51/0067 , H01L51/0068 , H01L51/0071 , H01L51/0081 , H01L51/0095 , H01L51/5293 , H03F1/42 , H03F3/195 , H03F3/45183 , H03F3/45632 , H03F3/45704 , H03F2200/36 , H03F2203/45084 , H03F2203/45118 , H03F2203/45296 , H03F2203/45318 , H03F2203/45332 , H03F2203/45418 , H03F2203/45466 , H03F2203/45512 , H03F2203/45548 , H03F2203/45554 , H03F2203/45638 , H03F2203/45702 , H05B33/14
摘要： Current-controlled CMOS (C3MOS) wideband input data amplifier for reduced differential and common-mode reflection. Impedance matching and bandwidth extension provides desired gain at higher frequencies and may be achieved at the interface between silicon and package and/or circuit board within various integrated circuits that may be employed within communication devices. In some instances, a differential transistor pair is employed that also includes Miller capacitors coupled between the gate of one transistor of the differential transistor pair to the drain of the other transistor of the differential transistor pair. This can also include series load connected resistors and inductors coupled between the respective drains of the transistors of the differential transistor pair to a power supply voltage. Also, series connected input inductors may also couple to the gates of the transistors of the differential transistor pair.
摘要翻译：电流控制CMOS（C3MOS）宽带输入数据放大器，用于降低差分和共模反射。阻抗匹配和带宽扩展在较高频率下提供期望的增益，并且可以在可以在通信设备中使用的各种集成电路内的硅和封装和/或电路板之间的接口处实现。在一些情况下，使用差分晶体管对，其还包括耦合在差分晶体管对的一个晶体管的栅极与差分晶体管对的另一个晶体管的漏极之间的米勒电容器。这还可以包括串联负载连接的电阻器和电感器，该电阻器和电感器耦合在差分晶体管对的晶体管的相应的漏极之间到电源电压。此外，串联的输入电感器也可以耦合到差分晶体管对的晶体管的栅极。

53. 发明授权

US07205792B2 Methods and circuitry for implementing first-in first-out structure 有权
公开(公告)号：US07205792B2
公开(公告)日：2007-04-17
申请号：US11027848
申请日：2004-12-31
申请人： Afshin Momtaz , Xin Wang , Jun Cao , Armond Hairapetian , David Chung
发明人： Afshin Momtaz , Xin Wang , Jun Cao , Armond Hairapetian , David Chung
IPC分类号： G11C8/04 , G11C7/00
CPC分类号： G06F5/10 , G06F2205/106
摘要： Methods and circuitry for implementing high speed first-in first-out (FIFO) structures. In one embodiment, a FIFO is disclosed that allows the frequency of one clock, e.g., the write clock, to be different than (e.g., half) that of the other (read) clock. In another embodiment a FIFO is presented that can be set and/or reset asynchronously. Other embodiments are disclosed wherein the read and write pointers are effectively monitored to ensure proper timing relationship, to detect loss of clock as well as to detect other abnormal FIFO conditions.

54. 发明授权

US07183540B2 Apparatus for measuring photo diodes' temperature dependence 有权
标题翻译：用于测量光电二极管温度依赖性的设备
公开(公告)号：US07183540B2
公开(公告)日：2007-02-27
申请号：US11082357
申请日：2005-03-17
申请人： Chao Zhang , Xuefei Zeng , Zhong Yang , Yuanjun Huang , Zhiyong Jiang , Jun Cao
发明人： Chao Zhang , Xuefei Zeng , Zhong Yang , Yuanjun Huang , Zhiyong Jiang , Jun Cao
IPC分类号： H01J7/24
CPC分类号： G01J1/08 , G01J1/02 , G01J1/0252 , G01J1/04 , G01J1/0418 , G01J2001/4466 , G01R31/2635 , G01R31/2642
摘要： A system for measuring gains of a plurality of photo diodes includes a chamber adapted to host the plurality of photo diodes and a temperature control unit configured to control the temperature within the chamber to a predetermined temperature. A control unit selects at least one of the plurality of photo diodes. A hosting unit is configured to provide a bias voltage to the selected photo diode at the predetermined temperature. A light source transmits photo signals to the selected photo diode at the predetermined temperature. A measurement unit configured to measure current signals generated by the selected photo diode in response to the photo signals under the bias voltage at the predetermined temperature.
摘要翻译：用于测量多个光电二极管的增益的系统包括适于容纳多个光电二极管的室，以及被配置为将室内的温度控制在预定温度的温度控制单元。控制单元选择多个光电二极管中的至少一个。托管单元被配置为在预定温度下向所选择的光电二极管提供偏置电压。光源在预定温度下将光信号传输到选定的光电二极管。测量单元，被配置为响应于在预定温度下的偏置电压下的光信号来测量由所选择的光电二极管产生的电流信号。

55. 发明授权

US07167024B2 Methods and circuitry for implementing first-in first-out structure 有权
标题翻译：实现先进先出结构的方法和电路
公开(公告)号：US07167024B2
公开(公告)日：2007-01-23
申请号：US11027864
申请日：2004-12-31
申请人： Afshin Momtaz , Xin Wang , Jun Cao , Armond Hairapetian , David Chung
发明人： Afshin Momtaz , Xin Wang , Jun Cao , Armond Hairapetian , David Chung
IPC分类号： H03K19/173 , G11C11/00
CPC分类号： G06F5/10 , G06F2205/106
摘要： Methods and circuitry for implementing high speed first-in first-out (FIFO) structures. In one embodiment, a FIFO is disclosed that allows the frequency of one clock, e.g., the write clock, to be different than (e.g., half) that of the other (read) clock. In another embodiment a FIFO is presented that can be set and/or reset asynchronously. Other embodiments are disclosed wherein the read and write pointers are effectively monitored to ensure proper timing relationship, to detect loss of clock as well as to detect other abnormal FIFO conditions.
摘要翻译：用于实现高速先进先出（FIFO）结构的方法和电路。在一个实施例中，公开了允许一个时钟（例如写时钟）的频率与另一（读取）时钟的频率不同的（例如，一半）的FIFO。在另一个实施例中，呈现可以异步地设置和/或复位的FIFO。公开了其他实施例，其中有效地监视读取和写入指针，以确保正确的时序关系，以检测时钟损耗以及检测其他异常FIFO条件。

56. 发明申请

US20060208180A1 Apparatus for measuring photo diodes' temperature dependence 有权
标题翻译：用于测量光电二极管温度依赖性的设备
公开(公告)号：US20060208180A1
公开(公告)日：2006-09-21
申请号：US11082357
申请日：2005-03-17
申请人： Chao Zhang , Xuefei Zeng , Zhong Yang , Yuanjun Huang , Zhiyong Jiang , Jun Cao
发明人： Chao Zhang , Xuefei Zeng , Zhong Yang , Yuanjun Huang , Zhiyong Jiang , Jun Cao
IPC分类号： H01J7/24
CPC分类号： G01J1/08 , G01J1/02 , G01J1/0252 , G01J1/04 , G01J1/0418 , G01J2001/4466 , G01R31/2635 , G01R31/2642
摘要： A system for measuring gains of a plurality of photo diodes includes a chamber adapted to host the plurality of photo diodes and a temperature control unit configured to control the temperature within the chamber to a predetermined temperature. A control unit selects at least one of the plurality of photo diodes. A hosting unit is configured to provide a bias voltage to the selected photo diode at the predetermined temperature. A light source transmits photo signals to the selected photo diode at the predetermined temperature. A measurement unit configured to measure current signals generated by the selected photo diode in response to the photo signals under the bias voltage at the predetermined temperature.
摘要翻译：用于测量多个光电二极管的增益的系统包括适于容纳多个光电二极管的室，以及被配置为将室内的温度控制在预定温度的温度控制单元。控制单元选择多个光电二极管中的至少一个。托管单元被配置为在预定温度下向所选择的光电二极管提供偏置电压。光源在预定温度下将光信号传输到选定的光电二极管。测量单元，被配置为响应于在预定温度下的偏置电压下的光信号来测量由所选择的光电二极管产生的电流信号。

57. 发明授权

US07103130B2 Phase-locked loop circuit 有权
标题翻译：锁相环电路
公开(公告)号：US07103130B2
公开(公告)日：2006-09-05
申请号：US11117768
申请日：2005-04-28
申请人： Jun Cao , Afshin Momtaz
发明人： Jun Cao , Afshin Momtaz
IPC分类号： H03D3/24
CPC分类号： H03L7/10 , H03L7/095 , Y10S331/02
摘要： Method and circuitry for improving the accuracy and efficiency of a phase-locked loop. More specifically, the present invention relates to a method and device for monitoring the frequency discrepancy between two signals in conjunction with at least one data signal so as to improve the accuracy and efficiency of a phase-locked loop. In one embodiment of the present invention, two counters are used to check the frequency differential between a VCO signal and an external reference or input signal. An adjustable threshold is provided to determine whether the frequencies of the two signals are considered to be in a frequency-locked mode. A pair of flip-flops is used to minimize any erroneous detection of frequency discrepancy by validating two consecutive results of the frequency differential check. In addition, a data present signal is used to control the transition between the phase-locked mode and the frequency-locked mode to minimize the potential data loss.
摘要翻译：用于提高锁相环的精度和效率的方法和电路。更具体地，本发明涉及一种用于监视两个信号之间的频率差异与至少一个数据信号的方法和装置，以便提高锁相环的精度和效率。在本发明的一个实施例中，使用两个计数器来检查VCO信号和外部参考或输入信号之间的频率差。提供可调阈值以确定两个信号的频率是否被认为处于频率锁定模式。一对触发器用于通过验证频率差分检查的两个连续结果来最小化频率差异的任何错误检测。另外，使用数据存在信号来控制锁相模式和锁频模式之间的转换，以最小化潜在的数据丢失。

58. 发明申请

US20060187918A1 Powerful and expandable pipeline architecture for a network device 有权
标题翻译：强大而可扩展的网络设备管道架构
公开(公告)号：US20060187918A1
公开(公告)日：2006-08-24
申请号：US11081644
申请日：2005-03-17
申请人： Brandon Smith , Jun Cao
发明人： Brandon Smith , Jun Cao
IPC分类号： H04L12/56 , H04L12/28
CPC分类号： H04L45/742 , H04L49/3063
摘要： A network device for processing data on a data network including a plurality of ports, configured to receive data packets and to send out processed data packets, a modification engine configured to parse, evaluate and modify the data packets to produce the processed data packets and a series of search engine pipeline stages configured to perform lookup searches through a plurality of search engines. The series of search engine pipeline stages perform search requests in sequential processing steps and any stage of the series of search engine pipeline stages may submit a particular search request to the plurality of search engines and receive search results particular to a particular data packet at a respective processing step.
摘要翻译：一种用于处理包括多个端口在内的数据网络上的数据的网络设备，用于接收数据分组并发送处理后的数据分组;修改引擎，被配置为解析，评估和修改数据分组以产生经处理的数据分组;以及一系列搜索引擎流水线级配置为通过多个搜索引擎执行查找搜索。一系列搜索引擎流水线阶段在顺序处理步骤中执行搜索请求，并且该系列搜索引擎流水线阶段的任何阶段可以向多个搜索引擎提交特定的搜索请求，并在相应的处理步骤接收特定数据分组的特定搜索结果处理步骤。

59. 发明授权

US07072885B2 Method and apparatus for performing a binary search on an expanded tree 失效
公开(公告)号：US07072885B2
公开(公告)日：2006-07-04
申请号：US10965074
申请日：2004-10-15
申请人： Jun Cao , Brandon Carl Smith , Eric Ng
发明人： Jun Cao , Brandon Carl Smith , Eric Ng
IPC分类号： G06F17/30
CPC分类号： G06F17/30985 , Y10S707/99933
摘要： A method and apparatus for searching an electronically stored table of information including a plurality of table entries and facilitating high speed searching of a table to provide a longest matching entry. The table searching method uses at least one memory unit having a table of information including a plurality of data entries. The table of information has a plurality of search keys associated with the plurality of data entries and the plurality of search keys form a tree structure based on a prefix length for each of the search keys. The plurality of search keys are expanded such that each of the plurality of search keys has two lowest level search keys associated therewith that cover a lowest level of the tree structure. A binary search of the lowest level search keys is performed based on a search value to determine a longest prefix match. A data entry of the plurality of data entries is output based on said longest prefix match. The method is also applicable to routing data in an internet router where the routing of data packets depends on address information stored in the table of information.

60. 发明授权

US06700899B1 Bit slice arbiter 失效
标题翻译：位片仲裁器
公开(公告)号：US06700899B1
公开(公告)日：2004-03-02
申请号：US09241658
申请日：1999-02-02
申请人： Jun Cao
发明人： Jun Cao
IPC分类号： H04L1242
CPC分类号： H04L12/433
摘要： An arbiter circuit is provided for resolving a plurality of N request signals received from a plurality of agents requesting access to a resource. The arbiter circuit includes: a token distribution circuit responsive to a first clock signal defining a grant cycle, and providing a plurality of token priority signals each corresponding with one of the agents, the distribution circuit being operative to prioritize one of the agents at the beginning of each grant cycle by asserting the token priority signal corresponding with the prioritized agent; means forming a token ring; and a plurality of N grant devices coupled together by the token ring, each of the grant devices corresponding with an associated one of the agents and being responsive to the corresponding request signal provided by the associated agent, and also being responsive to the token priority signal corresponding with the associated agent, and being further responsive to a corresponding token carry signal, each of the devices being operative to provide a grant signal to its associated agent if the corresponding request signal is asserted and either the corresponding token priority signal or the corresponding token carry signal is asserted. The token ring means may include a token look ahead device providing enhanced performance characteristics. The token look ahead device is operative to generate the token carry signals in a predictive manner to eliminate a ripple effect.
摘要翻译：提供了一种仲裁器电路，用于解析从多个请求访问资源的代理接收的多个N个请求信号。仲裁器电路包括：令牌分配电路，响应于定义许可周期的第一时钟信号，并且提供每个与代理之一相对应的多个令牌优先级信号，分配电路可操作以在开始时对代理之一进行优先级排序通过断言与优先化代理相对应的令牌优先级信号来确定每个授权周期; 意味着形成令牌环; 以及由所述令牌环耦合在一起的多个N个授权设备，所述许可设备中的每一个与所述代理中的相关联的一个对应，并且响应于由所述相关联的代理提供的相应的请求信号，并且还响应于所述令牌优先级信号对应于相关联的代理，并且进一步响应于相应的令牌进位信号，每个设备可操作以向对应的代理提供授权信号，如果相应的请求信号被断言，并且相应的令牌优先级信号或相应的令牌进位信号被断言。令牌环装置可以包括提供增强的性能特征的令牌前视装置。令牌前视装置可操作以预测方式产生令牌进位信号以消除纹波效应。

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