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51. 发明授权

US08756591B2 Generating compiled code that indicates register liveness 有权
公开(公告)号：US08756591B2
公开(公告)日：2014-06-17
申请号：US13251803
申请日：2011-10-03
申请人： Michael K. Gschwind , Valentina Salapura
发明人： Michael K. Gschwind , Valentina Salapura
IPC分类号： G06F9/45
CPC分类号： G06F9/3832 , G06F8/447 , G06F9/3016 , G06F9/3859
摘要： Object code is generated from an internal representation that includes a plurality of source operands. The generating includes performing for each source operand in the internal representation determining whether a last use has occurred for the source operand. The determining includes accessing a data flow graph to determine whether all uses of a live range have been emitted. If it is determined that a last use has occurred for the source operand, an architected resource associated with the source operand is marked for last-use indication. A last-use indication is then generated for the architected resource. Instructions and the last-use indications are emitted into the object code.

52. 发明申请

US20130262839A1 INSTRUCTION MERGING OPTIMIZATION 有权
标题翻译：指导性优化
公开(公告)号：US20130262839A1
公开(公告)日：2013-10-03
申请号：US13432458
申请日：2012-03-28
申请人： Michael K. Gschwind , Valentina Salapura
发明人： Michael K. Gschwind , Valentina Salapura
IPC分类号： G06F9/30 , G06F9/318
CPC分类号： G06F9/30181 , G06F9/3017 , G06F9/3836
摘要： A computer system for optimizing instructions is configured to identify two or more machine instructions as being eligible for optimization, to merge the two or more machine instructions into a single optimized internal instruction that is configured to perform functions of the two or more machine instructions, and to execute the single optimized internal instruction to perform the functions of the two or more machine instructions. Being eligible includes determining that the two or more machine instructions include a first instruction specifying a first target register and a second instruction specifying the first target register as a source register and a target register. The second instruction is a next sequential instruction of the first instruction in program order, wherein the first instruction specifies a first function to be performed, and the second instruction specifies a second function to be performed.
摘要翻译：用于优化指令的计算机系统被配置为将两个或更多个机器指令识别为有资格进行优化，以将两个或多个机器指令合并成被配置为执行两个或更多个机器指令的功能的单个优化内部指令，以及执行单个优化的内部指令来执行两个或更多个机器指令的功能。合格包括确定两个或多个机器指令包括指定第一目标寄存器的第一指令和指定第一目标寄存器作为源寄存器和目标寄存器的第二指令。第二指令是程序顺序中的第一指令的下一个顺序指令，其中第一指令指定要执行的第一功能，并且第二指令指定要执行的第二功能。

53. 发明申请

US20130262822A1 CACHING OPTIMIZED INTERNAL INSTRUCTIONS IN LOOP BUFFER 有权
标题翻译：缓存缓存中优化的内部指令
公开(公告)号：US20130262822A1
公开(公告)日：2013-10-03
申请号：US13432512
申请日：2012-03-28
申请人： Michael K. Gschwind , Valentina Salapura
发明人： Michael K. Gschwind , Valentina Salapura
IPC分类号： G06F9/30
CPC分类号： G06F9/30145 , G06F9/3017 , G06F9/381 , G06F9/384
摘要： Embodiments of the invention relate to a computer system for storing an internal instruction loop in a loop buffer. The computer system includes a loop buffer and a processor. The computer system is configured to perform a method including fetching instructions from memory to generate an internal instruction to be executed, detecting a beginning of a first instruction loop in the instructions, determining that a first internal instruction loop corresponding to the first instruction loop is not stored in the loop buffer, fetching the first instruction loop, optimizing one or more instructions corresponding to the first instruction loop to generate a first optimized internal instruction loop, and storing the first optimized internal instruction loop in the loop buffer based on the determination that the first internal instruction loop is not stored in the loop buffer.
摘要翻译：本发明的实施例涉及一种用于在循环缓冲器中存储内部指令循环的计算机系统。计算机系统包括循环缓冲器和处理器。计算机系统被配置为执行一种方法，包括从存储器取出指令以产生要执行的内部指令，检测指令中的第一指令循环的开始，确定与第一指令循环相对应的第一内部指令循环不是存储在循环缓冲器中，获取第一指令循环，优化与第一指令循环相对应的一个或多个指令以产生第一优化内部指令循环，以及基于确定所述第一优化内部指令循环，将所述第一优化内部指令循环存储在所述循环缓冲器中第一个内部指令循环不存储在循环缓冲区中。

54. 发明申请

US20130179736A1 TICKET CONSOLIDATION 有权
标题翻译：票务合并
公开(公告)号：US20130179736A1
公开(公告)日：2013-07-11
申请号：US13348172
申请日：2012-01-11
申请人： Michael K. Gschwind , Ruchi Mahindru , Valentina Salapura
发明人： Michael K. Gschwind , Ruchi Mahindru , Valentina Salapura
IPC分类号： G06F11/07
CPC分类号： G06F11/3075 , G06F11/3006
摘要： A method of ticket consolidation in computing environment may in one aspect analyze problem reports, determine whether problems reported by machines are caused by the same or substantially the same run-time configuration error or are occurring on the same physical server, and are within the given sensitivity time window, consolidate the problem tickets and increase the priority of the consolidated ticket.
摘要翻译：在计算环境中的票据合并的方法可以在一个方面分析问题报告，确定机器报告的问题是由相同或基本相同的运行时配置错误引起的，或者是在相同的物理服务器上发生的，并且在给定的敏感时间窗口，整合问题单，增加综合票的优先级。

55. 发明申请

US20130086367A1 Tracking operand liveliness information in a computer system and performance function based on the liveliness information 审中-公开
标题翻译：在计算机系统中跟踪操作数活力信息，并基于活动信息执行性能函数
公开(公告)号：US20130086367A1
公开(公告)日：2013-04-04
申请号：US13251441
申请日：2011-10-03
申请人： Michael K. Gschwind , Valentina Salapura
发明人： Michael K. Gschwind , Valentina Salapura
IPC分类号： G06F9/30 , G06F9/302
CPC分类号： G06F9/3834 , G06F9/30076 , G06F9/30105 , G06F9/30127 , G06F9/30185 , G06F9/3832 , G06F9/384 , G06F9/3851 , G06F9/3855 , G06F9/462
摘要： Operand liveness state information is maintained during context switches for current architected operands of executing programs the current operand state information indicating whether corresponding current operands are any one of enabled or disabled for use by a first program module, the first program module comprising machine instructions of an instruction set architecture (ISA) for disabling current architected operands, wherein a current operand is accessed by a machine instruction of said first program module, the accessing comprising using the current operand state information to determine whether a previously stored current operand value is accessible by the first program module.
摘要翻译：操作数活动状态信息在用于执行程序的当前构造操作数的上下文切换期间被维持，当前操作数状态信息指示相应的当前操作数是否是由第一程序模块使用或禁用的任何一个，第一程序模块包括机器指令指令集架构（ISA），用于禁用当前的架构操作数，其中当前操作数由所述第一程序模块的机器指令访问，所述访问包括使用当前操作数状态信息来确定先前存储的当前操作数值是否可被第一个程序模块。

56. 发明申请

US20080263280A1 LOW COMPLEXITY SPECULATIVE MULTITHREADING SYSTEM BASED ON UNMODIFIED MICROPROCESSOR CORE 有权
标题翻译：基于未修改的微处理器核心的低复杂度测量多路复用系统
公开(公告)号：US20080263280A1
公开(公告)日：2008-10-23
申请号：US12147914
申请日：2008-06-27
申请人： Alan G. Gara , Michael K. Gschwind , Valentina Salapura
发明人： Alan G. Gara , Michael K. Gschwind , Valentina Salapura
IPC分类号： G06F12/08
CPC分类号： G06F12/0811 , G06F9/3828 , G06F9/3842 , G06F9/3851 , G06F12/0815 , G06F2212/507
摘要： A system, method and computer program product for supporting thread level speculative execution in a computing environment having multiple processing units adapted for concurrent execution of threads in speculative and non-speculative modes. Each processing unit includes a cache memory hierarchy of caches operatively connected therewith. The apparatus includes an additional cache level local to each processing unit for use only in a thread level speculation mode, each additional cache for storing speculative results and status associated with its associated processor when handling speculative threads. The additional local cache level at each processing unit are interconnected so that speculative values and control data may be forwarded between parallel executing threads. A control implementation is provided that enables speculative coherence between speculative threads executing in the computing environment.
摘要翻译：一种用于在具有多个处理单元的计算环境中支持线程级推测性执行的系统，方法和计算机程序产品，该处理单元适于以推测和非推测模式并行执行线程。每个处理单元包括与其可操作地连接的高速缓存的高速缓冲存储器层级。该装置包括仅在线程级推测模式中使用的每个处理单元本地的附加高速缓存级别，每个附加高速缓存用于存储推测结果以及处理推测性线程时与其相关联的处理器相关联的状态。在每个处理单元处的附加本地高速缓存级别互连，使得推测值和控制数据可以在并行执行线程之间转发。提供了一种控制实现，其实现在计算环境中执行的推测线程之间的推测性一致性。

57. 发明申请

US20080046700A1 Method and apparatus for efficient performance monitoring of a large number of simultaneous events 失效
公开(公告)号：US20080046700A1
公开(公告)日：2008-02-21
申请号：US11507307
申请日：2006-08-21
申请人： Alan G. Gara , Michael K. Gschwind , Valentina Salapura
发明人： Alan G. Gara , Michael K. Gschwind , Valentina Salapura
IPC分类号： G06F9/44
CPC分类号： G06F11/348 , Y02D10/34
摘要： A system for monitoring a large number of simultaneous events implements a hybrid counter array device having a first counter portion comprising counter devices, each counter device for receiving signals representing occurrences of events from an event source and providing a first count value corresponding to a lower order bits of the hybrid counter array. A second counter portion comprises a memory array device having addressable memory locations in correspondence with the counter devices, each addressable memory location for storing a second count value representing higher order bits. A control device monitors each of the counter devices and initiates updating a value of a corresponding second count value stored at the corresponding addressable memory location. The system includes interrupt pre-indication for providing fast interrupt trigger to a processor device when a count value related to an event equals a threshold value. A data transfer sub-system additionally enables one or more of: read access or write access to both the count values in the first and second counter portions over a narrow bus, the read/write access for purposes of initializing and determining status of the count values for a monitored event type in response to a processor device request.

58. 发明授权

US09690583B2 Exploiting an architected list-use operand indication in a computer system operand resource pool 有权
公开(公告)号：US09690583B2
公开(公告)日：2017-06-27
申请号：US13251519
申请日：2011-10-03
申请人： Michael K. Gschwind , Valentina Salapura
发明人： Michael K. Gschwind , Valentina Salapura
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30072 , G06F9/30138 , G06F9/3832 , G06F9/384 , G06F9/3859
摘要： A pool of available physical registers are provided for architected registers, wherein operations are performed that activate and deactivate selected architected registers, such that the deactivated selected architected registers need not retain values, and physical registers can be deallocated to the pool, wherein deallocation of physical registers is performed after a last-use by a designated last-use instruction, wherein the last-use information is provided either by the last-use instruction or a prefix instruction, wherein reads to deallocated architecture registers return an architected default value.

59. 发明授权

US09513915B2 Instruction merging optimization 有权
标题翻译：指令合并优化
公开(公告)号：US09513915B2
公开(公告)日：2016-12-06
申请号：US13432537
申请日：2012-03-28
申请人： Michael K. Gschwind , Valentina Salapura
发明人： Michael K. Gschwind , Valentina Salapura
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30181 , G06F9/3017 , G06F9/3836 , G06F9/384
摘要： A computer system for optimizing instructions includes a processor including an instruction execution unit configured to execute instructions and an instruction optimization unit configured to optimize instructions and memory to store machine instructions to be executed by the instruction execution unit. The computer system is configured to perform a method including analyzing machine instructions from among a stream of instructions to be executed by the instruction execution unit, the machine instructions including a memory load instruction and a data processing instruction to perform a data processing function based on the memory load instruction, identifying the machine instructions as being eligible for optimization, merging the machine instructions into a single optimized internal instruction, and executing the single optimized internal instruction to perform a memory load function and a data processing function corresponding to the memory load instruction and the data processing instruction.
摘要翻译：用于优化指令的计算机系统包括：处理器，包括被配置为执行指令的指令执行单元和被配置为优化指令和存储器以存储由指令执行单元执行的机器指令的指令优化单元。计算机系统被配置为执行一种方法，包括从由指令执行单元执行的指令流中分析机器指令，包括存储器加载指令的机器指令和数据处理指令，以执行基于存储器加载指令，将机器指令识别为符合优化的要求，将机器指令合并到单个优化的内部指令中，以及执行单个优化内部指令以执行对应于存储器加载指令的存储器加载功能和数据处理功能，以及数据处理指令。

60. 发明授权

US09323530B2 Caching optimized internal instructions in loop buffer 有权
公开(公告)号：US09323530B2
公开(公告)日：2016-04-26
申请号：US13432512
申请日：2012-03-28
申请人： Michael K. Gschwind , Valentina Salapura
发明人： Michael K. Gschwind , Valentina Salapura
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30145 , G06F9/3017 , G06F9/381 , G06F9/384
摘要： Embodiments of the invention relate to a computer system for storing an internal instruction loop in a loop buffer. The computer system includes a loop buffer and a processor. The computer system is configured to perform a method including fetching instructions from memory to generate an internal instruction to be executed, detecting a beginning of a first instruction loop in the instructions, determining that a first internal instruction loop corresponding to the first instruction loop is not stored in the loop buffer, fetching the first instruction loop, optimizing one or more instructions corresponding to the first instruction loop to generate a first optimized internal instruction loop, and storing the first optimized internal instruction loop in the loop buffer based on the determination that the first internal instruction loop is not stored in the loop buffer.

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