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51. 发明授权

US6057597A Semiconductor package with pre-fabricated cover 有权
标题翻译：具有预制盖的半导体封装
公开(公告)号：US6057597A
公开(公告)日：2000-05-02
申请号：US172451
申请日：1998-10-14
申请人： Warren M. Farnworth , David R. Hembree , Derek Gochnour , Salman Akram , John O. Jacobson , James M. Wark , Steven G. Thummel
发明人： Warren M. Farnworth , David R. Hembree , Derek Gochnour , Salman Akram , John O. Jacobson , James M. Wark , Steven G. Thummel
IPC分类号： H01L23/04 , H01L23/10 , H01L23/12
CPC分类号： H01L23/10 , H01L23/04 , H01L2224/16 , H01L2224/48091 , H01L24/48 , H01L2924/00014 , H01L2924/01087 , H01L2924/14 , H01L2924/15151 , H01L2924/15174 , H01L2924/15311 , H01L2924/16152 , H01L2924/16195
摘要： A semiconductor package includes a substrate having one or more dice mounted thereto, and a cover adapted to protect and form a sealed space for the dice. The cover can be pre-fabricated of molded plastic, or stamped metal, and attached to the substrate using a cured seal. A hole can also be provided through the substrate to permit pressure equalization during formation of the seal. The cover can be prefabricated in an enclosed configuration for attachment directly to the substrate, or in a planar configuration for attachment to a peripheral ridge on the substrate. In either embodiment, the cover is removable to permit defective dice to be replaced or repaired.
摘要翻译：半导体封装包括具有安装在其上的一个或多个裸片的衬底和适于保护并形成用于裸片的密封空间的盖。盖可以用模制塑料或冲压金属预制，并使用固化的密封件附接到基底。还可以通过基底提供孔，以在形成密封期间允许压力平衡。盖可以以封闭构造预制成直接附接到基底，或者以平面构造附接到基底上的外围脊。在任一实施例中，盖可移动以允许更换或修理有缺陷的骰子。

52. 发明授权

US06687989B1 Method for fabricating interconnect having support members for preventing component flexure 有权
标题翻译：用于制造具有用于防止部件弯曲的支撑构件的互连的方法
公开(公告)号：US06687989B1
公开(公告)日：2004-02-10
申请号：US10096649
申请日：2002-03-12
申请人： Warren M. Farnworth , Mike Hess , David R. Hembree , James M. Wark , John O. Jacobson , Salman Akram
发明人： Warren M. Farnworth , Mike Hess , David R. Hembree , James M. Wark , John O. Jacobson , Salman Akram
IPC分类号： H05K310
CPC分类号： G01R1/0483 , Y10T29/49147 , Y10T29/49155 , Y10T29/49165
摘要： A test carrier and an interconnect for testing semiconductor components, such as bare dice and chip scale packages, are provided. The carrier includes a base on which the interconnect is mounted, and a force applying mechanism for biasing the component against the interconnect. The interconnect includes interconnect contacts configured to make temporary electrical connections with component contacts (e.g., bond pads, solder balls). The interconnect also includes support members configured to physically contact the component, to prevent flexure of the component due to pressure exerted by the force applying mechanism. The support members can be formed integrally with the interconnect using an etching process. In addition, the support members can include an elastomeric layer to provide cushioning and to accommodate Z-direction dimensional variations.
摘要翻译：提供了测试载体和用于测试半导体部件（例如裸芯片和芯片级封装）的互连。载体包括其上安装有互连件的基座，以及用于将部件抵靠互连件的力施加机构。互连包括被配置为与部件触点（例如，焊盘，焊球）进行临时电连接的互连触头。互连还包括被配置为物理地接触部件的支撑部件，以防止部件由于施力机构施加的压力而挠曲。支撑构件可以使用蚀刻工艺与互连一体地形成。此外，支撑构件可以包括弹性体层以提供缓冲并适应Z方向尺寸变化。

53. 发明授权

US6072323A Temporary package, and method system for testing semiconductor dice having backside electrodes 失效
标题翻译：用于测试具有背面电极的半导体裸片的临时封装和方法系统
公开(公告)号：US6072323A
公开(公告)日：2000-06-06
申请号：US812098
申请日：1997-03-03
申请人： David R. Hembree , Salman Akram , Warren M. Farnworth , James M. Wark
发明人： David R. Hembree , Salman Akram , Warren M. Farnworth , James M. Wark
IPC分类号： G01R31/28 , G01R31/26
CPC分类号： G01R31/2886
摘要： A temporary package, a method, and a system for testing a semiconductor die having a backside electrode are provided. The temporary package includes a base for retaining the die; a conductive member for electrically contacting the backside electrode on the die; and terminal contacts in electrical communication with the conductive member. The package also includes a force applying mechanism for biasing the conductive member against the backside electrode. A conductive path between the conductive member and terminal contacts can be through a wire, or through the force applying mechanism. In an alternate embodiment the temporary package includes a base and terminal contacts formed in the configuration of a conventional semiconductor package. A cover for the base can include a metal, carbon filled elastomer, conductive foam, or conductive adhesive conductive member. The conductive member can be adapted to simultaneously contact the backside electrode on the die, and a mating contact on the base in electrical communication with the terminal contact. In addition, the conductive member can function as a heat sink for cooling the die during the test procedures.
摘要翻译：提供了一种用于测试具有背面电极的半导体管芯的临时封装，方法和系统。临时包装包括用于保持模具的基座; 导电构件，用于电接触模具上的背面电极; 以及与导电构件电连通的端子触点。封装还包括用于将导电构件偏压抵靠背侧电极的施力机构。导电构件和端子触点之间的导电路径可以通过导线或通过施力机构。在替代实施例中，临时封装包括以常规半导体封装的结构形成的基极和端子触点。用于基座的盖可以包括金属，填充碳的弹性体，导电泡沫或导电粘合剂导电构件。导电构件可以适于同时接触模具上的背面电极，以及基座上与端子触点电连通的配合触点。此外，导电构件可以用作在测试过程中用于冷却模具的散热器。

54. 发明授权

US06419844B1 Method for fabricating calibration target for calibrating semiconductor wafer test systems 失效
标题翻译：制造用于校准半导体晶片测试系统的校准目标的方法
公开(公告)号：US06419844B1
公开(公告)日：2002-07-16
申请号：US09469339
申请日：1999-12-20
申请人： Andrew J. Krivy , Warren M. Farnworth , David R. Hembree , Salman Akram , James M. Wark , John O. Jacobson
发明人： Andrew J. Krivy , Warren M. Farnworth , David R. Hembree , Salman Akram , James M. Wark , John O. Jacobson
IPC分类号： H01L2100
CPC分类号： G01R35/005 , G01R1/073 , Y10T29/49197
摘要： A calibration target for calibrating semiconductor wafer test systems including probe testers and probe card analyzers is provided. Also provided are calibration methods using the calibration target, and a method for fabricating the calibration target. The calibration target includes a substrate with various three dimensional alignment features formed thereon. A first type of alignment feature includes a contrast layer and an alignment fiducial formed on a tip portion thereof. The contrast layer and alignment fiducial are configured for viewing by a viewing device of the probe card analyzer, or the test system, to achieve X-direction and Y-direction calibration. A second type of alignment feature includes a conductive layer formed on a tip portion thereof, which is configured to electrically engage a contact on a check plate of the probe card analyzer, or a probe contact on a probe card of the test system, to achieve Z-direction calibration. The alignment features can be formed by forming raised members on a silicon substrate, and depositing and etching metal layers on the raised members.
摘要翻译：提供了用于校准包括探针测试仪和探针卡分析仪在内的半导体晶片测试系统的校准目标。还提供了使用校准目标的校准方法以及用于制造校准目标的方法。校准目标包括其上形成有各种三维对准特征的基板。第一类型的对准特征包括形成在其顶端部分上的对比层和对准基准。对比层和对准基准被配置为通过探针卡分析仪或测试系统的观察装置进行观察，以实现X方向和Y方向校准。第二类型的对准特征包括形成在其尖端部分上的导电层，其被配置为与探针卡分析器的支撑板上的触点或测试系统的探针卡上的探针接触电接合，以实现 Z向校准。对准特征可以通过在硅衬底上形成凸起构件，以及在凸起构件上沉积和蚀刻金属层来形成。

55. 发明授权

US6060894A Temporary package, method and system for testing semiconductor dice having backside electrodes 有权
标题翻译：用于测试具有背面电极的半导体裸片的临时封装，方法和系统
公开(公告)号：US6060894A
公开(公告)日：2000-05-09
申请号：US365676
申请日：1999-08-02
申请人： David R. Hembree , Salman Akram , Warren M. Farnworth , James M. Wark
发明人： David R. Hembree , Salman Akram , Warren M. Farnworth , James M. Wark
IPC分类号： G01R31/28 , G01R31/26
CPC分类号： G01R31/2886
摘要： A temporary package, a method, and a system for testing a semiconductor die having a backside electrode are provided. The temporary package includes a base for retaining the die; a conductive member for electrically contacting the backside electrode on the die; and terminal contacts in electrical communication with the conductive member. The package also includes a force applying mechanism for biasing the conductive member against the backside electrode. A conductive path between the conductive member and terminal contacts can be through a wire, or through the force applying mechanism. In an alternate embodiment the temporary package includes a base and terminal contacts formed in the configuration of a conventional semiconductor package. A cover for the base can include a metal, carbon filled elastomer, conductive foam, or conductive adhesive conductive member. The conductive member can be adapted to simultaneously contact the backside electrode on the die, and a mating contact on the base in electrical communication with the terminal contact. In addition, the conductive member can function as a heat sink for cooling the die during the test procedures.
摘要翻译：提供了一种用于测试具有背面电极的半导体管芯的临时封装，方法和系统。临时包装包括用于保持模具的基座; 导电构件，用于电接触模具上的背面电极; 以及与导电构件电连通的端子触点。封装还包括用于将导电构件偏压抵靠背侧电极的施力机构。导电构件和端子触点之间的导电路径可以通过导线或通过施力机构。在替代实施例中，临时封装包括以常规半导体封装的结构形成的基极和端子触点。用于基座的盖可以包括金属，填充碳的弹性体，导电泡沫或导电粘合剂导电构件。导电构件可以适于同时接触模具上的背面电极，以及基座上与端子触点电连通的配合触点。此外，导电构件可以用作在测试过程中用于冷却模具的散热器。

56. 发明授权

US06210984B1 Method and apparatus for automatically positioning electronic dice within component packages 有权
标题翻译：电子管芯在组件封装内自动定位的方法和装置
公开(公告)号：US06210984B1
公开(公告)日：2001-04-03
申请号：US09399640
申请日：1999-09-20
申请人： Warren M. Farnworth , Alan G. Wood , John O. Jacobson , David R. Hembree , James M. Wark , Jennifer L. Folaron , Robert J. Folaron , Jay C. Nelson , Lelan D. Warren
发明人： Warren M. Farnworth , Alan G. Wood , John O. Jacobson , David R. Hembree , James M. Wark , Jennifer L. Folaron , Robert J. Folaron , Jay C. Nelson , Lelan D. Warren
IPC分类号： H01L2166
CPC分类号： H01L21/67276 , G01R31/2851 , G01R31/2886 , G01R31/2893 , G01R31/311 , H01L21/67126 , H01L21/67242 , H01L21/67259 , H01L21/681 , H01L24/74 , H01L2924/12042 , H01L2924/14 , H05K13/08 , Y10T29/49004 , Y10T29/49131 , Y10T29/53174 , Y10T29/53178 , H01L2924/00
摘要： A method and apparatus of assembling and disassembling semiconductor dice to be tested from the components of a temporary test package. A computer-controlled vision system is employed to align the dice with the temporary test package bases, and an automated robot arm system is employed to retrieve and assemble the dice with the various package components. The invention has particular utility in the burn-in and other pre-packaging testing of dice to establish known good dice (KGD).
摘要翻译：从临时测试包的组件组装和拆卸要测试的半导体骰子的方法和装置。采用计算机控制的视觉系统将骰子与临时测试包基座对准，并且采用自动机器人手臂系统来检索和组装骰子与各种包装部件。本发明在骰子的老化和其他预包装测试中具有特殊的用途，以建立已知的骰子（KGD）。

57. 发明授权

US5955877A Method and apparatus for automatically positioning electronic dice within component packages 有权
标题翻译：电子管芯在组件封装内自动定位的方法和装置
公开(公告)号：US5955877A
公开(公告)日：1999-09-21
申请号：US170844
申请日：1998-10-13
申请人： Warren M. Farnworth , Alan G. Wood , John O. Jacobson , David R. Hembree , James M. Wark , Jennifer L. Folaron , Robert J. Folaron , Jay C. Nelson , Lelan D. Warren
发明人： Warren M. Farnworth , Alan G. Wood , John O. Jacobson , David R. Hembree , James M. Wark , Jennifer L. Folaron , Robert J. Folaron , Jay C. Nelson , Lelan D. Warren
IPC分类号： G01R31/26 , G01R31/28 , G01R31/311 , H01L21/00 , H01L21/60 , H01L21/66 , H01L21/68 , H05K13/08
CPC分类号： H01L21/67276 , G01R31/2851 , G01R31/2886 , G01R31/2893 , H01L21/67126 , H01L21/67242 , H01L21/67259 , H01L21/681 , H01L24/74 , H05K13/08 , G01R31/311 , H01L2924/12042 , H01L2924/14 , Y10T29/49004 , Y10T29/49131 , Y10T29/53174 , Y10T29/53178
摘要： A method and apparatus of assembling and disassembling semiconductor dice to be tested from the components of a temporary test package. A computer-controlled vision system is employed to align the dice with the temporary test package bases, and an automated robot arm system is employed to retrieve and assemble the dice with the various package components. The invention has particular utility in the burn-in and other pre-packaging testing of dice to establish known good dice (KGD).
摘要翻译：从临时测试包的组件组装和拆卸要测试的半导体骰子的方法和装置。采用计算机控制的视觉系统将骰子与临时测试包基座对准，并且采用自动机器人手臂系统来检索和组装骰子与各种包装部件。本发明在骰子的老化和其他预包装测试中具有特殊的用途，以建立已知的骰子（KGD）。

58. 发明授权

US07223626B2 Spacers for packaged microelectronic imagers and methods of making and using spacers for wafer-level packaging of imagers 有权
标题翻译：用于封装的微电子成像器的间隔器以及制造和使用间隔件用于成像器的晶片级封装的方法
公开(公告)号：US07223626B2
公开(公告)日：2007-05-29
申请号：US10922192
申请日：2004-08-19
申请人： Warren M. Farnworth , Alan G. Wood , James M. Wark , David R. Hembree , Rickie C. Lake
发明人： Warren M. Farnworth , Alan G. Wood , James M. Wark , David R. Hembree , Rickie C. Lake
IPC分类号： H01L21/00
CPC分类号： H01L31/0203 , H01L27/14618 , H01L27/14625 , H01L27/14634 , H01L27/14683 , H01L2224/48227 , H01L2224/48091 , H01L2924/00014
摘要： Methods of packaging microelectronic imagers and packaged microelectronic imagers. An embodiment of such a method can include providing an imager workpiece having a plurality of imager dies arranged in a die pattern and providing a cover substrate through which a desired radiation can propagate. The imager dies include image sensors and integrated circuitry coupled to the image sensors. The method further includes providing a spacer having a web that includes an adhesive and has openings arranged to be aligned with the image sensors. For example, the web can be a film having an adhesive coating, or the web itself can be a layer of adhesive. The method continues by assembling the imager workpiece with the cover substrate such that (a) the spacer is between the imager workpiece and the cover substrate, and (b) the openings are aligned with the image sensors. The attached web is not cured after the imager workpiece and the cover substrate have both been adhered to the web. As such, the web does not outgas contaminants into the compartments in which the image sensors are housed.
摘要翻译：包装微电子成像仪和封装的微电子成像仪的方法。这种方法的实施例可以包括提供具有以模片图案布置的多个成像模具的成像工件，并提供覆盖基板，期望的辐射可以通过该基板传播。成像器裸片包括耦合到图像传感器的图像传感器和集成电路。该方法还包括提供具有包括粘合剂并具有布置成与图像传感器对准的开口的腹板的间隔件。例如，网可以是具有粘合剂涂层的膜，或者网本身可以是一层粘合剂。该方法通过将成像器工件与盖基板组装成使得（a）间隔件位于成像器工件和盖基板之间，并且（b）开口与图像传感器对准，该方法继续。在成像器工件和盖基板都已经粘附在卷材上之后，连接的卷材不固化。因此，纸幅不会将污染物排出到其中容纳图像传感器的隔室中。

59. 发明授权

US06900459B2 Apparatus for automatically positioning electronic dice within component packages 失效
标题翻译：电子骰子在组件包中自动定位的装置
公开(公告)号：US06900459B2
公开(公告)日：2005-05-31
申请号：US10310752
申请日：2002-12-05
申请人： Warren M. Farnworth , Alan G. Wood , John O. Jacobson , David R. Hembree , James M. Wark , Jennifer L. Folaron , Robert J. Folaron , Jay C. Nelson , Lelan D. Warren
发明人： Warren M. Farnworth , Alan G. Wood , John O. Jacobson , David R. Hembree , James M. Wark , Jennifer L. Folaron , Robert J. Folaron , Jay C. Nelson , Lelan D. Warren
IPC分类号： G01R31/26 , G01R31/28 , G01R31/311 , H01L21/00 , H01L21/60 , H01L21/66 , H01L21/68 , H05K13/08 , H01L23/58 , G01R31/02
CPC分类号： H01L21/67276 , G01R31/2851 , G01R31/2886 , G01R31/2893 , G01R31/311 , H01L21/67126 , H01L21/67242 , H01L21/67259 , H01L21/681 , H01L24/74 , H01L2924/12042 , H01L2924/14 , H05K13/08 , Y10T29/49004 , Y10T29/49131 , Y10T29/53174 , Y10T29/53178 , H01L2924/00
摘要： A method and apparatus of assembling and disassembling semiconductor dice to be tested from the components of a temporary test package. A computer-controlled vision system is employed to align the dice with the temporary test package bases, and an automated robot arm system is employed to retrieve and assemble the dice with the various package components. The invention has particular utility in the burn-in and other pre-packaging testing of dice to establish known good dice (KGD).
摘要翻译：从临时测试包的组件组装和拆卸要测试的半导体骰子的方法和装置。采用计算机控制的视觉系统将骰子与临时测试包基座对准，并且采用自动机器人手臂系统来检索和组装骰子与各种包装部件。本发明在骰子的老化和其他预包装测试中具有特殊的用途，以建立已知的骰子（KGD）。

60. 发明授权

US07723741B2 Spacers for packaged microelectronic imagers and methods of making and using spacers for wafer-level packaging of imagers 有权
标题翻译：用于封装的微电子成像器的间隔器以及制造和使用间隔件用于成像器的晶片级封装的方法
公开(公告)号：US07723741B2
公开(公告)日：2010-05-25
申请号：US11451398
申请日：2006-06-13
申请人： Warren M. Farnworth , Alan G. Wood , James M. Wark , David R. Hembree , Rickie C. Lake
发明人： Warren M. Farnworth , Alan G. Wood , James M. Wark , David R. Hembree , Rickie C. Lake
IPC分类号： H01L21/00
CPC分类号： H01L31/0203 , H01L27/14618 , H01L27/14625 , H01L27/14634 , H01L27/14683 , H01L2224/48227 , H01L2224/48091 , H01L2924/00014
摘要： Methods of packaging microelectronic imagers and packaged microelectronic imagers. An embodiment of such a method can include providing an imager workpiece having a plurality of imager dies arranged in a die pattern and providing a cover substrate through which a desired radiation can propagate. The imager dies include image sensors and integrated circuitry coupled to the image sensors. The method further includes providing a spacer having a web that includes an adhesive and has openings arranged to be aligned with the image sensors. For example, the web can be a film having an adhesive coating, or the web itself can be a layer of adhesive. The method continues by assembling the imager workpiece with the cover substrate such that (a) the spacer is between the imager workpiece and the cover substrate, and (b) the openings are aligned with the image sensors. The attached web is not cured after the imager workpiece and the cover substrate have both been adhered to the web. As such, the web does not outgas contaminants into the compartments in which the image sensors are housed.
摘要翻译：包装微电子成像仪和封装的微电子成像仪的方法。这种方法的实施例可以包括提供具有以模片图案布置的多个成像模具的成像工件，并提供覆盖基板，期望的辐射可以通过该基板传播。成像器裸片包括耦合到图像传感器的图像传感器和集成电路。该方法还包括提供具有包括粘合剂并具有布置成与图像传感器对准的开口的腹板的间隔件。例如，网可以是具有粘合剂涂层的膜，或者网本身可以是一层粘合剂。该方法通过将成像器工件与盖基板组装成使得（a）间隔件位于成像器工件和盖基板之间，并且（b）开口与图像传感器对准，该方法继续。在成像器工件和盖基板都已经粘附在卷材上之后，连接的卷材不固化。因此，纸幅不会将污染物排出到其中容纳图像传感器的隔室中。

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