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51. 发明申请

US20120210105A1 PROCESSOR POWER CONSUMPTION CONTROL AND VOLTAGE DROP VIA MICRO-ARCHITECTURAL BANDWIDTH THROTTLING 审中-公开
标题翻译：处理器消耗电力控制和电压降通过微结构带宽折射
公开(公告)号：US20120210105A1
公开(公告)日：2012-08-16
申请号：US13212042
申请日：2011-08-17
申请人： Sanjeev Jahagirdar , Edward Gamsaragan , Scott E. Siers
发明人： Sanjeev Jahagirdar , Edward Gamsaragan , Scott E. Siers
IPC分类号： G06F9/30
CPC分类号： G06F1/3203 , G06F1/3296 , Y02D10/172
摘要： A method, device, and system are disclosed. In one embodiment the method includes supplying a processor with a first voltage. The method also includes allowing the processor to function within an enhanced processor halt state at the first voltage. The first voltage is a voltage below the lowest compatible voltage for the enhanced processor halt state. The method allows the processor to execute instructions upon waking from the enhanced processor halt state at the first voltage by throttling a maximum throughput rate of instructions being executed in the processor.
摘要翻译：公开了一种方法，装置和系统。在一个实施例中，该方法包括向处理器提供第一电压。该方法还包括允许处理器在第一电压下在增强的处理器停止状态下起作用。第一电压是低于用于增强的处理器停止状态的最低兼容电压的电压。该方法允许处理器在通过在处理器中执行的指令的最大吞吐速率从第一电压处的增强型处理器停止状态唤醒时执行指令。

52. 发明授权

US07917787B2 Method, apparatus and system to dynamically choose an aoptimum power state 有权
标题翻译：动态选择最佳功率状态的方法，装置和系统
公开(公告)号：US07917787B2
公开(公告)日：2011-03-29
申请号：US12419855
申请日：2009-04-07
申请人： Sanjeev Jahagirdar , Varghese George , Jose Allarey , Eric Heit
发明人： Sanjeev Jahagirdar , Varghese George , Jose Allarey , Eric Heit
IPC分类号： G06F1/00 , G05D9/00 , H04B1/04 , H04B1/38
CPC分类号： G06F1/3203
摘要： Some embodiments of the invention include an apparatus and method for dynamically choosing an optimum power state. In some embodiments, the optimum power state may be determined from historical information about the various power states that any of the embodiments of the apparatus or a system equipped with embodiments of the apparatus or operating embodiments of the method may encounter. Some embodiments may generate registers to maintain information regarding the various power states. In some embodiments, power management logic may determine the optimum power state based upon this information. Other embodiments are described.
摘要翻译：本发明的一些实施例包括用于动态选择最佳功率状态的装置和方法。在一些实施例中，最佳功率状态可以根据关于各种功率状态的历史信息来确定，该装置或装置的任何实施例装备有该方法的装置或操作实施例的实施例可能会遇到。一些实施例可以生成寄存器来维护关于各种功率状态的信息。在一些实施例中，功率管理逻辑可以基于该信息来确定最佳功率状态。描述其他实施例。

53. 发明申请

US20100083021A1 Voltage stabilization for clock signal frequency locking 有权
标题翻译：电压稳定时钟信号频率锁定
公开(公告)号：US20100083021A1
公开(公告)日：2010-04-01
申请号：US12286190
申请日：2008-09-29
申请人： Jose Allarey , Sanjeev Jahagirdar , Ivan Herrera
发明人： Jose Allarey , Sanjeev Jahagirdar , Ivan Herrera
IPC分类号： G06F1/00 , G06F15/00
CPC分类号： G06F1/08 , G06F1/30
摘要： A processor, system, and method are disclosed. In an embodiment, the processor includes a first site and a second site. There is a link to transmit a voltage stabilization signal from the second site to the first site. In the first site voltage correction logic can dynamically modify a voltage supplied to the first site and second site. In the second site there is logic to assert the voltage stabilization signal. After asserting the voltage stabilization signal, the second site is granted at least a window of time in which the supplied voltage to the second site does not change.
摘要翻译：公开了一种处理器，系统和方法。在一个实施例中，处理器包括第一站点和第二站点。存在将第二站点传送到第一站点的电压稳定信号的链路。在第一站点电压校正逻辑可以动态地修改提供给第一站点和第二站点的电压。在第二个站点有逻辑来表示电压稳定信号。在确定电压稳定信号之后，第二站点被授予至少一个时间窗口，其中提供给第二站点的电压不改变。

54. 发明授权

US07664970B2 Method and apparatus for a zero voltage processor sleep state 有权
标题翻译：零电压处理器睡眠状态的方法和装置
公开(公告)号：US07664970B2
公开(公告)日：2010-02-16
申请号：US11323254
申请日：2005-12-30
申请人： Sanjeev Jahagirdar , George Varghese , John B. Conrad , Robert Milstrey , Stephen A. Fischer , Alon Navch , Shai Rotem
发明人： Sanjeev Jahagirdar , George Varghese , John B. Conrad , Robert Milstrey , Stephen A. Fischer , Alon Navch , Shai Rotem
IPC分类号： G06F1/00 , G06F1/26 , G06F15/00 , G06F11/00
CPC分类号： G06F1/3287 , G06F1/3203 , G06F1/324 , G06F1/3243 , G06F1/3246 , G06F1/3275 , G06F1/3293 , G06F1/3296 , G06F9/4418 , G06F11/1441 , G06F12/084 , G06F12/0875 , G06F2212/281 , G06F2212/305 , G06F2212/314 , G11C7/1072 , Y02B70/123 , Y02B70/126 , Y02B70/32 , Y02D10/152 , Y02D10/172 , Y02D50/20 , Y02P80/11 , Y10T307/305 , Y10T307/406 , Y10T307/582 , Y10T307/826
摘要： Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.
摘要翻译：本发明的实施例涉及一种用于零电压处理器睡眠状态的方法和装置。处理器可以包括专用高速缓存存储器。电压调节器可以耦合到处理器以向处理器提供工作电压。在处理器转换到零电压电源管理状态期间，电压调节器施加到处理器的工作电压可以减小到大约零，并且与处理器相关联的状态变量可以被保存到专用高速缓冲存储器。

55. 发明申请

US20090199024A1 METHOD, APPARATUS AND SYSTEM TO DYNAMICALLY CHOOSE AN AOPTIMUM POWER STATE 有权
标题翻译：方法，装置和动态动态选择系统
公开(公告)号：US20090199024A1
公开(公告)日：2009-08-06
申请号：US12419855
申请日：2009-04-07
申请人： Sanjeev Jahagirdar , Varghese George , Jose Allarey , Eric Heit
发明人： Sanjeev Jahagirdar , Varghese George , Jose Allarey , Eric Heit
IPC分类号： G06F1/00
CPC分类号： G06F1/3203
摘要： Some embodiments of the invention include an apparatus and method for dynamically choosing an optimum power state. In some embodiments, the optimum power state may be determined from historical information about the various power states that any of the embodiments of the apparatus or a system equipped with embodiments of the apparatus or operating embodiments of the method may encounter. Some embodiments may generate registers to maintain information regarding the various power states. In some embodiments, power management logic may determine the optimum power state based upon this information. Other embodiments are described.
摘要翻译：本发明的一些实施例包括用于动态选择最佳功率状态的装置和方法。在一些实施例中，最佳功率状态可以根据关于各种功率状态的历史信息来确定，该装置或装置的任何实施例装备有该方法的装置或操作实施例的实施例可能会遇到。一些实施例可以生成寄存器来维护关于各种功率状态的信息。在一些实施例中，功率管理逻辑可以基于该信息来确定最佳功率状态。描述其他实施例。

56. 发明申请

US20080215875A1 Method and apparatus for establishing safe processor operating points 有权
标题翻译：建立安全处理器工作点的方法和装置
公开(公告)号：US20080215875A1
公开(公告)日：2008-09-04
申请号：US12081204
申请日：2008-04-11
申请人： Stephen Anthony Fischer , Varghese George , Sanjeev Jahagirdar , Stephen H. Gunther
发明人： Stephen Anthony Fischer , Varghese George , Sanjeev Jahagirdar , Stephen H. Gunther
IPC分类号： G06F1/08 , G06F1/24
CPC分类号： G06F21/57 , G06F1/324 , G06F1/3296 , G06F21/575 , G06F21/70 , G06F21/81 , G06F2221/2101 , Y02D10/126
摘要： A system and method is provided for establishing safe processor operating points. Some embodiments may include a tamper resistant storage element that stores information regarding one or more operating points of an adjustable processor operating parameter. Some embodiments may further include an element to determine what the current processor operating point is of the operating parameter, and an element to compare the current operating point of the operating parameter with the stored information.
摘要翻译：提供了一种用于建立安全处理器工作点的系统和方法。一些实施例可以包括防篡改存储元件，其存储关于可调节处理器操作参数的一个或多个操作点的信息。一些实施例可以进一步包括用于确定当前处理器工作点是操作参数的元件，以及将操作参数的当前操作点与存储的信息进行比较的元件。

57. 发明申请

US20080072088A1 Method and Apparatus for a Zero Voltage Processor Sleep State 有权
标题翻译：零电压处理器睡眠状态的方法和装置
公开(公告)号：US20080072088A1
公开(公告)日：2008-03-20
申请号：US11937139
申请日：2007-11-08
申请人： Jose Allarey , Sanjeev Jahagirdar
发明人： Jose Allarey , Sanjeev Jahagirdar
IPC分类号： G06F1/32
CPC分类号： G06F1/3287 , G06F1/3203 , G06F1/324 , G06F1/3243 , G06F1/3246 , G06F1/3275 , G06F1/3293 , G06F1/3296 , G06F9/4418 , G06F11/1441 , G06F12/084 , G06F12/0875 , G06F2212/281 , G06F2212/305 , G06F2212/314 , G11C7/1072 , Y02B70/123 , Y02B70/126 , Y02B70/32 , Y02D10/152 , Y02D10/172 , Y02D50/20 , Y02P80/11 , Y10T307/305 , Y10T307/406 , Y10T307/582 , Y10T307/826
摘要： Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A voltage regulator may be coupled to a processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero while an external voltage is continuously applied to a portion of the processor to save state variables of the processor during the zero voltage management power state.
摘要翻译：本发明的实施例涉及一种用于零电压处理器睡眠状态的方法和装置。电压调节器可以耦合到处理器以向处理器提供工作电压。在向处理器转换到零电压电源管理状态期间，由电压调节器施加到处理器的工作电压可以减小到大约为零，同时外部电压被持续地施加到处理器的一部分以保存处理器的状态变量处理器在零电压管理电源状态。

58. 发明申请

US20070157036A1 Method and apparatus for a zero voltage processor sleep state 有权
标题翻译：零电压处理器睡眠状态的方法和装置
公开(公告)号：US20070157036A1
公开(公告)日：2007-07-05
申请号：US11323254
申请日：2005-12-30
申请人： Sanjeev Jahagirdar , Varghese George , John Conrad , Robert Milstrey , Stephen Fischer , Alon Navch , Shai Rotem
发明人： Sanjeev Jahagirdar , Varghese George , John Conrad , Robert Milstrey , Stephen Fischer , Alon Navch , Shai Rotem
IPC分类号： G06F1/26
CPC分类号： G06F1/3287 , G06F1/3203 , G06F1/324 , G06F1/3243 , G06F1/3246 , G06F1/3275 , G06F1/3293 , G06F1/3296 , G06F9/4418 , G06F11/1441 , G06F12/084 , G06F12/0875 , G06F2212/281 , G06F2212/305 , G06F2212/314 , G11C7/1072 , Y02B70/123 , Y02B70/126 , Y02B70/32 , Y02D10/152 , Y02D10/172 , Y02D50/20 , Y02P80/11 , Y10T307/305 , Y10T307/406 , Y10T307/582 , Y10T307/826
摘要： Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.
摘要翻译：本发明的实施例涉及一种用于零电压处理器睡眠状态的方法和装置。处理器可以包括专用高速缓存存储器。电压调节器可以耦合到处理器以向处理器提供工作电压。在处理器转换到零电压电源管理状态期间，电压调节器施加到处理器的工作电压可以减小到大约零，并且与处理器相关联的状态变量可以被保存到专用高速缓冲存储器。

59. 发明授权

US07210054B2 Maintaining processor execution during frequency transitioning 有权
标题翻译：在频率转换期间维护处理器执行
公开(公告)号：US07210054B2
公开(公告)日：2007-04-24
申请号：US10180836
申请日：2002-06-25
申请人： Sanjeev Jahagirdar , Islam Derhalli , Varghese George , Kedar Mangrulkar , Mathew Nazareth
发明人： Sanjeev Jahagirdar , Islam Derhalli , Varghese George , Kedar Mangrulkar , Mathew Nazareth
IPC分类号： G06F1/04
CPC分类号： G06F1/08
摘要： An embodiment of the present invention includes a standby clock generator and a selector. The standby clock generator generates a standby clock synchronous to a core clock. The core clock is generated by a core clock generator during a normal operation mode. The core clock generator stops the core clock during a frequency transition. The selector generates a processor clock from the standby clock during the frequency transition from the normal operation mode according to a selector control signal.
摘要翻译：本发明的实施例包括备用时钟发生器和选择器。备用时钟发生器产生与内核时钟同步的备用时钟。内核时钟由正常操作模式下的核心时钟发生器产生。核心时钟发生器在频率转换期间停止核心时钟。根据选择器控制信号，从正常操作模式的频率转换期间，选择器从待机时钟产生处理器时钟。

60. 发明申请

US20070001694A1 On-die real time leakage energy meter 审中-公开
标题翻译：片上实时泄漏电能表
公开(公告)号：US20070001694A1
公开(公告)日：2007-01-04
申请号：US11173147
申请日：2005-06-30
申请人： Sanjeev Jahagirdar , Jose Allarey , Varghese George
发明人： Sanjeev Jahagirdar , Jose Allarey , Varghese George
IPC分类号： G01R31/02
CPC分类号： G01R31/2891 , G01R21/02
摘要： A method includes measuring a temperature for a portion of an electronic component, determining the voltage being applied to the portion of the component, and determining a leakage power for the component portion based on a measured temperature and determined voltage for the portion of the component. The method also includes measuring a temperature for another portion of the component, determining the voltage being applied to the other component portion, and determining a leakage power for the other component portion based on the measured temperature and determined voltage for the other portion of the component. The method also includes summing the leakage power for the portion with the leakage power for the other portion of the component.
摘要翻译：一种方法包括测量电子部件的一部分的温度，确定施加到部件的该部分的电压，并且基于部件的该部分的测量温度和确定的电压来确定部件部分的泄漏功率。该方法还包括测量部件的另一部分的温度，确定施加到另一部件部分的电压，以及基于所测量的温度和组件的其它部分的确定电压来确定另一部件部分的泄漏功率。该方法还包括对具有部件的其他部分的泄漏功率的部分的泄漏功率求和。

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