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51. 发明授权

US06577910B1 Digital audio signal processors 有权
标题翻译：数字音频信号处理器
公开(公告)号：US06577910B1
公开(公告)日：2003-06-10
申请号：US09178341
申请日：1998-10-23
申请人： Peter Charles Eastty , Peter Damien Thorpe , Christopher Sleight
发明人： Peter Charles Eastty , Peter Damien Thorpe , Christopher Sleight
IPC分类号： G06F1700
CPC分类号： H04H60/04
摘要： A digital audio signal processor processes digital audio signals having a first sampling rate S1. The processor has a multiplicity of manually adjustable controls (403) for setting desired parameters of signals to be processed. Sampling means (404) sample each control (403) setting at a second sampling rate S2 less than the first rate S1 to determine the settings thereof. Applying means (401) responsive to the sampling means apply the sampled settings to the signals. For each control the applying means determines the difference of successive samples of setting and applies to the signal, subject to control by that control, increments of setting each increment being a predetermined fraction 1/n of the said difference at a rate nS2 which is n times the said second sampling rate S2.
摘要翻译：数字音频信号处理器处理具有第一采样率S1的数字音频信号。处理器具有多个可手动调节的控制（403），用于设置要处理的信号的期望参数。采样装置（404）以小于第一速率S1的第二采样率S2对每个控制（403）进行采样，以确定其设置。响应于采样装置的应用装置（401）将采样的设置应用于信号。对于每个控制，施加装置确定连续的设定采样的差值并施加到信号，受该控制的控制，将以nS2为n的所述差分的预定分数1 / n设定每个增量的增量乘以所述第二采样率S2。

52. 发明授权

US06144328A Cascaded delta sigma modulators 有权
标题翻译：级联的delta-Σ调制器
公开(公告)号：US06144328A
公开(公告)日：2000-11-07
申请号：US177394
申请日：1998-10-23
申请人： Peter Charles Eastty , Peter Damien Thorpe , Christopher Sleight
发明人： Peter Charles Eastty , Peter Damien Thorpe , Christopher Sleight
IPC分类号： H03M1/08 , H03H17/02 , H03M3/02 , H03M7/32 , H03M3/00
CPC分类号： H03M7/3006 , H03M7/3028 , H03M7/3033 , H03M7/304
摘要： A signal processor for processing 1-bit signals comprising at least a pair of Delta Sigma Modulators (DSM) coupled in series, one of the said pair of DSMs having an signal-band noise-shaping filter characteristic complementary to the signal-band noise-shaping filter characteristic of the other of the pair of DSMs.
摘要翻译：一种信号处理器，用于处理包括串联耦合的至少一对ΔΣ调制器（DSM）的1位信号，所述一对DSM具有与信号带噪声整形滤波器特性互补的信号带噪声整形滤波器特性，对一对DSM的另一个的整形滤波器特性。

53. 发明授权

US6078621A Signal processors 失效
标题翻译：信号处理器
公开(公告)号：US6078621A
公开(公告)日：2000-06-20
申请号：US978844
申请日：1997-11-26
申请人： Peter Charles Eastty , Christopher Sleight , Peter Damien Thorpe
发明人： Peter Charles Eastty , Christopher Sleight , Peter Damien Thorpe
IPC分类号： H03H17/06 , H03M7/00 , H04B14/06
CPC分类号： H03M7/3033 , H03H17/06 , H03M7/3028 , H03M7/304
摘要： A signal processor for 1-bit signals comprises a nth order Delta-Sigma Modulator, where n is greater than or equal to 2. The Delta-Sigma Modulator comprises a first input 4A for receiving a first 1-bit signal and a second input 4B for receiving a second 1-bit signal. A quantizer Q quantises a p bit signal to 1-bit form, the requantized signal being the output signal of the processor. A plurality of signal combiners are provided. A first combiner (A1, 61, c1 b1, 71) forms the integral of the sum of the input signals and the output signal multiplied by coefficients A1, B1 and C1. At least one intermediate combiner forms the integral of the sum of the first and second input signals and the output signal multiplied by coefficients A2, B2, C2 together with the output of the first combiner. The final combiner a4, b4, 64 forms the integral of the sum of the first and second signals multiplied by coefficients A4 and B4 together with the output of the preceding intermediate combiner. The coefficients A and B applied to the first and second input signals define the proportions in which the first and second signals are combined. The coefficients A and B maybe variable, generated by a generator 42.
摘要翻译：用于1位信号的信号处理器包括n阶Δ-Σ调制器，其中n大于或等于2.Δ-Σ调制器包括用于接收第一1位信号的第一输入4A和第二输入4B 用于接收第二个1位信号。量化器Q将p位信号量化为1位形式，重新量化的信号是处理器的输出信号。提供多个信号组合器。第一组合器（A1,61，c1b1,71）形成乘以系数A1，B1和C1的输入信号和输出信号之和的积分。至少一个中间组合器与第一组合器的输出一起形成第一和第二输入信号之和的总和以及乘以系数A2，B2，C2的输出信号的积分。最终组合器a4，b4，64形成乘以系数A4和B4的第一和第二信号的和与前一中间组合器的输出的积分。应用于第一和第二输入信号的系数A和B定义第一和第二信号组合的比例。系数A和B可能是变量的，由发电机42产生。

54. 发明授权

US6057792A Signal processors 失效
标题翻译：信号处理器
公开(公告)号：US6057792A
公开(公告)日：2000-05-02
申请号：US979756
申请日：1997-11-26
申请人： Peter Charles Eastty , Christopher Sleight , Peter Damien Thorpe
发明人： Peter Charles Eastty , Christopher Sleight , Peter Damien Thorpe
IPC分类号： H03M7/32 , H03H17/04 , H04B14/06 , H03M3/00
CPC分类号： H03H17/04 , H03H17/0411
摘要： An nth order Delta Sigma Modulator (DSM) where n.gtoreq.1, comprising an input (4) for receiving a 1-bit input signal having a signal component and a noise component,a quantifier (Q) for re-quantizing a p-bit signal (where p>1) to 1-bit form, the re-quantised 1-bit signal being the output signal of the DSM,a first combiner (a, A, 61, 71) for forming the integral (71) of an additive (61) combination of the product of the input 1-bit signal and a coefficient (a) and of the product of the output signal and a coefficient (A),n-1 intermediate combiners each for forming the integral of an additive combination of the product of the input 1-bit signal and a coefficient, of the product of the output signal and a coefficient and of the integral of the additive combination of the preceding combiner anda final combiner (d, 64) for forming an additive combination (64) of the input signal and a coefficient (d) and of the integral of the combiner of the preceding combination to form the said p-bit signal re-quantised by the quantifier (Q),wherein the transfer function applied by the DSM to the input 1-bit signal is ##EQU1## the transfer function applied to the quantized noise introduced by the quantizer is ##EQU2## wherein at least one of a.sub.1 to a.sub.n equals +1, and each of b.sub.1 to b.sub.n is not equal to +1.
摘要翻译：包括用于接收具有信号分量和噪声分量的1位输入信号的输入端（4）的第n级ΔΣ调制器（DSM），其中n> / = 1，用于重新量化p 位数信号（其中p> 1）到1位形式，重新量化的1位信号是DSM的输出信号，用于形成积分（71）的第一组合器（a，A，61,71）输入1位信号与系数（a）的乘积和输出信号与系数（A）的乘积的加法（61）组合，n-1个中间组合器，用于形成一个输入1比特信号的乘积和输出信号的乘积的系数和前一个组合器和最后组合器（d，64）的加法组合的系数和积分的系数的加法组合，用于形成输入信号的加法组合（64）和系数（d）以及前一组合的组合器的积分形成所述p比特信号由量化器（Q）重新量化，其中由DSM施加到输入1比特信号的传递函数是应用于由量化器引入的量化噪声的传递函数，其中a1至an中的至少一个等于+ 1，b1〜bn中的每一个不等于+1。

55. 发明授权

US5983258A Apparatus and method for summing 1-bit signals 失效
标题翻译：用于对1位信号求和的装置和方法
公开(公告)号：US5983258A
公开(公告)日：1999-11-09
申请号：US979469
申请日：1997-11-26
申请人： Peter Charles Eastty , Christopher Sleight , Peter Damien Thorpe
发明人： Peter Charles Eastty , Christopher Sleight , Peter Damien Thorpe
IPC分类号： G06F1/03 , G06F7/00 , G06F7/544 , G06F7/50
CPC分类号： G06F7/5443 , G06F1/03 , G06F7/00
摘要： An arithmetic stage calculates the sum AX+BY where A and B are 1-bit signals and X and Y p bit coefficients X=7 and Y=3 and the corresponding bits b.sub.1 to b.sub.5 are represented together with the corresponding logical states of A and B. It will be seen that for example column b.sub.3 together with columns A and B is the truth table of an NAND gate. Column b.sub.2 together with columns A and B is the truth table of a COINCIDENCE gate.In the example of FIG. 5 column b.sub.4 equals B; column b.sub.1 is logical 0 whatever the states of A and B; and column b.sub.5 is NOT A.Thus in accordance with one illustrative embodiment of the invention the arithmetic stage 40 may be implemented by the logic circuit of FIG. 6 wherebit b.sub.5 is produced by inverting A,bit b.sub.4 is produced by coupling output b.sub.1 to input B, via a direct connection 60,bit b.sub.3 is produced by a NAND gate 61,bit b.sub.2 is produced by a COINCIDENCE gate 62, andbit b.sub.1 is produced by coupling output b.sub.4 to a source of logical `0` via a connection 63.
摘要翻译：运算级计算和AX + BY，其中A和B是1位信号，X和Y p位系数X = 7和Y = 3，相应的位b1到b5与相应的逻辑状态A和可以看出，例如列b3与列A和B一起是NAND门的真值表。列b2和列A和B是COINCIDENCE门的真值表。在图1的示例中 5列b4等于B; 无论A和B的状态如何，列b1为逻辑0; 并且列b5不是A.因此，根据本发明的一个说明性实施例，算术级40可以由图1的逻辑电路来实现。如图6所示，通过反相A产生位b5，通过直接连接60将输出b1耦合到输入B产生位b4，比特b3由NAND门61产生，位b2由COINCIDENCE门62产生，位b 2由位C 通过连接63将输出b4耦合到逻辑“0”的源来产生b1。

56. 发明授权

US5923768A Digital audio processing 失效
标题翻译：数字音频处理
公开(公告)号：US5923768A
公开(公告)日：1999-07-13
申请号：US806250
申请日：1997-02-21
申请人： Paul Anthony Frindle , Peter Charles Eastty
发明人： Paul Anthony Frindle , Peter Charles Eastty
IPC分类号： G10L21/02 , H03G7/00 , H03M7/30
CPC分类号： H03G7/007
摘要： Digital audio processing apparatus for applying a time-varying gain to an input digital audio signal over contiguous first, second and third time periods, in which: the applied gain changes at no more than a first maximum rate of change during the first time period; the applied gain changes at no more than a second maximum rate of change during the third time period; and during the second time period the rate of change of the applied gain varies monotonically from a substantially zero rate of change towards the second maximum rate of change.
摘要翻译：数字音频处理装置，用于在连续的第一，第二和第三时间周期上对输入数字音频信号施加时变增益，其中：所施加的增益在第一时间段内不超过第一最大变化率; 所施加的增益在第三时间段内变化不超过第二最大变化率; 并且在第二时间段期间，所施加的增益的变化率从基本上零的变化率朝向第二最大变化率单调地变化。

57. 发明授权

US5892938A Interactive interface system 失效
标题翻译：互动界面系统
公开(公告)号：US5892938A
公开(公告)日：1999-04-06
申请号：US654216
申请日：1996-05-28
申请人： Peter Charles Eastty , William Edmund Cranstoun Kentish
发明人： Peter Charles Eastty , William Edmund Cranstoun Kentish
IPC分类号： G06F3/14 , G06F3/033 , H04H60/04 , H04N5/222 , H04L12/26
CPC分类号： H04H60/04 , G06F3/033
摘要： An interactive system for interfacing with signal processing apparatus having a network of interconnected processors (e.g., for a digital audio mixing console) uses a graphical user interface for monitoring the operation of the system. The graphical user interface can be used for inputting control and/or data signals at selected points in said data processing structure and/or for displaying control and/or data signals from selected points in said data processing structure in real time. A graphical representation of an audio mixing console can be used for experimentation, set-up and training purposes.
摘要翻译：与具有互连处理器（例如，用于数字音频混合控制台）的网络的信号处理设备进行接口的交互式系统使用图形用户界面来监视系统的操作。图形用户界面可用于在所述数据处理结构中的选定点处输入控制和/或数据信号和/或用于实时显示所述数据处理结构中的选定点的控制和/或数据信号。音频混音控制台的图形表示可用于实验，设置和训练。

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