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51. 发明授权

US4390888A X-y Infrared CCD sensor and method for making same 失效
标题翻译： X-y红外CCD传感器及其制作方法
公开(公告)号：US4390888A
公开(公告)日：1983-06-28
申请号：US182472
申请日：1980-08-28
申请人： Lothar Risch , Hermann Mader
发明人： Lothar Risch , Hermann Mader
IPC分类号： H04N5/33 , H01L27/146 , H01L27/148 , H01L27/14
CPC分类号： H01L27/14875 , H01L27/14649
摘要： An x-y infrared CCD sensor employing the photoelectric effect as in a p-doped semiconductor substrate of silicon with an n.sup.+ pn diode as the infrared sensor element with a three layer structure in the vertical direction in the semiconductor substrate and a n-channel charge coupled device shift register. The device has a metal-oxide-semiconductor storage electrode directly adjacent to the n-region of the three layer structure. The device is manufactured by masked ion implantation with the doping density for the three layer sequence such that the doping density for the layer operating as the emitter is greater than the doping density for the layer operating as a base, which in turn is greater than the doping density for the layer operating as the collector.
摘要翻译：使用光电效应的xy红外CCD传感器，其中n + pn二极管的p掺杂半导体衬底中的红外传感器元件在半导体衬底中具有垂直方向的三层结构，并且n沟道电荷耦合器件移位寄存器。该器件具有与三层结构的n区直接相邻的金属氧化物半导体存储电极。该器件通过掩模离子注入制造，具有三层序列的掺杂密度，使得作为发射极工作的层的掺杂密度大于作为基极操作的层的掺杂密度，其又大于作为收集器操作的层的掺杂密度。

52. 发明授权

US07804708B2 Integrated circuit including an array of memory cells and method 有权
标题翻译：集成电路包括一组存储单元和方法
公开(公告)号：US07804708B2
公开(公告)日：2010-09-28
申请号：US12182698
申请日：2008-07-30
申请人： Ulrike Gruening-von Schwerin , Lothar Risch , Peter Baars , Klaus Muemmler , Stefan Tegen , Thomas Happ
发明人： Ulrike Gruening-von Schwerin , Lothar Risch , Peter Baars , Klaus Muemmler , Stefan Tegen , Thomas Happ
IPC分类号： G11C11/00 , G11C5/06 , H01L29/02
CPC分类号： G11C13/0004 , G11C2213/72 , H01L27/24
摘要： An integrated circuit including an array of memory cells and method. In one embodiment, each memory cell includes a resistively switching memory element and a selection diode for selecting one cell from the plurality of memory cells. The memory element is coupled with its top to a first selection line and with its bottom side to the selection diode, the diode further being coupled to the bottom side of a second selection line.
摘要翻译：一种包括存储单元阵列和方法的集成电路。在一个实施例中，每个存储单元包括电阻切换存储器元件和用于从多个存储器单元中选择一个单元的选择二极管。存储元件与其顶部耦合到第一选择线并且其底侧连接到选择二极管，二极管还耦合到第二选择线的底侧。

53. 发明授权

US06351408B1 Memory cell configuration 有权
标题翻译：内存单元配置
公开(公告)号：US06351408B1
公开(公告)日：2002-02-26
申请号：US09544761
申请日：2000-04-06
申请人： Siegfried Schwarzl , Lothar Risch
发明人： Siegfried Schwarzl , Lothar Risch
IPC分类号： G11C1100
CPC分类号： H01L27/228 , G11C11/15 , G11C11/16 , H01L27/222
摘要： A memory cell configuration has word lines and bit lines running transversely with respect thereto. Memory elements with a magnetoresistive effect are respectively connected between one of the word lines and one of the bit lines. The memory elements are disposed in at least two layers one above the other.
摘要翻译：存储单元配置具有相对于其横向延伸的字线和位线。具有磁阻效应的存储元件分别连接在一条字线和一条位线之间。存储元件设置在彼此之上的至少两层中。

54. 发明授权

US06184045B2 Method for DRAM cell arrangement and method for its production 有权
标题翻译： DRAM单元布置方法及其制作方法
公开(公告)号：US06184045B2
公开(公告)日：2001-02-06
申请号：US09541952
申请日：2000-04-03
申请人： Franz Hofman , Lothar Risch , Wolfgang Roesner , Wolfgang Krautschneider
发明人： Franz Hofman , Lothar Risch , Wolfgang Roesner , Wolfgang Krautschneider
IPC分类号： H01L218242
CPC分类号： H01L27/10852 , H01L27/10808
摘要： A memory cell contains at least one transistor and one capacitor connected to an upper bit line. The capacitor contains a first capacitor electrode arranged above the transistor, and is connected to the transistor. The upper bit line can be created in self-adjusted fashion on the basis of trenches which are of different widths, which extend transversely to one another, and which are arranged between the first capacitor electrodes. At least a part of each first capacitor electrode can be created from a layer which is structured by the trenches. Trenches can be narrowed by spacers.
摘要翻译：存储单元包含至少一个晶体管和一个连接到高位线的电容器。电容器包含布置在晶体管上方的第一电容器电极，并连接到晶体管。基于具有不同宽度的沟槽彼此横向延伸并且布置在第一电容器电极之间的沟槽可以以自调节的方式创建高位线。每个第一电容器电极的至少一部分可以由由沟槽构成的层产生。沟槽可以通过间隔物变窄。

55. 发明授权

US6060911A Circuit arrangement with at least four transistors, and method for the manufacture thereof 有权
标题翻译：具有至少四个晶体管的电路布置及其制造方法
公开(公告)号：US6060911A
公开(公告)日：2000-05-09
申请号：US138160
申请日：1998-08-21
申请人： Thomas Schulz , Thomas Aeugle , Wolfgang Roesner , Lothar Risch
发明人： Thomas Schulz , Thomas Aeugle , Wolfgang Roesner , Lothar Risch
IPC分类号： G11C16/04 , H01L21/8238 , H01L27/092 , H01L29/78 , H03K19/094 , H01L29/76
CPC分类号： H01L27/092 , H01L21/823885
摘要： In the circuit arrangement two of the four vertical transistors are complementary to the remaining two transistors. Two of the transistors are respectively arranged at the same level. For this purpose, layer structures (St1, St2, St3, St4) are structured that respectively have at least a channel layer and a source/drain region of one of the transistors. All the layer structures (St1, St2, St3, St4) can be produced from a layer sequence with only four layers. In order to avoid leakage currents due to a parasitic bipolar transistor, the layer structures (St1, St2, St3, St4) can be realized very thinly, using spacer-type masks. Electrical connections between parts of the four transistors can take place via layers of the layer sequence. The contacting to the output voltage terminal can take place via a step that is formed by two layers of the layer sequence.
摘要翻译：在电路布置中，四个垂直晶体管中的两个与剩余的两个晶体管互补。两个晶体管分别布置在相同的电平上。为此，层结构（St1，St2，St3，St4）被构造成分别具有至少一个晶体管的沟道层和源极/漏极区域。所有的层结构（St1，St2，St3，St4）可以仅由四层制成。为了避免由寄生双极型晶体管引起的漏电流，使用间隔型掩模，可以非常薄地实现层结构（St1，St2，St3，St4）。四个晶体管的部分之间的电连接可以通过层序列的层进行。与输出电压端子的接触可以通过由层序列的两层形成的步骤进行。

56. 发明授权

US5828076A Microelectronic component and process for its production 失效
标题翻译：微电子元件及其生产工艺
公开(公告)号：US5828076A
公开(公告)日：1998-10-27
申请号：US727440
申请日：1996-10-17
申请人： Harald Gossner , Ignaz Eisele , Lothar Risch , Erwin Hammerl
发明人： Harald Gossner , Ignaz Eisele , Lothar Risch , Erwin Hammerl
IPC分类号： H01L29/78 , B82B1/00 , H01L21/20 , H01L21/335 , H01L29/06 , H01L29/10 , H01L29/12 , H01L29/423
CPC分类号： H01L29/127 , B82Y10/00 , H01L21/02381 , H01L21/02532 , H01L21/02609 , H01L21/02639 , H01L29/1054 , H01L29/125 , H01L29/66439 , H01L29/78
摘要： In its gate region (10), a silicon MOS technology component has a surface structure (6) having edges and/or vertices at which inversion regions, suitable as quantum wires or quantum dots, are preferentially formed when a gate voltage is applied. The surface structure is preferably formed as a silicon pyramid (6) by local molecular beam epitaxy.
摘要翻译： PCT No.PCT / DE95 / 00448 Sec。 371日期1996年10月17日第 102（e）日期1996年10月17日PCT提交1995年4月4日PCT公布。 WO95 / 28741 PCT出版物日期1995年10月26日在其栅极区域（10）中，硅MOS技术部件具有具有边缘和/或顶点的表面结构（6），当栅极（10）处优选形成适合作为量子线或量子点的反转区域施加电压。表面结构优选通过局部分子束外延形成为硅金字塔（6）。

57. 发明授权

US5817552A Process of making a dram cell arrangement 失效
标题翻译：制作电视剧排列的过程
公开(公告)号：US5817552A
公开(公告)日：1998-10-06
申请号：US635526
申请日：1996-04-22
申请人： Wolfgang Roesner , Lothar Risch , Franz Hofman , Wolfgang Krautschneider
发明人： Wolfgang Roesner , Lothar Risch , Franz Hofman , Wolfgang Krautschneider
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10876 , H01L27/10823
摘要： For each storage cell, the DRAM cell arrangement has a vertical MOS transistor, the first source/drain region of which is connected to a memory node of a storage capacitor, the channel region of which is annularly enclosed by a gate electrode and the second source/drain region of which is connected to a buried bit line. The DRAM cell arrangement can be produced with a storage-cell area of 4F.sup.2 by using only two masks, F being the minimum producible structure size in the respective technology.
摘要翻译：对于每个存储单元，DRAM单元布置具有垂直MOS晶体管，其第一源极/漏极区域连接到存储电容器的存储器节点，其存储电容器的沟道区域被栅电极环形地包围，并且第二源极漏极区连接到埋地位线。可以通过仅使用两个掩模来制造具有4F2的存储单元面积的DRAM单元布置，F是相应技术中的最小可生产结构尺寸。

58. 发明授权

US4905193A Large scale integrable memory cell with a trench capacitor wherein the trench edge is surrounded by a field oxide region 失效
标题翻译：具有沟槽电容器的大规模可积分存储单元，其中沟槽边缘被场氧化物区域包围
公开(公告)号：US4905193A
公开(公告)日：1990-02-27
申请号：US372236
申请日：1989-06-26
申请人： Lothar Risch , Reinhard Tielert
发明人： Lothar Risch , Reinhard Tielert
IPC分类号： H01L27/10 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10861 , H01L27/10829
摘要： A large scale integrable memory cell including a field effect transistor lying at a bit line and further including a storage capacitor which is formed by the wall of a trench and a cooperating electrode. The active region of the storage cell which lies outside the trench is fashioned in the form of a strip. The end face forms one part of the trench edge and the remaining portion of the trench edge is surrounded by a field oxide region.
摘要翻译：一种大规模可积分存储单元，包括位于位线处的场效应晶体管，还包括由沟槽壁和配合电极形成的存储电容器。位于沟槽外部的存储单元的有源区域以条带的形式形成。端面形成沟槽边缘的一部分，并且沟槽边缘的剩余部分被场氧化物区域包围。

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