专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

51. 发明申请

WO2014004706A1 QUALIFYING SOFTWARE BRANCH-TARGET HINTS WITH HARDWARE-BASED PREDICTIONS 审中-公开
标题翻译：以硬件为基础的质量评估软件分支目标
公开(公告)号：WO2014004706A1
公开(公告)日：2014-01-03
申请号：PCT/US2013/047956
申请日：2013-06-26
申请人： QUALCOMM INCORPORATED
发明人： MORROW, Michael William , DIEFFENDERFER, James Norris , SARTORIUS, Thomas Andrew , MCILVAINE, Michael Scott , STEMPEL, Brian Michael , STREETT, Daren Eugene , REDDY, Vimal K.
IPC分类号： G06F9/38
CPC分类号： G06F9/3806 , G06F9/3848
摘要： A processor architecture to qualify software target-branch hints with hardwarebased predictions, the processor including a branch target address cache (120) having entries (122), where an entry includes a tag field to store an instruction address, a target field to store a target address, and a state field to store a state value. Upon decoding an indirect branch instruction (302), the processor determines whether an entry in the branch target address cache has an instruction address that matches the address of the decoded indirect branch instruction (306); and if there is a match, depending upon the state value stored in the entry (310), the processor will use the stored target address as the predicted target address (312) for the decoded indirect branch instruction, or will use a software provided target address hint if available.
摘要翻译：一种处理器架构，用于基于硬件预测来限定软件目标分支提示，所述处理器包括具有条目（122）的分支目标地址高速缓存（120），其中条目包括用于存储指令地址的标签字段，存储目标地址和状态字段来存储状态值。在解码间接分支指令（302）时，处理器确定分支目标地址高速缓存中的条目是否具有与解码的间接转移指令（306）的地址相匹配的指令地址; 并且如果存在匹配，则根据存储在条目（310）中的状态值，处理器将使用存储的目标地址作为解码的间接分支指令的预测目标地址（312），或将使用提供软件的目标地址提示（如果有）。

52. 发明申请

WO2013173550A1 FUSING CONDITIONAL WRITE INSTRUCTIONS HAVING OPPOSITE CONDITIONS IN INSTRUCTION PROCESSING CIRCUITS, AND RELATED PROCESSOR SYSTEMS, METHODS, AND COMPUTER-READABLE MEDIA 审中-公开
标题翻译：在指令处理电路中具有对准条件的状态写入指令以及相关处理器系统，方法和计算机可读介质
公开(公告)号：WO2013173550A1
公开(公告)日：2013-11-21
申请号：PCT/US2013/041290
申请日：2013-05-16
申请人： QUALCOMM INCORPORATED
发明人： BROWN, Melinda J. , DIEFFENDERFER, James Norris , MCILVAINE, Michael Scott , STEMPEL, Brian Michael , SMITH, Rodney Wayne , SCHOTTMILLER, Jeffery M. , IRWIN, Andrew S. , MORROW, Michael William
IPC分类号： G06F9/30
CPC分类号： G06F9/3867 , G06F9/30043 , G06F9/30072 , G06F9/3017
摘要： Fusing conditional write instructions having opposite conditions in instruction processing circuits and related processor systems, methods, and computer-readable media are disclosed. In one embodiment, a first conditional write instruction writing a first value to a target register based on evaluating a first condition is detected by an instruction processing circuit. The circuit also detects a second conditional write instruction writing a second value to the target register based on evaluating a second condition that is a logical opposite of the first condition. Either the first condition or the second condition is selected as a fused instruction condition, and corresponding values are selected as if-true and if-false values. A fused instruction is generated for selectively writing the if-true value to the target register if the fused instruction condition evaluates to true, and selectively writing the if-false value to the target register if the fused instruction condition evaluates to false.
摘要翻译：公开了在指令处理电路和相关处理器系统，方法和计算机可读介质中具有相反条件的条件写指令。在一个实施例中，由指令处理电路检测基于评估第一条件将第一值写入目标寄存器的第一条件写入指令。该电路还基于评估与第一条件逻辑相反的第二条件来检测将第二值写入目标寄存器的第二条件写入指令。选择第一个条件或第二个条件作为融合指令条件，并将相应的值选为if-true和if-false值。如果融合指令条件评估为真，则生成融合指令，以便如果融合指令条件评估为真，则将if-true值有选择地写入目标寄存器，如果融合指令条件评估为false，则选择性地将if-false值写入目标寄存器。

53. 发明申请

WO2013112607A1 PREVENTING THE DISPLACEMENT OF HIGH TEMPORAL LOCALITY OF REFERENCE DATA FILL BUFFERS 审中-公开
标题翻译：防止参考数据填充缓冲区的高速局部性的偏移
公开(公告)号：WO2013112607A1
公开(公告)日：2013-08-01
申请号：PCT/US2013/022775
申请日：2013-01-23
申请人： QUALCOMM INCORPORATED
发明人： CLANCY, Robert D , SPEIER, Thomas Philip , DIEFFENDERFER, James Norris
IPC分类号： G06F12/08
CPC分类号： G06F12/0859 , G06F12/0882 , G06F2212/1028 , Y02D10/13
摘要： The disclosure relates to accessing memory content with a high temporal locality of reference. An embodiment of the disclosure stores the content in a data buffer, determines that the content of the data buffer has a high temporal locality of reference, and accesses the data buffer for each operation targeting the content instead of a cache storing the content.
摘要翻译：本公开涉及以高参考时间局部性访问存储器内容。本公开的实施例将内容存储在数据缓冲器中，确定数据缓冲器的内容具有高的参考时间局部性，并且针对针对内容的每个操作而不是存储内容的高速缓存来访问数据缓冲器。

54. 发明申请

WO2013086529A1 AUTO-ORDERING OF STRONGLY ORDERED, DEVICE, AND EXCLUSIVE TRANSACTIONS ACROSS MULTIPLE MEMORY REGIONS 审中-公开
标题翻译：在多个存储区域进行强制订购，设备和独家交易的自动订购
公开(公告)号：WO2013086529A1
公开(公告)日：2013-06-13
申请号：PCT/US2012/068820
申请日：2012-12-10
申请人： QUALCOMM INCORPORATED
发明人： PANAVICH, Jason Lawrence , DIEFFENDERFER, James Norris , SARTORIUS, Thomas Andrew , SPEIER, Thomas Philip
IPC分类号： G06F13/16
CPC分类号： G06F13/1621
摘要： Efficient techniques are described for controlling ordered accesses in a weakly ordered storage system. A stream of memory requests is split into two or more streams of memory requests and a memory access counter is incremented for each memory request. A memory request requiring ordered memory accesses is identified in one of the two or more streams of memory requests. The memory request requiring ordered memory accesses is stalled upon determining a previous memory request from a different stream of memory requests is pending. The memory access counter is decremented for each memory request guaranteed to complete. A count value in the memory access counter that is different from an initialized state of the memory access counter indicates there are pending memory requests. The memory request requiring ordered memory accesses is processed upon determining there are no further pending memory requests.
摘要翻译：描述了用于控制弱订单存储系统中有序访问的高效技术。存储器请求流被分成两个或更多个存储器请求流，并且每个存储器请求增加存储器访问计数器。需要有序存储器访问的存储器请求在两个或更多个存储器请求流中的一个中被识别。在从不同的存储器请求流确定先前的存储器请求正在等待时，需要有序存储器访问的存储器请求被停止。对于保证完成的每个存储器请求，存储器访问计数器递减。与存储器访问计数器的初始化状态不同的存储器访问计数器中的计数值指示存在未决存储器请求。在确定没有进一步的未决存储器请求时，处理需要有序存储器访问的存储器请求。

55. 发明申请

WO2013026055A1 LINK STACK REPAIR OF ERRONEOUS SPECULATIVE UPDATE 审中-公开
标题翻译：链路堆栈修复错误的参数更新
公开(公告)号：WO2013026055A1
公开(公告)日：2013-02-21
申请号：PCT/US2012/051578
申请日：2012-08-20
申请人： QUALCOMM INCORPORATED , DIEFFENDERFER, James Norris , STEMPEL, Brian Michael , SMITH, Rodney Wayne
发明人： DIEFFENDERFER, James Norris , STEMPEL, Brian Michael , SMITH, Rodney Wayne
IPC分类号： G06F9/38
CPC分类号： G06F9/3842 , G06F9/3806 , G06F9/3861
摘要： Whenever a link address is written to the link stack, the prior value of the link stack entry is saved, and is restored to the link stack after a link stack push operation is speculatively executed following a mispredicted branch. This condition is detected by maintaining an incrementing tag register which is incremented by each link stack write instruction entering the pipeline, and a snapshot of the incrementing tag register, associated with each branch instruction. When a branch is evaluated and determined to have been mispredicted, the snapshot associated with it is compared to the incrementing tag register. A discrepancy indicates a link stack write instruction was speculatively issued into the pipeline after the mispredicted branch instruction, and pushed a link address onto the link stack, thus corrupting the link stack. The prior link address is restored to the link stack from the link stack restore buffer.
摘要翻译：每当链接地址被写入链接堆栈时，链接堆栈条目的先前值被保存，并且在错误预测的分支之后推测地执行链路堆叠推送操作之后被还原到链路栈。通过保持由进入管线的每个链路堆栈写入指令递增的递增标签寄存器以及与每个分支指令相关联的递增标签寄存器的快照来检测该条件。当分支被评估并被确定为被错误预测时，将与之相关联的快照与增量标签寄存器进行比较。一个差异表示在错误预测的分支指令之后推测发布了一个链路堆栈写入指令，并将链路地址推送到链路堆栈上，从而破坏了链路堆栈。链路堆栈恢复缓冲区中的链路栈恢复到先前的链路地址。

56. 发明申请

WO2011103326A2 APPARATUS AND METHODS TO REDUCE DUPLICATE LINE FILLS IN A VICTIM CACHE 审中-公开
标题翻译：减少VICTIM CACHE中的重复线路丢包的设备和方法
公开(公告)号：WO2011103326A2
公开(公告)日：2011-08-25
申请号：PCT/US2011/025296
申请日：2011-02-17
申请人： QUALCOMM INCORPORATED , SPEIER, Thomas Philip , DIEFFENDERFER, James Norris , SARTORIUS, Thomas Andrew
发明人： SPEIER, Thomas Philip , DIEFFENDERFER, James Norris , SARTORIUS, Thomas Andrew
IPC分类号： G06F12/08 , G06F12/12
CPC分类号： G06F12/0897 , G06F12/0804 , G06F12/128 , G06F2212/1028 , Y02D10/13
摘要： Techniques and methods are used to reduce allocations to a higher level cache of cache lines displaced from a lower level cache. The allocations of the displaced cache lines are prevented for displaced cache lines that are determined to be redundant in the next level cache, whereby castouts are reduced. To such ends, a line is selected to be displaced in a lower level cache. Information associated with the selected line is identified which indicates that the selected line is present in a higher level cache or the selected line is a write-through line. An allocation of the selected line in the higher level cache is prevented based on the identified information. Preventing an allocation of the selected line saves power that would be associated with the allocation.
摘要翻译：技术和方法用于减少从较低级别缓存中移位的高速缓存行的更高级缓存的分配。对于在下一级高速缓存中被确定为冗余的移位高速缓存线，防止移位的高速缓存行的分配，从而减少了突发。为此，选择在下一级缓存中移位的行。识别与所选行相关联的信息，其指示所选择的行存在于较高级别的高速缓存中，或者所选行是直写行。基于所识别的信息来防止在较高级别高速缓存中的所选行的分配。防止所选线路的分配节省与分配相关联的功率。

57. 发明申请

WO2010138596A1 METHODS AND APPARATUS FOR ISSUING MEMORY BARRIER COMMANDS IN A WEAKLY ORDERED STORAGE SYSTEM 审中-公开
标题翻译：在微弱订购存储系统中发出存储障碍物命令的方法和装置
公开(公告)号：WO2010138596A1
公开(公告)日：2010-12-02
申请号：PCT/US2010/036209
申请日：2010-05-26
申请人： QUALCOMM Incorporated , SPEIER, Thomas Philip , DIEFFENDERFER, James Norris , SARTORIUS, Thomas Andrew
发明人： SPEIER, Thomas Philip , DIEFFENDERFER, James Norris , SARTORIUS, Thomas Andrew
IPC分类号： G06F13/16
CPC分类号： G06F13/1621 , G06F12/0811 , G06F12/0835
摘要： Efficient techniques are described for enforcing order of memory accesses. A memory access request is received from a device which is not configured to generate memory barrier commands. A surrogate barrier is generated in response to the memory access request. A memory access request may be a read request. In the case of a memory write request, the surrogate barrier is generated before the write request is processed. The surrogate barrier may also be generated in response to a memory read request conditional on a preceding write request to the same address as the read request. Coherency is enforced within a hierarchical memory system as if a memory barrier command was received from the device which does not produce memory barrier commands.
摘要翻译：描述了有效的技术来实现存储器访问的顺序。从未被配置为生成存储器障碍命令的设备接收到存储器访问请求。响应于存储器访问请求产生替代屏障。存储器访问请求可以是读请求。在存储器写入请求的情况下，在写入请求被处理之前生成替代屏障。替代障碍也可以响应于以与读取请求相同的地址的先前写入请求为条件的存储器读取请求而产生。一致性在分层存储器系统中实施，就好像从设备接收到不产生存储器屏障命令的存储器屏障命令一样。

58. 发明申请

WO2008092159A1 SNOOP FILTERING USING A SNOOP REQUEST CACHE 审中-公开
标题翻译：使用SNOOP REQUEST CACHE进行SNOOP过滤
公开(公告)号：WO2008092159A1
公开(公告)日：2008-07-31
申请号：PCT/US2008/052216
申请日：2008-01-28
申请人： QUALCOMM Incorporated , DIEFFENDERFER, James Norris
发明人： DIEFFENDERFER, James Norris
IPC分类号： G06F12/08
CPC分类号： G06F12/0831
摘要： A snoop request cache maintains records of previously issued snoop requests. Upon writing shared data, a snooping entity performs a lookup in the cache. If the lookup hits (and, in some embodiments, includes an identification of a target processor) the snooping entity suppresses the snoop request. If the lookup misses (or hits but the hitting entry lacks an identification of the target processor) the snooping entity allocates an entry in the cache (or sets an identification of the target processor) and directs a snoop request such to the target processor, to change the state of a corresponding line in the processor's L1 cache. When the processor reads shared data, it performs a snoop cache request lookup, and invalidates a hitting entry in the event of a hit (or clears it processor identification from the hitting entry), so that other snooping entities will not suppress snoop requests to it.
摘要翻译：侦听请求缓存维护先前发出的窥探请求的记录。在写共享数据时，侦听实体在缓存中执行查找。如果查找命中（并且在一些实施例中包括目标处理器的标识），则窥探实体抑制窥探请求。如果查找未命中（或命中但击中条目缺少目标处理器的标识），则窥探实体在高速缓存中分配条目（或设置目标处理器的标识），并将窥探请求（如目标处理器）引导到更改处理器的L1缓存中相应行的状态。当处理器读取共享数据时，它执行窥探高速缓存请求查找，并在命中事件中使命中条目无效（或从命中条目清除处理器标识），以便其他侦听实体不会抑制对其的侦听请求。

59. 发明申请

WO2007133895A1 BLOCK-BASED BRANCH TARGET ADDRESS CACHE 审中-公开
标题翻译：基于块的分支目标地址高速缓存
公开(公告)号：WO2007133895A1
公开(公告)日：2007-11-22
申请号：PCT/US2007/067176
申请日：2007-04-23
申请人： QUALCOMM Incorporated , SMITH, Rodney Wayne , DIEFFENDERFER, James Norris , SARTORIUS, Thomas Andrew
发明人： SMITH, Rodney Wayne , DIEFFENDERFER, James Norris , SARTORIUS, Thomas Andrew
IPC分类号： G06F9/38
CPC分类号： G06F9/3806 , G06F9/3836
摘要： A Branch Target Address Cache (BTAC) stores a plurality of entries, each BTAC entry associated with a block of two or more instructions that includes at least one branch instruction having been evaluated taken. The BTAC entry includes an indicator of which instruction within the associated block is a taken branch instruction. The BTAC entry also includes the Branch Target Address (BTA) of the taken branch. The block size may, but does not necessarily, correspond to the number of instructions per instruction cache line.
摘要翻译：分支目标地址缓存（BTAC）存储多个条目，每个BTAC条目与包括已经被评估的至少一个分支指令的两个或更多个指令的块相关联。 BTAC条目包括关联块内哪个指令是采取的分支指令的指示符。 BTAC条目还包括采集分支的分行目标地址（BTA）。块大小可以但不一定对应于每条指令高速缓存线的指令数。

60. 发明申请

WO2007051205A1 HIGH SPEED CAM LOOKUP USING STORED ENCODED KEY 审中-公开
标题翻译：使用存储编码键的高速凸轮
公开(公告)号：WO2007051205A1
公开(公告)日：2007-05-03
申请号：PCT/US2006/060371
申请日：2006-10-30
申请人： QUALCOMM INCORPORATED , FISCHER, Jeffrey Herbert , PHAN, Michael Thaithanh , CHAI, Chiaming , DIEFFENDERFER, James Norris
发明人： FISCHER, Jeffrey Herbert , PHAN, Michael Thaithanh , CHAI, Chiaming , DIEFFENDERFER, James Norris
IPC分类号： G11C15/04
CPC分类号： G11C15/00 , G06F12/1027 , G06F2212/652 , G11C15/04
摘要： The search key and key fields of a CAM in a cache are encoded with a Hamming distance of at least two to increase the speed of the CAM by ensuring each mismatching match line is discharged by at least two transistors in parallel. Where the cache is physically tagged, the search key is a physical address. The page address portion of the physical address is encoded prior to being stored in a TLB. The page offset bits are encoded in parallel with the TLB access, and concatenated with the encoded TLB entry. If a page address addresses a large memory page size, a plurality of corresponding sub-page addresses may be generated, each addressing a smaller page size. These sub-page addresses may be encoded and stored in a micro TLB. The encoded key and key field are tolerant of single-bit soft errors.
摘要翻译：高速缓存中的CAM的搜索键和关键字段通过至少两个汉明距离进行编码，以通过确保每个不匹配的匹配线由并联的至少两个晶体管放电来增加CAM的速度。在缓存物理标记的地方，搜索关键字是物理地址。物理地址的页地址部分在被存储在TLB中之前被编码。页面偏移位与TLB访问并行编码，并与编码的TLB条目连接。如果页面地址满足大的存储器页面大小，则可以生成多个对应的子页面地址，每个地址寻址较小的页面大小。这些子页地址可以被编码并存储在微型TLB中。编码的密钥和密钥字段容忍单位软错误。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式