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51. 发明授权

US08863068B2 Current-aware floorplanning to overcome current delivery limitations in integrated circuits 有权
标题翻译：电流识别布局规划，以克服集成电路中的当前传输限制
公开(公告)号：US08863068B2
公开(公告)日：2014-10-14
申请号：US13526194
申请日：2012-06-18
申请人： Pradip Bose , Alper Buyuktosunoglu , John A. Darringer , Moinuddin K. Qureshi , Jeonghee Shin
发明人： Pradip Bose , Alper Buyuktosunoglu , John A. Darringer , Moinuddin K. Qureshi , Jeonghee Shin
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/50 , G06F2217/78
摘要： A dynamic system coupled with “pre-Silicon” design methodologies and “post-Silicon” current optimizing programming methodologies to improve and optimize current delivery into a chip, which is limited by the physical properties of the connections (e.g., Controlled Collapse Chip Connection or C4s). The mechanism consists of measuring or estimating power consumption at a certain granularity within a chip, converting the power information into C4 current information using a method, and triggering throttling mechanisms (including token based throttling) where applicable to limit the current delivery per C4 beyond pre-established limits or periods. Design aids are used to allocate C4s throughout the chip based on the current delivery requirements. The system coupled with design and programming methodologies improve and optimize current delivery is extendable to connections across layers in a multilayer 3D chip stack.
摘要翻译：与“前置硅”设计方法和“后硅”当前优化编程方法相结合的动态系统，以改进和优化当前传输到芯片的传输，这受到连接的物理特性的限制（例如，受控崩溃芯片连接或 C4s）。该机制包括测量或估计芯片内特定粒度的功耗，使用一种方法将功率信息转换为C4当前信息，并在适用的情况下触发限流机制（包括基于令牌的限制），以限制每个C4超过预先的当前传输 - 建立的限制或期限。设计辅助工具用于根据当前交付要求在整个芯片上分配C4。该系统与设计和编程方法相结合，改进并优化电流传递可扩展到多层3D芯片堆叠中的层间连接。

52. 发明授权

US08826216B2 Token-based current control to mitigate current delivery limitations in integrated circuits 有权
标题翻译：基于令牌的电流控制，以减轻集成电路中的当前传输限制
公开(公告)号：US08826216B2
公开(公告)日：2014-09-02
申请号：US13526153
申请日：2012-06-18
申请人： Pradip Bose , Alper Buyuktosunoglu , John A. Darringer , Moinuddin K. Qureshi , Jeonghee Shin
发明人： Pradip Bose , Alper Buyuktosunoglu , John A. Darringer , Moinuddin K. Qureshi , Jeonghee Shin
IPC分类号： G06F17/50 , G06F9/44 , G06F9/46 , G06F15/177 , G06F9/00 , G06F1/24 , G06F9/50 , G06F9/455
CPC分类号： G06F17/5054 , G06F9/455 , G06F9/46 , G06F9/5044 , G06F15/177 , G06F17/5022 , G06F17/5045 , G06F2212/1041 , G06F2217/78
摘要： A system and method of operating an integrated circuit (IC) having a fixed layout of one or more blocks having one or more current sources therein that draw electrical current from a power source. The method includes dynamically issuing to a block configured to perform operations responsive to an instruction received at the block, a reserve amount of tokens; determining for each issuance of instruction to the block whether that block's reserve token amount exceeds zero; and one of: issuing the instruction to the block if the token reserve for that block is greater than one, and decrementing, after issuance of the instruction, by one token the block's reserve token amount, or, preventing issuance of an instruction to the block. In the method, each block may be initialized to have: a reserve token amount of zero, a token expiration period; a token generation cycle and a token generation amount.
摘要翻译：一种具有固定布局的集成电路（IC）的系统和方法，所述集成电路（IC）具有一个或多个具有一个或多个电流源的块，其中所述一个或多个块来自电源。所述方法包括动态地发布到被配置为响应于在所述块处接收的指令执行操作的块，标记的保留量; 确定每个向块的指令的发出是否该块的储备标记量超过零; 其中之一是：如果该块的令牌保留大于1，则向块发出指令，并且在发出指令之后递减一个令牌块的保留令牌量，或者阻止向块发出指令。在该方法中，每个块可以被初始化为具有：保留令牌量为零，令牌到期期间; 令牌生成周期和令牌生成量。

53. 发明授权

US08798962B2 Virtualized abstraction with built-in data alignment and simultaneous event monitoring in performance counter based application characterization and tuning 有权
标题翻译：虚拟化抽象与基于性能计数器的应用程序表征和调优内置数据对齐和同时事件监视
公开(公告)号：US08798962B2
公开(公告)日：2014-08-05
申请号：US13052616
申请日：2011-03-21
申请人： Pradip Bose , Alper Buyuktosunoglu , Canturk Isci , Jeff Kephart , Xiaoqiao Meng , Ruhi Sarikaya
发明人： Pradip Bose , Alper Buyuktosunoglu , Canturk Isci , Jeff Kephart , Xiaoqiao Meng , Ruhi Sarikaya
IPC分类号： G06F11/30 , G06F9/455
CPC分类号： G06F11/3089 , G06F11/3024 , G06F11/3466 , G06F2201/815 , G06F2201/86 , G06F2201/88
摘要： Techniques for monitoring a set of one or more event counters of application execution are provided. The techniques include constructing a virtual performance monitoring counter (VPMC) layer as a unified abstraction of a physical performance monitoring counter (PMC) architecture, and incorporating one or more programming interfaces (PIs) in connection with the virtual performance monitoring counter, wherein the one or more programming interfaces facilitate simultaneous access and data monitoring across a set of one or more event counters.
摘要翻译：提供了用于监视应用执行的一个或多个事件计数器的集合的技术。这些技术包括构建虚拟性能监视计数器（VPMC）层作为物理性能监视计数器（PMC）体系结构的统一抽象，并且结合一个或多个与虚拟性能监视计数器结合的编程接口（PI），其中一个或更多的编程接口便于跨一组或多个事件计数器的同时访问和数据监视。

54. 发明授权

US08683418B2 Adaptive workload based optimizations to mitigate current delivery limitations in integrated circuits 有权
标题翻译：基于自适应工作负载的优化，以减轻集成电路中的当前传输限制
公开(公告)号：US08683418B2
公开(公告)日：2014-03-25
申请号：US13526230
申请日：2012-06-18
申请人： Pradip Bose , Alper Buyuktosunoglu , John A. Darringer , Moinuddin K. Qureshi , Jeonghee Shin
发明人： Pradip Bose , Alper Buyuktosunoglu , John A. Darringer , Moinuddin K. Qureshi , Jeonghee Shin
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： H01L23/00 , G06F11/00 , G06F11/3062 , H01L23/50 , H01L25/065 , H01L2224/16145 , H01L2224/16225
摘要： A dynamic system coupled with “pre-Silicon” design methodologies and “post-Silicon” current optimizing programming methodologies to improve and optimize current delivery into a chip, which is limited by the physical properties of the connections (e.g., Controlled Collapse Chip Connection or C4s). The mechanism consists of measuring or estimating power consumption at a certain granularity within a chip, converting the power information into C4 current information using a method, and triggering throttling mechanisms (including token based throttling) where applicable to limit the current delivery per C4 beyond pre-established limits or periods. Design aids are used to allocate C4s throughout the chip based on the current delivery requirements. The system coupled with design and programming methodologies improve and optimize current delivery is extendable to connections across layers in a multilayer 3D chip stack.
摘要翻译：与“前置硅”设计方法和“后硅”当前优化编程方法相结合的动态系统，以改进和优化当前传输到芯片的传输，这受到连接的物理特性的限制（例如，受控崩溃芯片连接或 C4s）。该机制包括测量或估计芯片内特定粒度的功耗，使用一种方法将功率信息转换为C4当前信息，并在适用的情况下触发限流机制（包括基于令牌的限制），以限制每个C4超过预先的当前传输 - 建立的限制或期限。设计辅助工具用于根据当前的交付要求在整个芯片上分配C4。该系统与设计和编程方法相结合，改进并优化电流传递可扩展到多层3D芯片堆叠中的层间连接。

55. 发明申请

US20140082580A1 CURRENT-AWARE FLOORPLANNING TO OVERCOME CURRENT DELIVERY LIMITATIONS IN INTEGRATED CIRCUITS 有权
标题翻译：集成电路中的当前流量限制的当前意义
公开(公告)号：US20140082580A1
公开(公告)日：2014-03-20
申请号：US13526194
申请日：2012-06-18
申请人： Pradip Bose , Alper Buyuktosunoglu , John A. Darringer , Moinuddin K. Qureshi , Jeonghee Shin
发明人： Pradip Bose , Alper Buyuktosunoglu , John A. Darringer , Moinuddin K. Qureshi , Jeonghee Shin
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/50 , G06F2217/78
摘要： A dynamic system coupled with “pre-Silicon” design methodologies and “post-Silicon” current optimizing programming methodologies to improve and optimize current delivery into a chip, which is limited by the physical properties of the connections (e.g., Controlled Collapse Chip Connection or C4s). The mechanism consists of measuring or estimating power consumption at a certain granularity within a chip, converting the power information into C4 current information using a method, and triggering throttling mechanisms (including token based throttling) where applicable to limit the current delivery per C4 beyond pre-established limits or periods. Design aids are used to allocate C4s throughout the chip based on the current delivery requirements. The system coupled with design and programming methodologies improve and optimize current delivery is extendable to connections across layers in a multilayer 3D chip stack.
摘要翻译：与“前置硅”设计方法和“后硅”当前优化编程方法相结合的动态系统，以改进和优化当前传输到芯片的传输，这受到连接的物理特性的限制（例如，受控崩溃芯片连接或 C4s）。该机制包括测量或估计芯片内特定粒度的功耗，使用一种方法将功率信息转换为C4当前信息，并在适用的情况下触发限流机制（包括基于令牌的限制），以限制每个C4超过预先的当前传输 - 建立的限制或期限。设计辅助工具用于根据当前的交付要求在整个芯片上分配C4。该系统与设计和编程方法相结合，改进并优化电流传递可扩展到多层3D芯片堆叠中的层间连接。

56. 发明授权

US08296773B2 Systems and methods for thread assignment and core turn-off for integrated circuit energy efficiency and high-performance 有权
标题翻译：用于线程分配和核心关断的集成电路能效和高性能的系统和方法
公开(公告)号：US08296773B2
公开(公告)日：2012-10-23
申请号：US12164775
申请日：2008-06-30
申请人： Pradip Bose , Alper Buyuktosunoglu , Eren Kursun
发明人： Pradip Bose , Alper Buyuktosunoglu , Eren Kursun
IPC分类号： G06F9/46 , G06F1/00
CPC分类号： G06F1/3203 , G06F1/3287 , G06F1/329 , G06F9/5094 , Y02D10/171 , Y02D10/22 , Y02D10/24
摘要： A system and method for improving efficiency of a multi-core architecture includes, in accordance with a workload, determining a number of cores to shut down based upon a metric that combines parameters to represent operational efficiency. Threads of the workload are reassigned to cores remaining active by assigning threads based on priority constraints and thread execution history to improve the operational efficiency of the multi-core architecture.
摘要翻译：用于提高多核架构的效率的系统和方法包括根据工作负载，基于组合参数以表示操作效率的度量来确定要关闭的多个内核。工作负载的线程通过基于优先级约束和线程执行历史分配线程来重新分配给保持活动的内核，以提高多核架构的运营效率。

57. 发明申请

US20120030481A1 Measuring Data Switching Activity in a Microprocessor 失效
标题翻译：测量微处理器中的数据切换活动
公开(公告)号：US20120030481A1
公开(公告)日：2012-02-02
申请号：US12844372
申请日：2010-07-27
申请人： Pradip Bose , Alper Buyuktosunoglu , Christopher J. Gonzalez , Moinuddin K. Qureshi , Victor Zyuban
发明人： Pradip Bose , Alper Buyuktosunoglu , Christopher J. Gonzalez , Moinuddin K. Qureshi , Victor Zyuban
IPC分类号： G06F1/26
CPC分类号： G06F1/3206 , G06F1/324 , G06F1/3296 , Y02D10/126
摘要： A mechanism is provided for approximating data switching activity in a data processing system. A data switching activity identification mechanism in the data processing system receives an identification of a set of data storage devices and a set of bits in the set of data storage devices in the data processing system to be monitored for the data switching activity. The data switching activity identification mechanism sums a count of the identified bits that have changed state for the data storage device along with other counts of the identified bits that have changed state for other data storage devices in the set of data storage devices to form an approximation of data switching activity. A power manager in the data processing system then adjusts a set of operational parameters associated with the data processing system using the approximation of data switching activity.
摘要翻译：提供了一种用于近似数据处理系统中的数据交换活动的机制。数据处理系统中的数据交换活动识别机制在数据处理系统中接收数据存储设备的集合的标识和数据存储设备中的一组位，以对数据交换活动进行监控。数据交换活动识别机制对数据存储装置的已改变状态的已识别比特的计数与数据存储装置中的其他数据存储装置的已改变状态的识别比特的其他计数相加以形成近似值的数据交换活动。数据处理系统中的电源管理器然后使用数据交换活动的近似来调整与数据处理系统相关联的一组操作参数。

58. 发明申请

US20100268930A1 ON-CHIP POWER PROXY BASED ARCHITECTURE 失效
标题翻译：基于芯片功率代理的架构
公开(公告)号：US20100268930A1
公开(公告)日：2010-10-21
申请号：US12749179
申请日：2010-03-29
申请人： Pradip Bose , Alper Buyuktosunoglu , Michael S. Floyd , Maria L. Pesantez
发明人： Pradip Bose , Alper Buyuktosunoglu , Michael S. Floyd , Maria L. Pesantez
IPC分类号： G06F9/00 , G06F1/00
CPC分类号： G06F1/3203 , G06F11/3062 , G06F11/3096 , Y02D10/126
摘要： The embodiments provide an assigned counter of a first set of counters and stores a value for an activity of a set of activities forming a set of stored values. The value comprises the count multiplied by a weight factor specific to the activity. A power manager manages the first set of counters, receives a set of activities to be monitored for a unit, groups the portion into subsets based on at least one of a frequency of occurrence of each activity and power consumption for each activity, sums the stored values corresponding to each activity in each subset to reach a total value for each subset, multiplies the total value of each subset by factor corresponding to the subset to form a scaled value for each subset, and sums the scaled value of each subset to form a power usage value.
摘要翻译：这些实施例提供了第一组计数器的分配的计数器，并且存储形成一组存储值的一组活动的活动的值。该值包括计数乘以活动特有的权重因子。功率管理器管理第一组计数器，接收一组要监视单元的活动，基于每个活动的发生频率和每个活动的功耗中的至少一个将该部分分组成子集，将所存储的对应于每个子集中的每个活动的值以达到每个子集的总值，将每个子集的总值乘以与该子集对应的因子，以形成每个子集的缩放值，并且将每个子集的缩放值相加以形成电力使用价值。

59. 发明申请

US20090328055A1 SYSTEMS AND METHODS FOR THREAD ASSIGNMENT AND CORE TURN-OFF FOR INTEGRATED CIRCUIT ENERGY EFFICIENCY AND HIGH-PERFORMANCE 有权
标题翻译：用于集成电路能量效率和高性能的螺纹分配和核心关闭的系统和方法
公开(公告)号：US20090328055A1
公开(公告)日：2009-12-31
申请号：US12164775
申请日：2008-06-30
申请人： Pradip Bose , Alper Buyuktosunoglu , Eren Kursun
发明人： Pradip Bose , Alper Buyuktosunoglu , Eren Kursun
IPC分类号： G06F9/50
CPC分类号： G06F1/3203 , G06F1/3287 , G06F1/329 , G06F9/5094 , Y02D10/171 , Y02D10/22 , Y02D10/24
摘要： A system and method for improving efficiency of a multi-core architecture includes, in accordance with a workload, determining a number of cores to shut down based upon a metric that combines parameters to represent operational efficiency. Threads of the workload are reassigned to cores remaining active by assigning threads based on priority constraints and thread execution history to improve the operational efficiency of the multi-core architecture.
摘要翻译：用于提高多核架构的效率的系统和方法包括根据工作负载，基于组合参数以表示操作效率的度量来确定要关闭的多个内核。工作负载的线程通过基于优先级约束和线程执行历史分配线程来重新分配给保持活动的内核，以提高多核架构的运行效率。

60. 发明授权

US07627742B2 Method and apparatus for conserving power by throttling instruction fetching when a processor encounters low confidence branches in an information handling system 失效
标题翻译：当处理器在信息处理系统中遇到低置信度分支时，通过节流指令获取来节省功率的方法和装置
公开(公告)号：US07627742B2
公开(公告)日：2009-12-01
申请号：US11733589
申请日：2007-04-10
申请人： Pradip Bose , Alper Buyuktosunoglu , Chen-Yong Cher , Michael Karl Gschwind , Ravi Nair , Robert Alan Philhower , Wolfram Sauer , Raymond Cheung Yeung
发明人： Pradip Bose , Alper Buyuktosunoglu , Chen-Yong Cher , Michael Karl Gschwind , Ravi Nair , Robert Alan Philhower , Wolfram Sauer , Raymond Cheung Yeung
IPC分类号： G06F1/32
CPC分类号： G06F9/3844 , G06F1/3203 , G06F9/3802 , G06F9/3806
摘要： An information handling system includes a processor that throttles the instruction fetcher whenever the inaccuracy, or lack of confidence, in branch predictions for branch instructions stored in a branch instruction queue exceeds a predetermined threshold confidence level of inaccuracy or error. In this manner, fetch operations slow down to conserve processor power when it is likely that the processor will mispredict the outcome of branch instructions. Fetch operations return to full speed when it is likely that the processor will correctly predict the outcome of branch instructions.
摘要翻译：一种信息处理系统包括处理器，每当对分支指令队列中存储的分支指令的分支预测中的不准确性或缺乏置信度的不准确性或缺乏置信度超过预定的不准确度或误差的阈值置信水平时，可以节制指令获取器。以这种方式，当处理器可能会错误地预测分支指令的结果时，获取操作减慢以节省处理器功率。当处理器可能正确预测分支指令的结果时，获取操作将返回全速。

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