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51. 发明授权

US08174294B1 Configurable buffer circuits and methods 有权
标题翻译：可配置缓冲电路和方法
公开(公告)号：US08174294B1
公开(公告)日：2012-05-08
申请号：US12910177
申请日：2010-10-22
申请人： Weiqi Ding , Yanjing Ke , Sergey Shumarayev
发明人： Weiqi Ding , Yanjing Ke , Sergey Shumarayev
IPC分类号： H03B1/00
CPC分类号： H04L25/0272
摘要： A buffer circuit includes a current source circuit, first and second switch circuits that are coupled to the current source circuit, a first resistor coupled to the first switch circuit, a second resistor coupled to the second switch circuit, and a third switch circuit coupled to the first and the second resistors. The third switch circuit couples the first and the second resistors to a node at a first voltage when the buffer circuit is configured to function in a current mode logic buffer mode. The third switch circuit couples the first and the second resistors to a node at a second voltage when the buffer circuit is configured to function in an H-bridge buffer mode.
摘要翻译：缓冲电路包括电流源电路，耦合到电流源电路的第一和第二开关电路，耦合到第一开关电路的第一电阻器，耦合到第二开关电路的第二电阻器和耦合到第二开关电路的第三开关电路，第一和第二电阻。当缓冲电路被配置为以当前模式逻辑缓冲器模式工作时，第三开关电路将第一和第二电阻器耦合到第一电压的节点。当缓冲电路被配置为以H桥缓冲器模式工作时，第三开关电路将第一和第二电阻器耦合到第二电压的节点。

52. 发明授权

US08120429B1 Voltage-controlled oscillator methods and apparatus 有权
标题翻译：压控振荡器的方法和装置
公开(公告)号：US08120429B1
公开(公告)日：2012-02-21
申请号：US12787722
申请日：2010-05-26
申请人： Tim Tri Hoang , Wilson Wong , Kazi Asaduzzaman , Simardeep Maangat , Sergey Shumarayev , Rakesh H. Patel
发明人： Tim Tri Hoang , Wilson Wong , Kazi Asaduzzaman , Simardeep Maangat , Sergey Shumarayev , Rakesh H. Patel
IPC分类号： H03L7/00 , H03K3/03
CPC分类号： H03L7/0995 , H03K3/0322 , H03K3/35613 , H03K2005/00228 , H03K2005/00234
摘要： Methods and apparatus are provided for generating a clock signal with relatively high bandwidth and relatively low phase noise. A circuit of the invention can include a pair of transistors serially coupled between a signal of relatively high voltage and a source of relatively low voltage, where a voltage of the signal of relatively high voltage can vary according to a voltage of a variable control signal. A gate of one of the pair of transistors can be coupled to an input clock signal, and an output node between the pair of transistors can be coupled to an output clock signal. The circuit can also include a third transistor, whose drain and source are coupled to the output clock signal, and whose gate can be coupled to a gear input signal. This circuit can advantageously operate under at least two different gears, each with different bandwidth and phase noise characteristics.
摘要翻译：提供了用于产生具有相对较高带宽和相对较低相位噪声的时钟信号的方法和装置。本发明的电路可以包括串联耦合在相对高电压的信号和相对低电压的源之间的一对晶体管，其中相对高电压的信号的电压可以根据可变控制信号的电压而变化。一对晶体管中的一个的栅极可以耦合到输入时钟信号，并且该对晶体管之间的输出节点可以耦合到输出时钟信号。电路还可以包括第三晶体管，其漏极和源极耦合到输出时钟信号，并且其栅极可以耦合到齿轮输入信号。该电路可以有利地在至少两个不同的齿轮下运行，每个齿轮具有不同的带宽和相位噪声特性。

53. 发明授权

US08098724B2 Automatic calibration in high-speed serial interface receiver circuitry 有权
标题翻译：高速串行接口电路自动校准
公开(公告)号：US08098724B2
公开(公告)日：2012-01-17
申请号：US12287009
申请日：2008-10-02
申请人： Sergey Shumarayev , Wilson Wong
发明人： Sergey Shumarayev , Wilson Wong
IPC分类号： H03H7/30 , H03H7/40 , H03K5/159
CPC分类号： H04L25/03885 , H04B3/04 , H04L1/205 , H04L25/03019
摘要： Circuitry for receiving a serial data signal (e.g., a high-speed serial data signal) includes adjustable equalizer circuitry for producing an equalized version of the serial data signal. The equalizer circuitry may include controllably variable DC gain and controllably variable AC gain. The circuitry may further include eye height and eye width monitor circuitry for respectively producing first and second output signals indicative of the height and width of the eye of the equalized version. The first output signal may be used in control of the DC gain of the equalizer circuitry, and the second output signal may be used in control of the AC gain of the equalizer circuitry.
摘要翻译：用于接收串行数据信号（例如，高速串行数据信号）的电路包括用于产生串行数据信号的均衡版本的可调均衡器电路。均衡器电路可以包括可控制的可变DC增益和可控可变的AC增益。电路还可以包括眼睛高度和眼睛宽度监视器电路，用于分别产生指示均衡版本的眼睛的高度和宽度的第一和第二输出信号。第一输出信号可用于控制均衡器电路的直流增益，并且第二输出信号可用于控制均衡器电路的AC增益。

54. 发明申请

US20110235756A1 SIGNAL LOSS DETECTOR FOR HIGH-SPEED SERIAL INTERFACE OF A PROGRAMMABLE LOGIC DEVICE 有权
标题翻译：用于可编程逻辑器件高速串行接口的信号丢失检测器
公开(公告)号：US20110235756A1
公开(公告)日：2011-09-29
申请号：US13151717
申请日：2011-06-02
申请人： Weiqi Ding , Sergey Shumarayev , Wilson Wong , Thungoc M. Tran , Tim Tri Hoang
发明人： Weiqi Ding , Sergey Shumarayev , Wilson Wong , Thungoc M. Tran , Tim Tri Hoang
IPC分类号： H04L27/06
CPC分类号： H04L25/45
摘要： A loss-of-signal detector includes digital and analog monitoring of incoming data. The incoming signal is compared digitally to at least one predetermined pattern that may indicate a loss of signal, and also is monitored by an analog detector that detects transitions in the data. If the digital comparison fails to match any of the at least one predetermined pattern, or if transitions are detected by the analog monitoring, even if the digital comparison produces a pattern match, then loss of signal is not indicated.
摘要翻译：信号丢失检测器包括对输入数据进行数字和模拟监测。输入信号被数字地比较为可以指示信号丢失的至少一个预定模式，并且还由检测数据中的转换的模拟检测器监视。如果数字比较不能匹配至少一个预定模式中的任何一个，或者如果通过模拟监视检测到转换，即使数字比较产生模式匹配，则不指示信号丢失。

55. 发明申请

US20110188621A1 CLOCK AND DATA RECOVERY CIRCUITRY WITH AUTO-SPEED NEGOTIATION AND OTHER POSSIBLE FEATURES 有权
标题翻译：时钟和数据恢复电路与自动调速和其他可能的特性
公开(公告)号：US20110188621A1
公开(公告)日：2011-08-04
申请号：US12700433
申请日：2010-02-04
申请人： Kazi Asaduzzaman , Tim Tri Hoang , Tin H. Lai , Shou-Po Shih , Sergey Shumarayev
发明人： Kazi Asaduzzaman , Tim Tri Hoang , Tin H. Lai , Shou-Po Shih , Sergey Shumarayev
IPC分类号： H04L7/00
CPC分类号： H03L7/08 , H03L7/0807 , H03L7/0814 , H03L7/087 , H03L7/0898 , H03L7/099 , H03L7/183 , H04L7/0337
摘要： An integrated circuit (“IC”) may include clock and data recovery (“CDR”) circuitry for recovering data information from an input serial data signal. The CDR circuitry may include a reference clock loop and a data loop. A retimed (recovered) data signal output by the CDR circuitry is monitored by other control circuitry on the IC for a communication change request contained in that signal. Responsive to such a request, the control circuitry can change an operating parameter of the CDR circuitry (e.g., a frequency division factor used in either of the above-mentioned loops). This can help the IC support communication protocols that employ auto-speed negotiation.
摘要翻译：集成电路（“IC”）可以包括用于从输入串行数据信号恢复数据信息的时钟和数据恢复（“CDR”）电路。 CDR电路可以包括参考时钟环路和数据环路。由CDR电路输出的重新定时（恢复）数据信号由IC上的其它控制电路监视用于包含在该信号中的通信改变请求。响应于这种请求，控制电路可以改变CDR电路的操作参数（例如，在上述任何一个循环中使用的分频因子）。这可以帮助IC支持采用自动速度协商的通信协议。

56. 发明授权

US07940814B2 Heterogeneous transceiver architecture for wide range programmability of programmable logic devices 有权
标题翻译：异构收发器架构，用于可编程逻辑器件的广泛可编程性
公开(公告)号：US07940814B2
公开(公告)日：2011-05-10
申请号：US12576507
申请日：2009-10-09
申请人： Sergey Shumarayev , Bill W. Bereza , Chong H. Lee , Rakesh H. Patel , Wilson Wong
发明人： Sergey Shumarayev , Bill W. Bereza , Chong H. Lee , Rakesh H. Patel , Wilson Wong
IPC分类号： H04J3/04
CPC分类号： H04L5/14 , H03K19/17744 , H04L27/00
摘要： High-speed serial data transceiver circuitry on a programmable logic device (“PLD”) includes some channels that are able to operate at data rates up to a first, relatively low maximum data rate, and other channels that are able to operate at data rates up to a second, relatively high maximum data rate. The relatively low-speed channels are served by relatively low-speed phase locked loop (“PLL”) circuitry, and have other circuit components that are typically needed for handling data that is transmitted at relatively low data rates. The relatively high-speed channels are served by relatively high-speed PLLs, and have other circuit components that are typically needed for handling data that is transmitted at relatively high data rates.
摘要翻译：可编程逻辑器件（“PLD”）上的高速串行数据收发器电路包括一些能够以高达第一，相对较低的最大数据速率的数据速率工作的通道，以及能够以数据速率操作的其他通道达到第二个相对较高的最大数据速率。相对低速的通道由相对低速的锁相环（“PLL”）电路服务，并且具有通常用于处理以相对低的数据速率发送的数据所需的其他电路组件。相对高速的信道由相对高速的PLL服务，并且具有通常用于处理以相对高的数据速率传输的数据所需的其他电路部件。

57. 发明授权

US07903679B1 Power supply filtering for programmable logic device having heterogeneous serial interface architecture 有权
标题翻译：具有异构串行接口架构的可编程逻辑器件的电源滤波
公开(公告)号：US07903679B1
公开(公告)日：2011-03-08
申请号：US11622396
申请日：2007-01-11
申请人： Sergey Shumarayev , Wilson Wong , Thungoc M. Tran , Tim Tri Hoang
发明人： Sergey Shumarayev , Wilson Wong , Thungoc M. Tran , Tim Tri Hoang
IPC分类号： H04L12/56
CPC分类号： H03K19/17744
摘要： In a programmable logic device with a number of different types of serial interfaces, different power supply filtering schemes are applied to different interfaces. For interfaces operating at the lowest data rates—e.g., 1 Gbps—circuit-board level filtering including one or more decoupling capacitors may be provided. For interfaces operating at somewhat higher data rates—e.g., 3 Gbps—modest on-package filtering also may be provided, which may include power-island decoupling. For interfaces operating at still higher data rates—e.g., 6 Gbps—more substantial on-package filtering, including one or more on-package decoupling capacitors, also may be provided. For interfaces operating at the highest data rates—e.g., 10 Gbps—on-die filtering, which may include one or more on-die filtering or regulating networks, may be provided. The on-die regulators may be programmably bypassable allowing a user to trade off performance for power savings.
摘要翻译：在具有多种不同类型的串行接口的可编程逻辑器件中，不同的电源滤波方案被应用于不同的接口。对于以最低数据速率操作的接口，例如，可以提供包括一个或多个去耦电容器的1Gbps电路板电平滤波器。对于以较高数据速率工作的接口，例如，也可以提供3 Gbps适度的封装内滤波，这可能包括功率岛解耦。对于以更高的数据速率运行的接口，例如，也可以提供包括一个或多个封装内去耦电容器的6Gbps更实质的封装内滤波。对于以最高数据速率工作的接口，例如，可以提供10Gbps片上滤波，其可以包括一个或多个片上滤波或调节网络。片上调节器可以可编程地旁路，允许用户权衡功能以节省功率。

58. 发明授权

US07834712B2 Techniques for providing option conductors to connect components in an oscillator circuit 有权
标题翻译：提供选项导体以连接振荡器电路中的组件的技术
公开(公告)号：US07834712B2
公开(公告)日：2010-11-16
申请号：US12277810
申请日：2008-11-25
申请人： Sergey Shumarayev , Wilson Wong , Allen Chan , Ali Atesoglu
发明人： Sergey Shumarayev , Wilson Wong , Allen Chan , Ali Atesoglu
IPC分类号： H03B5/00
CPC分类号： H03B5/1228 , H03B5/1215 , H03B5/1243 , H03B5/1265 , H03B2201/011
摘要： An oscillator circuit includes transistors that are cross-coupled through routing conductors in a first conductive layer. The oscillator circuit also includes a varactor, a capacitor, and an option conductor in a second conductive layer. The option conductor forms at least a portion of a connection between one of the transistors and the capacitor or the varactor.
摘要翻译：振荡器电路包括通过第一导电层中的路由导体交叉耦合的晶体管。振荡器电路还包括第二导电层中的变容二极管，电容器和选项导体。选项导体形成晶体管之一和电容器或变容二极管之间的连接的至少一部分。

59. 发明授权

US07812659B1 Clock signal circuitry for multi-channel data signaling 有权
标题翻译：用于多通道数据信号的时钟信号电路
公开(公告)号：US07812659B1
公开(公告)日：2010-10-12
申请号：US11432420
申请日：2006-05-10
申请人： Sergey Shumarayev , Rakesh H Patel , William W Bereza , Tim Tri Hoang , Thungoc Tran
发明人： Sergey Shumarayev , Rakesh H Patel , William W Bereza , Tim Tri Hoang , Thungoc Tran
IPC分类号： G06F1/04 , H04L7/00
CPC分类号： H03L7/22 , G06F1/06
摘要： A programmable logic device (“PLD”) or the like has a plurality of data transmitter channels. Certain circuitry is shared by the channels. The shared circuitry includes at least one phase-locked loop (“PLL”) circuit for producing a primary clock signal, and global frequency divider circuitry for producing at least one global secondary clock signal based on the primary signal. The primary and global secondary signal(s) are distributed to the channels. Each of the channels includes local frequency divider circuitry for producing at least one local secondary clock signal based on the primary signal. Each channel also includes selection circuitry for selecting either the global or local secondary signal(s) for use by clock utilization circuitry of the channel. The clock utilization circuitry may include serializer circuitry for converting data from parallel to serial form.
摘要翻译：可编程逻辑器件（“PLD”）等具有多个数据发送器通道。某些电路由通道共享。共享电路包括用于产生主时钟信号的至少一个锁相环（“PLL”）电路和用于基于主信号产生至少一个全局辅助时钟信号的全局分频器电路。主要和全局辅助信号被分配到信道。每个通道包括本地分频器电路，用于基于主信号产生至少一个本地辅助时钟信号。每个通道还包括选择电路，用于选择由信道的时钟利用电路使用的全局或局部辅助信号。时钟利用电路可以包括用于将数据从并行转换为串行形式的串行化器电路。

60. 发明授权

US07812634B1 Programmable logic device transceiver architectures that facilitate using various numbers of transceiver channels together 有权
标题翻译：可编程逻辑器件收发器架构，便于将各种数量的收发器通道一起使用
公开(公告)号：US07812634B1
公开(公告)日：2010-10-12
申请号：US11726471
申请日：2007-03-21
申请人： Sergey Shumarayev , Thungoc M. Tran , Tim Tri Hoang
发明人： Sergey Shumarayev , Thungoc M. Tran , Tim Tri Hoang
IPC分类号： H03K19/173
CPC分类号： H03K19/17736 , H03K19/1774 , H03K19/17744
摘要： Transceiver circuitry on a programmable logic device integrated circuit (“PLD”) is preferably provided in a plurality of identical or at least similar modules. Each module preferably includes a plurality of transceiver channels and a clock source unit. Clock distribution circuitry is provided for distributing the signal of a module's clock source to all of the transceiver channels in that module, and also selectively beyond that module to other modules.
摘要翻译：可编程逻辑器件集成电路（“PLD”）上的收发器电路优选地设置在多个相同或至少相似的模块中。每个模块优选地包括多个收发器通道和时钟源单元。提供时钟分配电路用于将模块的时钟源的信号分配给该模块中的所有收发器通道，并且还选择性地超出该模块到其他模块。

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