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51. 发明授权

US09014326B2 Flip-flop, shift register, display drive circuit, display apparatus, and display panel 有权
标题翻译：触发器，移位寄存器，显示驱动电路，显示装置和显示面板
公开(公告)号：US09014326B2
公开(公告)日：2015-04-21
申请号：US13378214
申请日：2010-03-26
申请人： Yuhichiroh Murakami , Shige Furuta , Yasushi Sasaki , Makoto Yokoyama , Takahiro Yamaguchi
发明人： Yuhichiroh Murakami , Shige Furuta , Yasushi Sasaki , Makoto Yokoyama , Takahiro Yamaguchi
IPC分类号： H03K3/356 , G11C19/00 , G09G3/36 , G11C19/28
CPC分类号： G09G3/3677 , G09G3/3655 , G09G3/3688 , G09G2300/0876 , G09G2310/0286 , G11C19/28 , H03K3/356104
摘要： A flip-flop includes: a first, second, third, and fourth transistors; input terminals; and first and second output terminals, the first and second transistors constituting a first CMOS circuit such that gate terminals are connected and drain terminals are connected, the third and fourth transistors constituting a second CMOS circuit such that gate terminals are connected and drain terminals are connected, the first output terminal connected to a gate side of the first CMOS circuit and a drain side of the second CMOS circuit, the second output terminal connected to a gate side of the second CMOS circuit and a drain side of the first CMOS circuit, at least one input transistor included in the group of the first through fourth transistors, a source terminal of the input transistor being connected to one of the input terminals. This can provide a further compact flip-flop.
摘要翻译：触发器包括：第一，第二，第三和第四晶体管; 输入端子; 以及第一和第二输出端子，构成第一CMOS电路的第一和第二晶体管使得栅极端子连接并且漏极端子连接，第三和第四晶体管构成第二CMOS电路，使得栅极端子连接并且漏极端子被连接连接到第一CMOS电路的栅极侧的第一输出端子和第二CMOS电路的漏极侧，第二输出端子连接到第二CMOS电路的栅极侧和第一CMOS电路的漏极侧，包括在第一至第四晶体管组中的至少一个输入晶体管，输入晶体管的源极端子连接到输入端子之一。这可以提供更紧凑的触发器。

52. 发明授权

US08890856B2 Display driving circuit, display device and display driving method 有权
标题翻译：显示驱动电路，显示装置及显示驱动方式
公开(公告)号：US08890856B2
公开(公告)日：2014-11-18
申请号：US13375311
申请日：2010-02-24
申请人： Yasushi Sasaki , Yuhichiroh Murakami , Shige Furuta , Makoto Yokoyama
发明人： Yasushi Sasaki , Yuhichiroh Murakami , Shige Furuta , Makoto Yokoyama
IPC分类号： G09G5/00 , G09G3/36
CPC分类号： G09G3/3677 , G09G3/3614 , G09G3/3655 , G09G2300/0852 , G09G2300/0876 , G09G2310/0286
摘要： A display driving circuit that carries out CC driving is configured such that retaining circuits are provided in such a way as to correspond one-by-one to their respective stages of a shift register, that a polarity signal CMI is inputted to each of the latch circuits, that when an internal signal Mn generated by a shift register at the nth stage becomes active, a latch circuit corresponding to the nth stage loads and retains the polarity signal CMI, that an output signal SRBOn from the shift register at the nth stage is supplied as a scanning signal to a gate line connected to pixels corresponding to the (n+1)th stage, and that an output from latch circuit corresponding to the nth stage is supplied as CSOUTn to a CS bus line forming capacitors with pixel electrodes of pixels corresponding to the nth stage.
摘要翻译：执行CC驱动的显示驱动电路被配置为使得保持电路以与移位寄存器的各个级逐个对应的方式被提供，极性信号CMI被输入到每个锁存器电路，当第n级的移位寄存器产生的内部信号Mn变为有效时，对应于第n级的锁存电路加载并保持极性信号CMI，来自第n级的移位寄存器的输出信号SRB0n为作为扫描信号提供给连接到对应于第（n + 1）级的像素的栅极线，并且将与第n级相对应的锁存电路的输出作为CSOUTn提供给形成具有像素电极的电容器的CS总线对应于第n级的像素。

53. 发明授权

US08587572B2 Storage capacitor line drive circuit and display device 有权
标题翻译：存储电容线路驱动电路和显示装置
公开(公告)号：US08587572B2
公开(公告)日：2013-11-19
申请号：US12734376
申请日：2008-08-21
申请人： Yasushi Sasaki , Yuhichiroh Murakami , Makoto Yokoyama , Shige Furuta
发明人： Yasushi Sasaki , Yuhichiroh Murakami , Makoto Yokoyama , Shige Furuta
IPC分类号： G06F3/038 , G09G5/00 , G09G3/30 , G09G3/36
CPC分类号： G09G3/3655 , G09G3/3614 , G09G3/3677 , G09G2300/0876 , G09G2310/0286 , G09G2320/0209 , G09G2320/0219 , G11C19/184
摘要： In a storage capacitor line drive circuit driving a storage capacitor line of an active-matrix display device and driven by outputs of a scanning signal line drive circuit, at least one (VSS) of a high-potential supply voltage (VDD) and a low-potential supply voltage (VSS) differs from a supply voltage (GVSS) of a corresponding logical level of the scanning signal line drive circuit, the high-potential supply voltage and the low-potential supply voltage being used for generating a signal voltage of a preceding stage to an output stage. This makes it possible to achieve a storage capacitor line drive circuit capable of avoiding malfunctioning even in a case where the storage capacitor line drive circuit receives noise from a scanning signal line, and a display device including the storage capacitor line drive circuit.
摘要翻译：在驱动有源矩阵型显示装置的辅助电容线并由扫描信号线驱动电路的输出驱动的辅助电容线驱动电路中，高电位电源电压（VDD）和低电位电位电压（VSS）与扫描信号线驱动电路的相应逻辑电平的电源电压（GVSS）不同，高电位电源电压和低电位电源电压用于产生信号电压前一阶段到产出阶段。这使得即使在存储电容器线路驱动电路从扫描信号线接收到噪声的情况下也可以实现能够避免故障的存储电容器线路驱动电路，以及包括辅助电容线驱动电路的显示装置。

54. 发明申请

US20130100105A1 SIGNAL GENERATOR CIRCUIT, LIQUID CRYSTAL DISPLAY DEVICE 审中-公开
标题翻译：信号发生器电路，液晶显示装置
公开(公告)号：US20130100105A1
公开(公告)日：2013-04-25
申请号：US13806878
申请日：2011-06-23
申请人： Shige Furuta , Makoto Yokoyama , Yuhichiroh Murakami , Yasushi Sasaki
发明人： Shige Furuta , Makoto Yokoyama , Yuhichiroh Murakami , Yasushi Sasaki
IPC分类号： G09G3/36
CPC分类号： G09G3/3674 , G09G3/3614 , G09G3/3648 , G09G3/3655 , G09G3/3677
摘要： A signal generator circuit of the present invention is a signal generator circuit for use in a display device, the display device including (a) a pixel having a pixel electrode, (b) an electric conductor with which the pixel electrode forms a capacitor, (c) a data signal line driving circuit which outputs a data signal whose polarity is reversed for each n horizontal scanning period(s), where n is a natural number, and (d) a scanning signal line driving circuit which outputs scanning signals corresponding to respective stages, said signal generator circuit generating a drive signal supplied to the electric conductor, wherein: said signal generator circuit comprises flip flops corresponding to the respective stages, each flip flop including a gate circuit and a latch circuit; and in regard to one flip flop corresponding to one of the stages, (i) the gate circuit is supplied with a signal synchronized with a scanning signal corresponding to a preceding stage of the one of the stages, and a signal synchronized with a scanning signal corresponding to a subsequent stage of the one of the stages, (ii) the latch circuit is supplied with a polarity signal whose polarity is reversed for each n horizontal scanning period(s) via the gate circuit, and (iii) the drive signal of the one of the stages is generated in accordance with an output of the one flip flop. With the arrangement, it is possible to provide, with use of a simple configuration, a driver circuit for use in a liquid crystal display device which carries out CC (charge coupling) driving or COM driving.
摘要翻译：本发明的信号发生器电路是用于显示装置的信号发生器电路，该显示装置包括：（a）具有像素电极的像素，（b）像素电极与电容器形成的电导体; c）数据信号线驱动电路，其输出对于每个n个水平扫描周期的极性反转的数据信号，其中n是自然数，以及（d）扫描信号线驱动电路，其输出与所述信号发生器电路产生提供给所述电导体的驱动信号，其中：所述信号发生器电路包括对应于各个级的触发器，每个触发器包括门电路和锁存电路; 并且对于与其中一个级相对应的一个触发器，（i）门电路被提供与与该级中的一级的前级相对应的扫描信号同步的信号，以及与扫描信号同步的信号对应于所述一级的后续级，（ii）锁存电路经由门电路为每个n个水平扫描周期极性反转极性信号，以及（iii）驱动信号根据一个触发器的输出产生一个级。通过这种布置，可以使用简单的配置来提供用于执行CC（电荷耦合）驱动或COM驱动的液晶显示装置中的驱动电路。

55. 发明申请

US20120306829A1 SHIFT REGISTER, SIGNAL LINE DRIVE CIRCUIT, LIQUID CRYSTAL DISPLAY DEVICE 有权
标题翻译：移位寄存器，信号线驱动电路，液晶显示装置
公开(公告)号：US20120306829A1
公开(公告)日：2012-12-06
申请号：US13575490
申请日：2011-02-10
申请人： Shige Furuta , Yuhichiroh Murakami , Yasushi Sasaki , Takahiro Yamaguchi , Seijirou Gyouten
发明人： Shige Furuta , Yuhichiroh Murakami , Yasushi Sasaki , Takahiro Yamaguchi , Seijirou Gyouten
IPC分类号： G11C19/00 , G09G3/36 , G06F3/038
CPC分类号： G11C19/28 , G09G3/3677
摘要： A shift register includes a plurality of stages of unit circuits each including a flip-flop. Each of the unit circuits generates, by obtaining a sync signal in accordance with an output from the flip-flop, an output signal. The flip-flop includes a first switch and a second switch and a latch circuit for latching a signal supplied thereto and outputting the signal as the output from the flip-flop. A first shift direction signal is supplied to the latch circuit via the first switch, and the second shift direction signal is supplied to the latch circuit via the second switch. In each unit circuit other than those of the first and last stages, an output signal from a previous stage is supplied to a control terminal of the first switch, and an output signal from a subsequent stage is supplied to a control terminal of the second switch.
摘要翻译：移位寄存器包括多个阶段的单元电路，每个单元电路包括一个触发器。每个单元电路通过根据触发器的输出获得同步信号来产生输出信号。触发器包括第一开关和第二开关以及用于锁存提供给其的信号的锁存电路，并将该信号作为触发器的输出输出。第一移位方向信号通过第一开关提供给锁存电路，第二移位方向信号通过第二开关提供给锁存电路。在除了第一级和最后级之外的每个单元电路中，来自前一级的输出信号被提供给第一开关的控制端，并且来自后级的输出信号被提供给第二开关的控制端。

56. 发明申请

US20120176393A1 MEMORY DEVICE, DISPLAY DEVICE EQUIPPED WITH MEMORY DEVICE, DRIVE METHOD FOR MEMORY DEVICE, AND DRIVE METHOD FOR DISPLAY DEVICE 审中-公开
标题翻译：存储装置，具有存储装置的显示装置，用于存储装置的驱动方法和用于显示装置的驱动方法
公开(公告)号：US20120176393A1
公开(公告)日：2012-07-12
申请号：US13395977
申请日：2010-04-23
申请人： Hiroyuki Ohkawa , Yasushi Sasaki , Yuhichiroh Murakami , Shige Furuta , Seijirou Gyouten , Shuji Nishi
发明人： Hiroyuki Ohkawa , Yasushi Sasaki , Yuhichiroh Murakami , Shige Furuta , Seijirou Gyouten , Shuji Nishi
IPC分类号： G09G5/36 , G11C5/02
CPC分类号： G09G3/3648 , G09G2300/0852 , G09G2300/0857 , G09G2310/06 , G09G2320/0219
摘要： Provided is a memory device that allows an amount of leakage into a first retaining section to which a binary logic level is written to be balanced between different circuit states. A predetermined period is set in which in a state where a first control section turns off an output element, (i) a first retaining section and a second retaining section retain an identical binary logic level, (ii) an electric potential of a voltage supply is set to one of a first electric potential level and a second electric potential level, (iii) the other one of the first electric potential level and the second electric potential level is supplied from a column driver to a fourth wire, and (iv) subsequently the fourth wire is shifted to a floating state.
摘要翻译：提供了一种存储器件，其允许向写入二进制逻辑电平的第一保持部分的泄漏量在不同的电路状态之间平衡。设定规定期间，其中在第一控制部分关闭输出元件的状态下，（i）第一保持部分和第二保持部分保持相同的二进制逻辑电平，（ii）电压源的电位被设置为第一电位电平和第二电位电平之一，（iii）第一电位电平和第二电位电平中的另一个从列驱动器提供给第四线，以及（iv）随后第四根线移动到浮动状态。

57. 发明申请

US20120169750A1 DISPLAY DEVICE AND DRIVE METHOD FOR DISPLAY DEVICE 审中-公开
标题翻译：用于显示装置的显示装置和驱动方法
公开(公告)号：US20120169750A1
公开(公告)日：2012-07-05
申请号：US13394606
申请日：2010-04-23
申请人： Yuhichiroh Murakami , Yasushi Sasaki , Shige Furuta , Seijirou Gyouten , Shuji Nishi
发明人： Yuhichiroh Murakami , Yasushi Sasaki , Shige Furuta , Seijirou Gyouten , Shuji Nishi
IPC分类号： G09G5/39
CPC分类号： G09G3/3659 , G02F1/13624 , G09G2300/0842 , G09G2300/0861 , G09G2330/022
摘要： Provided are a memory-type display device capable of improving image quality during a normal mode and a method for driving such a display device. Each memory circuit (MR1) includes: a node (PIX) (pixel electrode); a node (MRY) (memory electrode); a switch circuit (SW1); a first data-retention section (DS1) composed of a capacitor (Ca1); a data transfer section (TS1) composed of a transistor (N2); a second data-retention section (DS2) composed of a capacitor (Cb1); and a refresh output control section (RS1) including a transistor (N4). During the normal mode, and the capacitor (Ca1) and the capacitor (Cb1) are both used as auxiliary capacitors with the transistor (N2) in a conductive state and the transistor (N4) in a cutoff state.
摘要翻译：提供了能够在正常模式下提高图像质量的记忆型显示装置以及用于驱动这种显示装置的方法。每个存储器电路（MR1）包括：节点（PIX）（像素电极）; 节点（MRY）（记忆电极）; 开关电路（SW1）; 由电容器（Ca1）组成的第一数据保持部（DS1）; 由晶体管（N2）构成的数据传送部（TS1）; 由电容器（Cb1）构成的第二数据保持部（DS2）; 以及包括晶体管（N4）的刷新输出控制部分（RS1）。在正常模式期间，电容器（Ca1）和电容器（Cb1）都用作具有导通状态的晶体管（N2）和晶体管（N4）处于截止状态的辅助电容器。

58. 发明申请

US20120169690A1 DISPLAY DEVICE AND DRIVE METHOD FOR DISPLAY DEVICE 有权
标题翻译：用于显示装置的显示装置和驱动方法
公开(公告)号：US20120169690A1
公开(公告)日：2012-07-05
申请号：US13395697
申请日：2010-04-23
申请人： Yasushi Sasaki , Yuhichiroh Murakami , Shige Furuta , Seijirou Gyouten , Shuji Nishi
发明人： Yasushi Sasaki , Yuhichiroh Murakami , Shige Furuta , Seijirou Gyouten , Shuji Nishi
IPC分类号： G09G3/36 , G09G5/00
CPC分类号： G09G3/3607 , G09G3/3614 , G09G3/3618 , G09G3/3655 , G09G3/3659 , G09G2300/0814 , G09G2300/0823 , G09G2300/0842 , G09G2300/0852 , G09G2300/0861 , G09G2320/0219 , G09G2330/021 , G09G2330/022
摘要： Provided are a display device capable of preventing image noise arising from changes in potential of a common electrode and auxiliary capacitor lines at the time of a switch between a normal mode and a memory mode and a method for driving such a display device. In a case where it is necessary to cause the common electrode and the auxiliary capacitor lines to change in potential along with a switch between the normal mode and the memory mode, the change in potential is made while electrically connecting a node of each memory circuit to a corresponding source line with the corresponding source line having its potential fixed and with the memory circuit having its a switch circuit in a conductive state.
摘要翻译：提供了能够防止在正常模式和存储模式之间的切换时由公共电极和辅助电容器线的电位变化引起的图像噪声的显示装置以及用于驱动这种显示装置的方法。在需要使公共电极和辅助电容线与正常模式和存储模式之间的切换一起改变电位的情况下，在将每个存储器电路的节点电连接到对应的源极线，其相应的源极线具有其电位固定，并且存储电路具有其导通状态的开关电路。

59. 发明申请

US20120086686A1 DISPLAY DRIVING CIRCUIT, DISPLAY DEVICE AND DISPLAY DRIVING METHOD 有权
标题翻译：显示驱动电路，显示设备和显示驱动方法
公开(公告)号：US20120086686A1
公开(公告)日：2012-04-12
申请号：US13375311
申请日：2010-02-24
申请人： Yasushi Sasaki , Yuhichiroh Murakami , Shige Furuta , Makoto Yokoyama
发明人： Yasushi Sasaki , Yuhichiroh Murakami , Shige Furuta , Makoto Yokoyama
IPC分类号： G09G3/36 , G06F3/038
CPC分类号： G09G3/3677 , G09G3/3614 , G09G3/3655 , G09G2300/0852 , G09G2300/0876 , G09G2310/0286
摘要： A display driving circuit that carries out CC driving is configured such that retaining circuits are provided in such a way as to correspond one-by-one to their respective stages of a shift register, that a polarity signal CMI is inputted to each of the latch circuits, that when an internal signal Mn generated by a shift register at the nth stage becomes active, a latch circuit corresponding to the nth stage loads and retains the polarity signal CMI, that an output signal SRBOn from the shift register at the nth stage is supplied as a scanning signal to a gate line connected to pixels corresponding to the (n+1)th stage, and that an output from latch circuit corresponding to the nth stage is supplied as CSOUTn to a CS bus line forming capacitors with pixel electrodes of pixels corresponding to the nth stage.
摘要翻译：执行CC驱动的显示驱动电路被配置为使得保持电路以与移位寄存器的各个级逐个对应的方式被提供，极性信号CMI被输入到每个锁存器电路，当第n级的移位寄存器产生的内部信号Mn变为有效时，对应于第n级的锁存电路加载并保持极性信号CMI，来自第n级的移位寄存器的输出信号SRB0n为作为扫描信号提供给连接到与第（n + 1）级相对应的像素的栅极线，并且将与第n级对应的锁存电路的输出作为CSOUTn提供给形成具有像素电极的电容器的CS总线对应于第n级的像素。

60. 发明申请

US20100259529A1 POWER SUPPLY CIRCUIT AND DISPLAY DEVICE INCLUDING THE SAME 有权
标题翻译：电源电路和包括其的显示装置
公开(公告)号：US20100259529A1
公开(公告)日：2010-10-14
申请号：US12734394
申请日：2008-09-01
申请人： Shuji Nishi , Sachio Tsujino , Yuhichiroh Murakami , Yasushi Sasaki , Seijirou Gyouten
发明人： Shuji Nishi , Sachio Tsujino , Yuhichiroh Murakami , Yasushi Sasaki , Seijirou Gyouten
IPC分类号： G09G5/00 , G05F3/24
CPC分类号： H02M3/073 , H02M2003/077
摘要： An embodiment of the present invention provides a power supply circuit including a charge-pumping booster section which uses switching elements provided only by N-channel transistors yet does not have a problem of voltage drop by threshold value. When a boosted voltage is obtained at a first terminal of a first capacitor in a booster section, a booster control section supplies this boosted voltage to a third capacitor, to boost the voltage further thereby turning ON a first transistor. When a boosted voltage is obtained at a first terminal of a second capacitor in the booster section, the booster control section supplies this boosted voltage to a fourth capacitor, to boost the voltage further thereby turning ON a second transistor. This arrangement eliminates a problem of voltage drop by threshold value in the first and the second transistors which serve as output-side switching elements.
摘要翻译：本发明的一个实施例提供一种电源电路，其包括使用仅由N沟道晶体管提供的开关元件的电荷泵浦升压器部分，但不具有通过阈值的电压降的问题。当在升压部中的第一电容器的第一端获得升压电压时，升压控制部将该升压电压提供给第三电容器，进一步升高电压，从而导通第一晶体管。当在升压部中的第二电容器的第一端获得升压电压时，升压控制部将该升压电压提供给第四电容器，进一步升压电压，从而导通第二晶体管。这种布置消除了用作输出侧开关元件的第一和第二晶体管中的阈值电压下降的问题。

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