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51. 发明申请

US20120254846A1 System and Method for Optimizing a Code Section by Forcing a Code Section to be Executed Atomically 有权
标题翻译：通过强制代码部分原子执行来优化代码段的系统和方法
公开(公告)号：US20120254846A1
公开(公告)日：2012-10-04
申请号：US13077793
申请日：2011-03-31
申请人： Mark S. Moir , David Dice , Srikanta N. Tirthapura
发明人： Mark S. Moir , David Dice , Srikanta N. Tirthapura
IPC分类号： G06F9/45 , G06F9/46
CPC分类号： G06F9/467 , G06F8/443 , G06F9/30087 , G06F12/0261
摘要： Systems and methods for optimizing code may use transactional memory to optimize one code section by forcing another code section to execute atomically. Application source code may be analyzed to identify instructions in one code section that only need to be executed if there exists the possibility that another code section (e.g., a critical section) could be partially executed or that its results could be affected by interference. In response to identifying such instructions, alternate code may be generated that forces the critical section to be executed as an atomic transaction, e.g., using best-effort hardware transactional memory. This alternate code may replace the original code or may be included in an alternate execution path that can be conditionally selected for execution at runtime. The alternate code may elide the identified instructions (which are rendered unnecessary by the transaction) by removing them, or by including them in the alternate execution path.
摘要翻译：用于优化代码的系统和方法可以使用事务存储器来通过强制另一个代码部分以原子方式执行来优化一个代码段。可以分析应用源代码以识别一个代码部分中的指令，其仅在存在可以部分地执行另一代码部分（例如，关键部分）或其结果可能受到干扰的影响的情况下才需要执行。响应于识别这样的指令，可以生成迫使关键部分作为原子事务执行的替代代码，例如使用尽力而为的硬件事务存储器。该替代代码可以替换原始代码，或者可以被包括在可以有选择地在运行时执行的备用执行路径中。替代代码可以通过删除它们或者将它们包括在备用执行路径中来去除所识别的指令（由事务变得不必要）。

52. 发明授权

US08140497B2 System and method for implementing nonblocking zero-indirection transactional memory 有权
标题翻译：用于实现非阻塞零间接事务内存的系统和方法
公开(公告)号：US08140497B2
公开(公告)日：2012-03-20
申请号：US11967381
申请日：2007-12-31
申请人： James R. Goodman , Mark S. Moir , Fu'ad W. F. Al Tabba′ , Cong Wang
发明人： James R. Goodman , Mark S. Moir , Fu'ad W. F. Al Tabba′ , Cong Wang
IPC分类号： G06F17/00
CPC分类号： G06F9/467
摘要： Systems and methods for implementing and using nonblocking zero-indirection software transactional memory (NZSTM) are disclosed. NZSTM systems implement object-based software transactional memory that eliminates all levels of indirection except in the uncommon case of a conflict with an unresponsive thread. Shared data is co-located with a header in an NZObject, and is addressable at a fixed offset from the header. Conflicting transactions are requested to abort themselves without being forced to abort. NZObjects are modified in place when there are no conflicts, and when a conflicting transaction acknowledges the abort request. In the uncommon case, NZObjects are inflated to introduce a locator and some levels of indirection, and are restored to their un-inflated form following resolution of the conflict. In some embodiments, transactions are executed using best effort hardware transactional memory if it is available and effective, and software transactional memory if not, yielding a hybrid transactional memory system, NZTM.
摘要翻译：公开了用于实现和使用非阻塞零间接软件事务存储器（NZSTM）的系统和方法。 NZSTM系统实现了基于对象的软件事务内存，消除了所有级别的间接，除非是与无响应线程冲突的罕见情况。共享数据与NZObject中的头部位于一起，并且可以与头部固定的偏移量进行寻址。要求冲突交易中止自己而不被迫中止。当没有冲突时，NZObjects被修改就位，当冲突的事务确认中止请求时。在不常见的情况下，NZObjects被膨胀以引入定位器和一定程度的间接性，并且在解决冲突之后恢复到它们没有膨胀的形式。在一些实施例中，如果可用且有效，则使用尽力而为的硬件事务存储器来执行事务，如果不是，则使用软件事务存储器，产生混合事务存储器系统NZTM。

53. 发明授权

US08117605B2 Method and apparatus for improving transactional memory interactions by tracking object visibility 有权
标题翻译：通过跟踪对象可视性来改善事务记忆交互的方法和装置
公开(公告)号：US08117605B2
公开(公告)日：2012-02-14
申请号：US11311506
申请日：2005-12-19
申请人： Yosef Lev , Jan-Willem Maessen , Mark S. Moir
发明人： Yosef Lev , Jan-Willem Maessen , Mark S. Moir
IPC分类号： G06F9/45
CPC分类号： G06F9/466
摘要： In a multi-threaded computer system that uses transactional memory, object fields accessed by only one thread are accessed by regular non-transactional read and write operations. When an object may be visible to more than one thread, access by non-transactional code is prevented and all accesses to the fields of that object are performed using transactional code. In one embodiment, the current visibility of an object is stored in the object itself. This stored visibility can be checked at runtime by code that accesses the object fields or code can be generated to check the visibility prior to access during compilation.
摘要翻译：在使用事务内存的多线程计算机系统中，只有一个线程访问的对象字段通过常规的非事务性读写操作进行访问。当一个对象可能对多个线程可见时，将阻止非事务代码的访问，并使用事务代码执行对该对象的字段的所有访问。在一个实施例中，对象的当前可视性被存储在对象本身中。可以在运行时通过访问对象字段的代码检查存储的可见性，或者可以生成代码以在编译期间访问之前检查可见性。

54. 发明申请

US20120005461A1 System and Method for Performing Incremental Register Checkpointing in Transactional Memory 有权
标题翻译：在事务性存储器中执行增量寄存器检查点的系统和方法
公开(公告)号：US20120005461A1
公开(公告)日：2012-01-05
申请号：US12827842
申请日：2010-06-30
申请人： Mark S. Moir , David Dice , Daniel S. Nussbaum , James R. Goodman
发明人： Mark S. Moir , David Dice , Daniel S. Nussbaum , James R. Goodman
IPC分类号： G06F9/312
CPC分类号： G06F9/3863 , G06F9/3834 , G06F9/3859
摘要： Systems and methods described herein for performing incremental register checkpointing may employ a special register to indicate which registers have already been checkpointed. This register may include one bit per register. These systems may also include a special pointer register whose value identifies a location in user memory or in dedicated on-chip storage at which a copy of a register's value should be saved by a checkpointing operation. Only registers modified during speculative execution or execution of a transaction may be checkpointed (e.g., when register modifying instructions are encountered) and subsequently restored (e.g., due to misspeculation or transaction abort), rather than all of the registers of the processor. Each register may be checkpointed at most once for a given speculative episode or atomic transaction. Setting a bit in the special register may prevent checkpointing of the corresponding register. Setting all of the bits in the special register may disable checkpointing.
摘要翻译：本文描述的用于执行增量寄存器检查点的系统和方法可以使用特殊寄存器来指示哪些寄存器已经被检查点。该寄存器可以包括每个寄存器一位。这些系统还可以包括特殊的指针寄存器，其特征指针寄存器的值标识用户存储器中的位置或专用片上存储器，通过检查点操作应该保存寄存器值的副本。只有在推测性执行或执行交易期间修改的寄存器可以是检查点（例如，当遇到寄存器修改指令时）并且随后恢复（例如，由于错误设置或事务中止）而不是处理器的所有寄存器。对于给定的投机事件或原子事务，每个寄存器最多可以被检查点一次。在特殊寄存器中设置一位可能会阻止相应寄存器的检查点。设置特殊寄存器中的所有位可能会禁用检查点。

55. 发明授权

US07849446B2 Replay debugging 有权
标题翻译：重播调试
公开(公告)号：US07849446B2
公开(公告)日：2010-12-07
申请号：US11608830
申请日：2006-12-10
申请人： Yosef Lev , Mark S. Moir
发明人： Yosef Lev , Mark S. Moir
IPC分类号： G06F9/44
CPC分类号： G06F11/3632
摘要： Transactional programming promises to substantially simplify the development and maintenance of correct, scalable, and efficient concurrent programs. Designs for supporting transactional programming using transactional memory implemented in hardware, software, and a mixture of the two have emerged recently. Unfortunately, conventional debugging programs are often inadequate when employed in relation to code that employs transactional memory and new or modified techniques are needed. We describe techniques whereby certain facilities of a transactional memory implementation can be leveraged to provide replay debugging. With replay debugging, the user can examine a partial or complete execution of an atomic block after it has happened—for example, right before the execution commits. Moreover, in some cases the user can modify the replayed execution, and decide to commit the new modified execution instead of the original replayed one.
摘要翻译：事务性规划将大大简化正确，可扩展和高效并发程序的开发和维护。最近出现了使用在硬件，软件和两者的混合中实现的事务性存储来支持事务性编程的设计。不幸的是，传统的调试程序在采用事务性存储器的代码方面经常是不足够的，需要新的或修改的技术。我们描述了可以利用事务性存储器实现的某些设施来提供重播调试的技术。通过重播调试，用户可以在发生原子块之后检查原子块的部分或完全执行，例如在执行提交之前。此外，在某些情况下，用户可以修改重播的执行，并决定提交新的修改的执行，而不是原始的被重播的执行。

56. 发明授权

US07793052B2 System and method for implementing hybrid single-compare-single-store operations 有权
标题翻译：实现混合单比较单店操作的系统和方法
公开(公告)号：US07793052B2
公开(公告)日：2010-09-07
申请号：US11967358
申请日：2007-12-31
申请人： James R. Goodman , Mark S. Moir , Fu'ad W. F. Al Tabba′ , Cong Wang
发明人： James R. Goodman , Mark S. Moir , Fu'ad W. F. Al Tabba′ , Cong Wang
IPC分类号： G06F12/00
CPC分类号： G06F9/526 , G06F9/466 , G06F11/141 , G06F11/1479 , G06F2209/521
摘要： A hybrid Single-Compare-Single-Store (SCSS) operation may exploit best-effort hardware transactional memory (HTM) for good performance in the case that it succeeds, and may transparently resort to software-mediated transactions if the hardware transactional mechanisms fail. The SCSS operation may compare a value in a control location to a specified expected value, and if they match, may store a new value in a separate data location. The control value may include a global lock, a transaction status indicator, and/or a portion of an ownership record, in different embodiments. If another transaction in progress owns the data location, the SCSS operation may abort the other transaction or may help it complete by copying the other transactions' write set into its own right set before acquiring ownership. A hybrid SCSS operation, which is usually nonblocking, may be applied to building software transactional memories (STMs) and/or hybrid transactional memories (HyTMs), in some embodiments.
摘要翻译：混合单一比较单存储（SCSS）操作可以在成功的情况下利用尽力而为的硬件事务存储器（HTM）以获得良好的性能，并且如果硬件事务机制失败，则可以透明地诉诸软件介入的事务。 SCSS操作可以将控制位置中的值与指定的预期值进行比较，如果匹配，则可将新值存储在单独的数据位置。在不同的实施例中，控制值可以包括全局锁定，事务状态指示符和/或所有权记录的一部分。如果正在进行的另一个交易拥有数据位置，SCSS操作可能会中止其他交易，或者可以在获得所有权之前将其他交易的写入集合复制到自己的权利集中来帮助完成该交易。在一些实施例中，通常不阻塞的混合SCSS操作可以应用于构建软件事务存储器（STM）和/或混合事务存储器（HyTM）。

57. 发明申请

US20100169895A1 Method and System for Inter-Thread Communication Using Processor Messaging 有权
标题翻译：使用处理器消息传递进行线程间通信的方法和系统
公开(公告)号：US20100169895A1
公开(公告)日：2010-07-01
申请号：US12345179
申请日：2008-12-29
申请人： David Dice , Mark S. Moir
发明人： David Dice , Mark S. Moir
IPC分类号： G06F9/54
CPC分类号： G06F9/466 , G06F9/3009 , G06F9/544
摘要： In shared-memory computer systems, threads may communicate with one another using shared memory. A receiving thread may poll a message target location repeatedly to detect the delivery of a message. Such polling may cause excessive cache coherency traffic and/or congestion on various system buses and/or other interconnects. A method for inter-processor communication may reduce such bus traffic by reducing the number of reads performed and/or the number of cache coherency messages necessary to pass messages. The method may include a thread reading the value of a message target location once, and determining that this value has been modified by detecting inter-processor messages, such as cache coherence messages, indicative of such modification. In systems that support transactional memory, a thread may use transactional memory primitives to detect the cache coherence messages. This may be done by starting a transaction, reading the target memory location, and spinning until the transaction is aborted.
摘要翻译：在共享内存计算机系统中，线程可以使用共享内存彼此进行通信。接收线程可以重复轮询消息目标位置以检测消息的传递。这种轮询可能导致各种系统总线和/或其他互连上的高速缓存一致性业务和/或拥塞。用于处理器间通信的方法可以通过减少执行的读取的数量和/或传递消息所需的高速缓存一致性消息的数量来减少这种总线流量。该方法可以包括读取消息目标位置的值一次的线程，并且通过检测指示这种修改的处理器间消息（例如高速缓存一致性消息）来确定该值已被修改。在支持事务内存的系统中，线程可以使用事务存储器原语来检测高速缓存一致性消息。这可以通过启动事务，读取目标内存位置和旋转直到事务中止来完成。

58. 发明申请

US20100153662A1 FACILITATING GATED STORES WITHOUT DATA BYPASS 有权
标题翻译：在没有数据旁路的情况下建立门控存储
公开(公告)号：US20100153662A1
公开(公告)日：2010-06-17
申请号：US12334316
申请日：2008-12-12
申请人： Christopher A. Vick , Gregory M. Wright , Mark S. Moir
发明人： Christopher A. Vick , Gregory M. Wright , Mark S. Moir
IPC分类号： G06F12/00
CPC分类号： G06F8/52 , G06F9/3004 , G06F9/30087 , G06F9/3834 , G06F9/384 , G06F9/3857 , G06F9/3863
摘要： One embodiment of the present invention provides a system that facilitates precise exception semantics for a virtual machine. During operation, the system executes a program in the virtual machine using a processor that includes a gated store buffer that stores values to be written to a memory. This gated store buffer is configured to delay a store to the memory until after a speculatively-optimized region of the program commits. The processor signals an exception when it detects that a load following the store is attempting to access the same memory region being written by the store prior to the commitment of the speculatively-optimized region.
摘要翻译：本发明的一个实施例提供一种促进虚拟机的精确异常语义的系统。在操作期间，系统使用包括存储要写入存储器的值的门控存储缓冲器的处理器在虚拟机中执行程序。该门控存储缓冲器配置为将存储器延迟到存储器，直到程序的推测优化区域提交。处理器在检测到存储器之后的负载尝试访问由推测优化区域承诺之前由存储器写入的相同存储区域时，发出异常。

59. 发明授权

US07711909B1 Read sharing using global conflict indication and semi-transparent reading in a transactional memory space 有权
标题翻译：在事务性存储空间中使用全局冲突指示和半透明读取读取共享
公开(公告)号：US07711909B1
公开(公告)日：2010-05-04
申请号：US11008692
申请日：2004-12-09
申请人： Yosef Lev , Mark S. Moir
发明人： Yosef Lev , Mark S. Moir
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F9/52
摘要： It has been discovered that globally indicating read-write conflicts and semi-transparent read sharing in a transactional memory space allows for a more expedient validation. Without being aware of particular transactions, a writing transaction can determine that a read-write conflict will occur with some transaction that has read one or more memory locations to be modified by the writing transaction. With semi-transparent reading, reading transactions can validate quickly. If a read-write conflict has not occurred since a reading transaction began (or since the last validation), then the previous reads are valid. Otherwise, the reading transaction investigates each memory location or ownership record to determine if a read-write conflict affected the investigating transaction.
摘要翻译：已经发现，在事务存储器空间中全局地指示读写冲突和半透明读共享允许更方便的验证。在不知道特定事务的情况下，写入事务可以确定读写冲突将发生，其中一些事务已读取要由写入事务修改的一个或多个存储器位置。通过半透明阅读，阅读交易可以快速验证。如果读取事务开始（或自上次验证）以来没有发生读写冲突，则之前的读取是有效的。否则，阅读交易会调查每个内存位置或所有权记录，以确定读写冲突是否影响了调查交易。

60. 发明授权

US07689788B2 System and method for executing transactions 有权
标题翻译：用于执行事务的系统和方法
公开(公告)号：US07689788B2
公开(公告)日：2010-03-30
申请号：US11656843
申请日：2007-01-23
申请人： Mark S. Moir , Virendra J. Marathe
发明人： Mark S. Moir , Virendra J. Marathe
IPC分类号： G06F12/00
CPC分类号： G06F9/466
摘要： A method for executing transactions including obtaining a memory location required by a first transaction, where the first transaction is identified using a first transaction identification and a first transaction version; determining a second transaction with ownership of a memory group including the memory location, where the second transaction is identified using a second transaction identification and a second transaction version; copying an intermediate value associated with the memory group from the second transaction into transactional metadata associated with the first transaction; changing ownership of the memory group to the first transaction; and committing the first transaction.
摘要翻译：一种用于执行交易的方法，包括获得第一交易所需的存储位置，其中使用第一交易标识和第一交易版本识别所述第一交易; 确定包括所述存储器位置的存储器组的所有权的第二事务，其中使用第二事务标识和第二事务版本识别所述第二事务; 将与所述存储器组相关联的中间值从所述第二事务复制到与所述第一事务相关联的事务元数据; 将内存组的所有权更改为第一笔交易; 并提交第一笔交易。

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