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51. 发明申请

US20080259479A1 System and Methods for Copying Digital Information from a Digital Media 审中-公开
标题翻译：从数字媒体复制数字信息的系统和方法
公开(公告)号：US20080259479A1
公开(公告)日：2008-10-23
申请号：US11738633
申请日：2007-04-23
申请人： Nils Graef
发明人： Nils Graef
IPC分类号： G11B5/86
CPC分类号： G11B5/86 , G11B27/034 , G11B27/11 , G11B27/3027 , G11B2220/2541
摘要： System and Methods for Copying Digital Information from a Digital Media Various embodiments of the present invention provide systems and methods for copying or ripping digital information contained on one media to another media. In particular, some embodiments of the present invention provide methods and systems for copying digital information contained in a first fixed media onto another media by using digital information content corresponding to that maintained on the first fixed media, but obtained from a database.
摘要翻译：用于从数字媒体复制数字信息的系统和方法本发明的各种实施例提供了将包含在一个媒体上的数字信息复制或翻录到另一媒体的系统和方法。特别地，本发明的一些实施例提供了使用包含在第一固定介质中的数字信息通过使用对应于在第一固定介质上保持的数字信息内容但从数据库获取的数字信息内容来复制到另一介质上的方法和系统。

52. 发明申请

US20060104390A1 Reduced-complexity multiple-input, multiple-output detection 失效
公开(公告)号：US20060104390A1
公开(公告)日：2006-05-18
申请号：US10990910
申请日：2004-11-17
申请人： Nils Graef , Joachim Hammerschmidt
发明人： Nils Graef , Joachim Hammerschmidt
IPC分类号： H03D1/00
CPC分类号： H04L25/03191 , H04B7/0413 , H04L5/0023 , H04L25/0204 , H04L25/0224 , H04L25/0321 , H04L25/03318 , H04L27/2647 , H04L2025/03414 , H04L2025/03426 , H04L2025/03643
摘要： A wireless receiver detects signals generated with a multiple-input, multiple-output (MIMO) transmitter. The receiver applies maximum-likelihood detection (MLD) for soft-output signal detection, where an MLD exhaustive search across all candidate vectors is performed recursively by computing and accumulating the differences between, for example, the Euclidean metrics of consecutive candidate tests. Difference terms used for the accumulation are also calculated recursively. An ordering of candidates, such as by a triangular-waveform shaped ordering, is employed such that only one candidate variable is changed between any two consecutive candidate evaluations, leading to a reduced set of computations.

53. 发明授权

US09753877B2 Memory read-channel with signal processing on general purpose processor 有权
公开(公告)号：US09753877B2
公开(公告)日：2017-09-05
申请号：US13510980
申请日：2009-11-30
申请人： Nils Graef , Erich F. Haratsch
发明人： Nils Graef , Erich F. Haratsch
IPC分类号： G06F3/00 , G06F13/38 , G06F11/10 , G06F3/06 , G06F5/10
CPC分类号： G06F13/385 , G06F3/0619 , G06F3/0656 , G06F5/10 , G06F11/1068
摘要： Methods and apparatus are provided for processing a data value in a read channel of a memory device. The data value provided to a general purpose processor for processing. The data value is not decoded data and may comprise one or more of a raw data value and an intermediate data value. The data value can be provided to the general purpose processor, for example, upon a detection of one or more predefined trigger conditions. A data value can be obtained from a memory device and then be redirected to a general purpose processor. The data value is not decoded data. The redirection can be conditionally performed if one or more predefined bypass conditions exist. The general purpose processor is optionally time-shared with one or more additional applications.

54. 发明授权

US09356623B2 LDPC decoder variable node units having fewer adder stages 有权
标题翻译：具有较少加法器级的LDPC解码器可变节点单元
公开(公告)号：US09356623B2
公开(公告)日：2016-05-31
申请号：US12323626
申请日：2008-11-26
申请人： Nils Graef
发明人： Nils Graef
IPC分类号： G06F11/00 , H03M13/00 , H03M13/11 , G06F11/10
CPC分类号： H03M13/116 , G06F11/1004 , H03M13/1117 , H03M13/1137 , H03M13/658 , H03M13/6591
摘要： In one embodiment, the present invention is a variable node unit (VNU) of a low-density parity-check (LDPC) decoder. The VNU receives a soft-input value and wc check node messages, where wc is the column hamming weight of the LDPC code. The VNU generates (i) an extrinsic log-likelihood ratio (LLR) by adding all wc check node messages together; (ii) a hard-decision output by adding the extrinsic LLR to the soft-input value and selecting the sign bit of the resulting sum; and (iii) wc variable node messages. Each variable node message is generated by adding a different set of (wc−1) check node messages to the soft-input value where each set excludes a different check node message. In so doing, VNUs of the present invention may generate variable node messages using fewer adder stages compared to prior-art VNUs such that throughput may be increased over that of prior-art VNUs.
摘要翻译：在一个实施例中，本发明是低密度奇偶校验（LDPC）解码器的可变节点单元（VNU）。 VNU接收软输入值并检查节点消息，其中wc是LDPC码的列汉明权重。 VNU通过将所有wc校验节点消息加在一起而产生（i）外在对数似然比（LLR）; （ii）通过将外部LLR加到软输入值并选择所得和的符号位的硬判决输出; 和（iii）wc变量节点消息。通过将不同的一组（wc-1）校验节点消息添加到软输入值来生成每个变量节点消息，其中每个集合排除不同的校验节点消息。这样做，与现有技术的VNU相比，本发明的VNU可以使用较少的加法器级产生可变节点消息，使得吞吐量可以比现有技术的VNU的吞吐量增加。

55. 发明授权

US08484535B2 Error-floor mitigation of codes using write verification 有权
标题翻译：使用写入验证的错误代码减少代码
公开(公告)号：US08484535B2
公开(公告)日：2013-07-09
申请号：US12994288
申请日：2009-04-21
申请人： Nils Graef , Kiran Gunnam
发明人： Nils Graef , Kiran Gunnam
IPC分类号： G11C29/00
CPC分类号： H03M13/1102 , G06F11/1012 , G11B20/1833 , G11B2020/1823 , G11B2020/185 , G11B2220/2516 , G11B2220/61 , H03M13/1108 , H03M13/1142 , H03M13/455
摘要： Executed when a channel input (e.g., LDPC) codeword is written to a storage medium, a write-verification method (i) compares the channel input codeword to the written codeword, (ii) identifies any erroneous bits, and (iii) stores the erroneous-bit indices to a record in a table. At some later time, the written codeword is read and sent to a decoder. If the decoder fails with a near codeword, a write-error recovery process searches the table and retrieves the erroneous-bit information. The codeword bits at those indices are adjusted, and the modified codeword is submitted to further processing.
摘要翻译：当通道输入（例如，LDPC）码字被写入存储介质时执行，写入验证方法（i）将信道输入码字与写入的码字进行比较，（ii）识别任何错误比特，以及（iii）表中记录的错误位索引。在稍后的时间，写入的码字被读取并发送到解码器。如果解码器出现接近码字失败，则写入错误恢复过程将搜索表并检索错误位信息。调整这些索引处的码字比特，并且修改的码字被提交进一步处理。

56. 发明授权

US08245098B2 Selectively strengthening and weakening check-node messages in error-correction decoders 有权
标题翻译：在纠错解码器中选择性地加强和削弱校验节点消息
公开(公告)号：US08245098B2
公开(公告)日：2012-08-14
申请号：US12538915
申请日：2009-08-11
申请人： Yang Han , Kiran Gunnam , Shaohua Yang , Hao Zhong , Nils Graef , Yuan Xing Lee
发明人： Yang Han , Kiran Gunnam , Shaohua Yang , Hao Zhong , Nils Graef , Yuan Xing Lee
IPC分类号： H03M13/00 , G06F11/10
CPC分类号： H03M13/1111 , H03M13/09 , H03M13/1142 , H03M13/3707 , H03M13/3738 , H03M13/3753 , H03M13/451
摘要： In one embodiment, an LDPC decoder has a plurality of check-node units (CNUs) and a controller. Initially, the CNUs generate check-node messages based on an initial offset value selected by the controller. If the decoder converges on a trapping set, then the controller selects new offset values for missatisfied check nodes (MSCs), the locations of which are approximated, and/or unsatisfied check nodes (USCs). In particular, offset values are selected such that (i) the messages corresponding to the MSCs are decreased relative to the messages that would be generated using the initial offset value and/or (ii) the messages corresponding to the USCs are increased relative to the messages that would be generated using the initial offset value. Decoding is then continued for a specified number of iterations to break the trapping set. In other embodiments, the controller selects scaling factors rather than, or in addition to, offset values.
摘要翻译：在一个实施例中，LDPC解码器具有多个校验节点单元（CNU）和控制器。最初，CNU基于由控制器选择的初始偏移值生成校验节点消息。如果解码器收敛于陷阱集合，则控制器为不满意的校验节点（MSC）（其位置近似）和/或不满足的校验节点（USC）选择新的偏移值。特别地，选择偏移值，使得（i）相对于MSC的消息相对于将使用初始偏移值生成的消息减少和/或（ii）相对于USC的消息相对于将使用初始偏移值生成的消息。然后继续解码指定数量的迭代以打破陷阱集。在其他实施例中，控制器选择缩放因子，而不是或附加于偏移值。

57. 发明授权

US08161348B2 Systems and methods for low cost LDPC decoding 有权
标题翻译：低成本LDPC解码的系统和方法
公开(公告)号：US08161348B2
公开(公告)日：2012-04-17
申请号：US12025924
申请日：2008-02-05
申请人： Nils Graef
发明人： Nils Graef
IPC分类号： H03M13/00
CPC分类号： H03M13/1137 , H03M13/1111 , H03M13/6325
摘要： Various embodiments of the present invention provide systems and circuits that provide for LDPC decoding and/or error correcting. For example, various embodiments of the present invention provide LDPC decoder circuits that include a soft-input memory, a memory unit, and an arithmetic unit. The arithmetic unit includes a hardware circuit that is selectably operable to perform a row update and a column update. In such cases, a substantial portion of the circuitry of the hardware circuit used to perform the row update is re-used to perform the column update.
摘要翻译：本发明的各种实施例提供了提供LDPC解码和/或纠错的系统和电路。例如，本发明的各种实施例提供了包括软输入存储器，存储器单元和运算单元的LDPC解码器电路。算术单元包括可选择地可操作地执行行更新和列更新的硬件电路。在这种情况下，用于执行行更新的硬件电路的大部分电路被重新用于执行列更新。

58. 发明授权

US08161345B2 LDPC decoders using fixed and adjustable permutators 有权
标题翻译： LDPC解码器使用固定和可调排列
公开(公告)号：US08161345B2
公开(公告)日：2012-04-17
申请号：US12260608
申请日：2008-10-29
申请人： Nils Graef
发明人： Nils Graef
IPC分类号： G06F11/00
CPC分类号： H03M13/116 , H03M13/1111 , H03M13/1137
摘要： In one embodiment, the present invention is a low-density parity-check (LDPC) decoder that has a plurality of variable node units (VNUs) that generate variable node messages and a plurality of check node units (CNUs) that generate check node messages. The variable node messages and check node messages are distributed between the VNUs and CNUs using a number r of combinations of permutators, wherein each permutator combination includes (i) a cyclic shifter and (ii) a fixed, non-cyclic permutator. The cyclic shifters are capable of supporting a number p of different cyclic LDPC sub-matrices; however, when combined with different fixed permutators, the permutator combinations are capable of supporting up to r×p different LDPC sub-matrices. In other embodiments, the LDPC decoder may have fewer than r fixed permutators such that the LDPC decoder is capable of supporting between p and r×p different LDPC sub-matrices.
摘要翻译：在一个实施例中，本发明是一种低密度奇偶校验（LDPC）解码器，其具有生成可变节点消息的多个可变节点单元（VNU）和产生校验节点消息的多个校验节点单元（CNU）。可变节点消息和校验节点消息使用排列的组合数r分配在VNU和CNU之间，其中每个置换器组合包括（i）循环移位器和（ii）固定的非循环置换器。循环移位器能够支持多个不同的循环LDPC子矩阵; 然而，当与不同的固定置换器组合时，置换器组合能够支持高达r×p个不同的LDPC子矩阵。在其他实施例中，LDPC解码器可以具有少于r个固定置换器，使得LDPC解码器能够在p和r×p个不同的LDPC子矩阵之间进行支持。

59. 发明申请

US20120087035A1 Systems and Methods for Variable Compensated Fly Height Measurement 有权
标题翻译：可变补偿飞行高度测量的系统和方法
公开(公告)号：US20120087035A1
公开(公告)日：2012-04-12
申请号：US13326493
申请日：2011-12-15
申请人： Nils Graef
发明人： Nils Graef
IPC分类号： G11B21/02
CPC分类号： G11B5/6029 , G11B5/6064
摘要： Various embodiments of the present invention provide systems and methods for determining fly height.
摘要翻译：本发明的各种实施例提供了用于确定飞行高度的系统和方法。

60. 发明授权

US08140947B2 Method and apparatus for storing survivor paths in a Viterbi detector using systematic pointer exchange 有权
标题翻译：使用系统指针交换在维特比检测器中存储幸存路径的方法和装置
公开(公告)号：US08140947B2
公开(公告)日：2012-03-20
申请号：US11241759
申请日：2005-09-30
申请人： Nils Graef
发明人： Nils Graef
IPC分类号： H03M13/00
CPC分类号： H03M13/4184 , H03M13/395 , H03M13/6331
摘要： Methods and apparatus are provided for storing survivor paths in a Viterbi detector. The invention maintains at least one register and at least one pointer for each state. Each register stores a bit sequence associated with a Viterbi state and each pointer points to one of the registers. One or more predefined rules based on a trellis structure are employed to exchange one or more of the pointers. A survivor path memory is also disclosed for a Viterbi detector. The survivor path memory comprises a plurality of columns, each associated with a different time step, and an input processor. Each column comprises a flip flop for storing one bit or portion of a bit sequence associated with a Viterbi state; and a multiplexer for each state controlled by a case signal indicating a time step, the multiplexer selecting a state from a previous time step, wherein an output of the multiplexer of a given state is connected to at least one data input of a flip flop of the given state. The input processor generates a control signal that exchanges one or more pointers based on a trellis structure, wherein each of the pointers points to one of the flip flops.
摘要翻译：提供了用于在维特比检测器中存储幸存路径的方法和装置。本发明为每个状态保持至少一个寄存器和至少一个指针。每个寄存器存储与维特比状态相关联的位序列，并且每个指针指向其中一个寄存器。采用基于网格结构的一个或多个预定义规则来交换一个或多个指针。还针对维特比检测器公开了幸存路径存储器。幸存者路径存储器包括多个列，每个列与不同的时间步长相关联，以及输入处理器。每列包括用于存储与维特比状态相关联的位序列的一个位或部分的触发器; 以及多路复用器，用于由指示时间步长的情况信号控制的每个状态，所述多路复用器从先前的时间步长选择状态，其中给定状态的多路复用器的输出连接到触发器的至少一个数据输入给定的状态。输入处理器生成基于网格结构交换一个或多个指针的控制信号，其中每个指针指向其中一个触发器。

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