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51. 发明授权

US07317241B2 Semiconductor apparatus having a large-size bus connection 有权
公开(公告)号：US07317241B2
公开(公告)日：2008-01-08
申请号：US11143649
申请日：2005-06-03
申请人： Yasurou Matsuzaki , Yasuharu Sato , Tadao Aikawa , Masafumi Yamazaki , Takaaki Suzuki
发明人： Yasurou Matsuzaki , Yasuharu Sato , Tadao Aikawa , Masafumi Yamazaki , Takaaki Suzuki
IPC分类号： H01L23/58
CPC分类号： G11C5/06 , G11C5/00 , G11C5/04 , G11C5/063 , H01L25/0652 , H01L25/0657 , H01L27/105 , H01L2224/48091 , H01L2225/0651 , H01L2225/06513 , H01L2225/06562 , H01L2924/13091 , H04L12/40 , H04L12/4625 , H01L2924/00014 , H01L2924/00
摘要： In a semiconductor apparatus of the present invention, a plurality of circuit components are provided. A first bus interconnects the circuit components. A second bus interconnects the circuit components. A switching unit outputs a select signal that causes each circuit component to select one of the first bus and the second bus when transmitting a signal from one of the circuit components to another. The second bus has a size larger than a size of the first bus.

52. 发明授权

US07304907B2 Memory circuit with automatic precharge function, and integrated circuit device with automatic internal command function 有权
标题翻译：具有自动预充功能的记忆电路，具有自动内部指令功能的集成电路器件
公开(公告)号：US07304907B2
公开(公告)日：2007-12-04
申请号：US11790832
申请日：2007-04-27
申请人： Yasurou Matsuzaki
发明人： Yasurou Matsuzaki
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C11/40603 , G11C11/40615 , G11C11/40618 , G11C11/4072 , G11C11/4094 , G11C2211/4061 , G11C2211/4065
摘要： According to the present invention, a memory circuit requiring refresh operations a first circuit which receives a command in synchronization with a clock signal, and which generates a first internal command internally and a second circuit which generates a second internal command, e.g., a refresh command, internally in a prescribed refresh cycle. And an internal circuit, according to said first internal command, executes corresponding control through clock-synchronous operations, and when said refresh command is issued, sequentially executes control corresponding to the refresh command and control corresponding to said first internal command through clock-asynchronous operations. According to the present invention, when a refresh timing signal is generated, the refresh operation can be intrupted among the external command operations.
摘要翻译：根据本发明，一种需要刷新操作的存储电路，第一电路接收与时钟信号同步的命令，并且内部产生第一内部命令，第二电路产生第二内部命令，例如刷新命令在规定的刷新周期内部。并且根据所述第一内部命令，内部电路通过时钟同步操作执行相应的控制，并且当发出所述刷新命令时，通过时钟异步操作顺序执行对应于刷新命令的控制和对应于所述第一内部命令的控制。根据本发明，当产生刷新定时信号时，可以在外部命令操作中中断刷新操作。

53. 发明授权

US07295483B2 Semiconductor memory 有权
公开(公告)号：US07295483B2
公开(公告)日：2007-11-13
申请号：US11513394
申请日：2006-08-31
申请人： Naoharu Shinozaki , Yasurou Matsuzaki
发明人： Naoharu Shinozaki , Yasurou Matsuzaki
IPC分类号： G11C7/00
CPC分类号： G11C11/40607 , G11C7/08 , G11C8/18 , G11C11/406 , G11C11/40615 , G11C11/40622 , G11C11/4074 , G11C11/4085 , G11C11/4091 , G11C2207/2227 , G11C2211/4067 , G11C2211/4068
摘要： A partial area for retaining data during low power consumption mode is composed of a single first memory cell out of a plurality of memory cells connected to a bit line. An operation control circuit operates any of the memory cells selected in accordance with an address signal during normal operation mode for performing a read operation and a write operation. The operation control circuit keeps latching data retained by the first memory cell in the partial area into a sense amplifier during the low power consumption mode. This eliminates the need for a refresh operation for retaining the data in the first memory cell during the low power consumption mode. Since the data can be retained without a refresh operation, it is possible to reduce the power consumption during the low power consumption mode.

54. 发明申请

US20060291297A1 Semiconductor memory 有权
公开(公告)号：US20060291297A1
公开(公告)日：2006-12-28
申请号：US11513394
申请日：2006-08-31
申请人： Naoharu Shinozaki , Yasurou Matsuzaki
发明人： Naoharu Shinozaki , Yasurou Matsuzaki
IPC分类号： G11C7/10
CPC分类号： G11C11/40607 , G11C7/08 , G11C8/18 , G11C11/406 , G11C11/40615 , G11C11/40622 , G11C11/4074 , G11C11/4085 , G11C11/4091 , G11C2207/2227 , G11C2211/4067 , G11C2211/4068
摘要： A partial area for retaining data during low power consumption mode is composed of a single first memory cell out of a plurality of memory cells connected to a bit line. An operation control circuit operates any of the memory cells selected in accordance with an address signal during normal operation mode for performing a read operation and a write operation. The operation control circuit keeps latching data retained by the first memory cell in the partial area into a sense amplifier during the low power consumption mode. This eliminates the need for a refresh operation for retaining the data in the first memory cell during the low power consumption mode. Since the data can be retained without a refresh operation, it is possible to reduce the power consumption during the low power consumption mode.

55. 发明授权

US07107504B2 Test apparatus for semiconductor device 有权
公开(公告)号：US07107504B2
公开(公告)日：2006-09-12
申请号：US10073129
申请日：2002-02-13
申请人： Masahiro Sato , Junji Akaza , Nobumi Kodama , Hirohisa Mizuno , Takashi Imura , Yasurou Matsuzaki
发明人： Masahiro Sato , Junji Akaza , Nobumi Kodama , Hirohisa Mizuno , Takashi Imura , Yasurou Matsuzaki
IPC分类号： G01R31/28 , G11C29/00
CPC分类号： G11C29/50012 , G11C29/006 , G11C29/36 , G11C2029/1206
摘要： A test apparatus for a semiconductor device, which improves the reliability of an operational test on target devices on a wafer using BOST (Built Out Self Test) and BIST (Built In Self Test). The test apparatus includes an external test unit, the BIST circuit formed in the semiconductor device, and BOST device which is coupled between the external test unit and the semiconductor device. Pattern data for a pattern dependency test is stored in the BIST circuit and pattern data for a timing dependency test is stored in the BOST device.

56. 发明申请

US20060007770A1 Semiconductor memory 有权
标题翻译：半导体存储器
公开(公告)号：US20060007770A1
公开(公告)日：2006-01-12
申请号：US10968811
申请日：2004-10-20
申请人： Naoharu Shinozaki , Yasurou Matsuzaki
发明人： Naoharu Shinozaki , Yasurou Matsuzaki
IPC分类号： G11C7/00
CPC分类号： G11C11/40607 , G11C7/08 , G11C8/18 , G11C11/406 , G11C11/40615 , G11C11/40622 , G11C11/4074 , G11C11/4085 , G11C11/4091 , G11C2207/2227 , G11C2211/4067 , G11C2211/4068
摘要： A partial area for retaining data during low power consumption mode is composed of a single first memory cell out of a plurality of memory cells connected to a bit line. An operation control circuit operates any of the memory cells selected in accordance with an address signal during normal operation mode for performing a read operation and a write operation. The operation control circuit keeps latching data retained by the first memory cell in the partial area into a sense amplifier during the low power consumption mode. This eliminates the need for a refresh operation for retaining the data in the first memory cell during the low power consumption mode. Since the data can be retained without a refresh operation, it is possible to reduce the power consumption during the low power consumption mode.
摘要翻译：在低功耗模式期间用于保留数据的部分区域由连接到位线的多个存储单元中的单个第一存储单元组成。操作控制电路在正常操作模式期间操作根据地址信号选择的任何存储单元，以执行读操作和写操作。操作控制电路在低功耗模式期间将由部分区域中的第一存储单元保留的数据保持为读出放大器。这消除了在低功耗模式期间需要用于将数据保持在第一存储单元中的刷新操作。由于可以在不进行刷新操作的情况下保持数据，因此可以在低功耗模式下降低功耗。

57. 发明申请

US20050218432A1 Semiconductor apparatus having a large-size bus connection 有权
公开(公告)号：US20050218432A1
公开(公告)日：2005-10-06
申请号：US11143649
申请日：2005-06-03
申请人： Yasurou Matsuzaki , Yasuharu Sato , Tadao Aikawa , Masafumi Yamazaki , Takaaki Suzuki
发明人： Yasurou Matsuzaki , Yasuharu Sato , Tadao Aikawa , Masafumi Yamazaki , Takaaki Suzuki
IPC分类号： G11C5/00 , G11C5/06 , H01L25/065 , H01L27/105 , H01L29/80 , H01L31/0336 , H01L31/109 , H01L31/112 , H04L12/46
CPC分类号： G11C5/06 , G11C5/00 , G11C5/04 , G11C5/063 , H01L25/0652 , H01L25/0657 , H01L27/105 , H01L2224/48091 , H01L2225/0651 , H01L2225/06513 , H01L2225/06562 , H01L2924/13091 , H04L12/40 , H04L12/4625 , H01L2924/00014 , H01L2924/00
摘要： In a semiconductor apparatus of the present invention, a plurality of circuit components are provided. A first bus interconnects the circuit components. A second bus interconnects the circuit components. A switching unit outputs a select signal that causes each circuit component to select one of the first bus and the second bus when transmitting a signal from one of the circuit components to another. The second bus has a size larger than a size of the first bus.

58. 发明授权

US06936874B2 Semiconductor apparatus having a large-size bus connection 失效
标题翻译：具有大尺寸总线连接的半导体装置
公开(公告)号：US06936874B2
公开(公告)日：2005-08-30
申请号：US10766890
申请日：2004-01-30
申请人： Yasurou Matsuzaki
发明人： Yasurou Matsuzaki
IPC分类号： G11C5/00 , G11C5/06 , H01L25/065 , H01L27/105 , H01L29/80 , H01L31/0336 , H01L31/109 , H01L31/112 , H04L12/46
CPC分类号： G11C5/06 , G11C5/00 , G11C5/04 , G11C5/063 , H01L25/0652 , H01L25/0657 , H01L27/105 , H01L2224/48091 , H01L2225/0651 , H01L2225/06513 , H01L2225/06562 , H01L2924/13091 , H04L12/40 , H04L12/4625 , H01L2924/00014 , H01L2924/00
摘要： In a semiconductor apparatus of the present invention, a plurality of circuit components are provided. A first bus interconnects the circuit components. A second bus interconnects the circuit components. A switching unit outputs a select signal that causes each circuit component to select one of the first bus and the second bus when transmitting a signal from one of the circuit components to another. The second bus has a size larger than a size of the first bus.
摘要翻译：在本发明的半导体装置中，设置有多个电路部件。第一条总线将电路组件互连。第二总线将电路组件互连。当从一个电路部件发送信号到另一个电路部件时，切换单元输出使每个电路部件选择第一总线和第二总线中的一个的选择信号。第二个总线的大小大于第一个总线的大小。

59. 发明授权

US06747906B2 Memory circuit with automatic precharge function, and integrated circuit device with automatic internal command function 有权
标题翻译：具有自动预充功能的记忆电路，具有自动内部指令功能的集成电路器件
公开(公告)号：US06747906B2
公开(公告)日：2004-06-08
申请号：US10438927
申请日：2003-05-16
申请人： Yasurou Matsuzaki
发明人： Yasurou Matsuzaki
IPC分类号： G11C700
CPC分类号： G11C11/406 , G11C11/40603 , G11C11/40615 , G11C11/40618 , G11C11/4072 , G11C11/4094 , G11C2211/4061 , G11C2211/4065
摘要： A memory circuit requiring refresh operations a first circuit which receives a command in synchronization with a clock signal, and which generates a first internal command internally and a second circuit which generates a second internal command, i.g. a refresh command, internally in a prescribed refresh cycle. And an internal circuit, according to said first internal command, executes corresponding control through clock-synchronous operations, and when said refresh command is issued, sequentially executes control corresponding to the refresh command and control corresponding to said first internal command through clock-asynchronous operations. When a refresh timing signal is generated, the refresh operation can be intrupted among the external command operations.
摘要翻译：一种需要刷新操作的存储器电路，第一电路与时钟信号同步地接收命令，并在内部生成第一内部命令，第二电路产生第二内部命令，例如，刷新命令，在规定的刷新周期内部。并且根据所述第一内部命令，内部电路通过时钟同步操作执行相应的控制，并且当发出所述刷新命令时，通过时钟异步操作顺序执行对应于刷新命令的控制和对应于所述第一内部命令的控制。当产生刷新定时信号时，可以在外部命令操作之间中断刷新操作。

60. 发明授权

US06707323B1 Semiconductor device, module having a plurality of semiconductor devices mounted thereon and system having a plurality of modules installed therein 有权
标题翻译：具有安装在其上的多个半导体器件的半导体器件模块和其中安装有多个模块的系统
公开(公告)号：US06707323B1
公开(公告)日：2004-03-16
申请号：US09666333
申请日：2000-09-21
申请人： Yasurou Matsuzaki , Masahiko Saitou
发明人： Yasurou Matsuzaki , Masahiko Saitou
IPC分类号： H03K300
CPC分类号： G11C29/021 , G11C11/401 , G11C29/02 , G11C29/028 , G11C29/12005 , G11C2029/5004 , H03K17/145
摘要： There is provided a semiconductor device having an output circuit for outputting a predetermined signal, and an output-level adjusting circuit for adjusting an output level of the output circuit in response to an adjustment start signal externally supplied and outputting an adjustment end signal upon completion of adjustment. A module in which a plurality of the semiconductor devices above are mounted. The module has an adjustment-start-signal terminal for receiving the adjustment start signal externally supplied and supplying the adjustment start signal to the semiconductor devices, and an adjustment-end-signal terminal for outputting a module adjustment end signal in response to adjustment end signals from the semiconductor devices. A plurality of such modules can be mounted in such a way that the adjustment-end-signal terminal of the (N−1)-th module is connected to the adjustment-start-signal terminal of the N-th module.
摘要翻译：提供了一种具有用于输出预定信号的输出电路的半导体器件，以及一个输出电平调整电路，用于响应外部提供的调整开始信号调整输出电路的输出电平，并在完成时输出调整结束信号调整。其中安装有上述多个半导体器件的模块。模块具有用于接收外部提供的调整开始信号并将调整开始信号提供给半导体器件的调整开始信号端子，以及用于响应于调整结束信号而输出模块调整结束信号的调整结束信号端子从半导体器件。可以以使第（N-1）个模块的调整结束信号端子连接到第N个模块的调整开始信号端子的方式安装多个这样的模块。

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