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51. 发明授权

US4949200A Method and apparatus for encoding and mapping magnetic disk sector addresses 失效
标题翻译：用于编码和映射磁盘扇区地址的方法和装置
公开(公告)号：US4949200A
公开(公告)日：1990-08-14
申请号：US176093
申请日：1988-03-31
申请人： Lih-Jyh Weng
发明人： Lih-Jyh Weng
IPC分类号： G11B20/10 , G11B20/18 , G11B27/30
CPC分类号： G11B20/1833 , G11B27/3027 , G11B2220/2508
摘要： Addresses corresponding to magnetic disk sectors are encoded using an error correction code (ECC), such that addresses which are in a neighborhood, that is, addresses which are mathematically or numerically close, are mapped to addresses which differ in at least D-1 bits where the ECC is a distance D code. An original n-bit sector address is separated into two segments. One segment is a "k"-bit neighborhood address segment containing the k lower order address bits identifying the location of the selected sector within a neighborhood. The second segment is an "n-k" bit higher order address segment identifying the neighborhood containing the selected sector. The k-bit neighborhood address segment is then encoded with an (n,k) distance D linear code to form an n-bit preliminary code word containing n-k redundancy (ECC) bits appended, as the most significant bits, to the k neighborhood address bits. The (n-k)-bit higher order address segment is encoded by representing the segment in Gray code. The (n-k)-bit Gray coded segment is added modulo 2 to the n-k redundancy (ECC) bits of the preliminary code word. The resulting n-bit address code word is recorded on the disk as the sector address. When a particular sector is to be accessed, the address is first encoded in the manner set forth above, and the read/write head is moved to the logical neighborhood containing the sector. The encoded address is then compared to the addresses written in the various sectors in the neighborhood. When a match within (D-2)/2 bits is found, the sector is identified as the correct sector.

52. 发明授权

US4856003A Error correction code encoder 失效
标题翻译：纠错码编码器
公开(公告)号：US4856003A
公开(公告)日：1989-08-08
申请号：US47627
申请日：1987-05-07
申请人： Lih-Jyh Weng
发明人： Lih-Jyh Weng
IPC分类号： G06F11/10 , H03M13/00 , H03M13/15
CPC分类号： H03M13/15
摘要： An encoder encodes a sector of data to produce ECC symbols using a GF(2.sup.10) code by first appending one or more pseudo data bytes to the sector data bytes. The data string of sector data bytes and pseudo data bytes are then encoded to produce a desired number of 10-bit ECC symbols. Two selected bits from each ECC symbol are compared to a known bit pattern. If the selected bits match the pattern, the bits are truncated and the remaining 8-bit symbols are concatenated with the data string to form a codeword. The codeword bytes can later be decoded, and any error correction performed, by appending the bit pattern as necessary. If the selected bits do not match the pattern, the pseudo data bytes are modified such that encoding the data bytes and the modified pseudo data bytes produce 10-bit ECC symbols with the selected bits matching the bit pattern. The selected bits are then truncated and the remaining 8-bit symbols are concatenated with the data string to form the code-word.
摘要翻译：编码器通过首先向扇区数据字节附加一个或多个伪数据字节，使用GF（210）码来编码数据扇区以产生ECC符号。然后对扇区数据字节和伪数据字节的数据串进行编码，以产生所需数量的10位ECC符号。将来自每个ECC符号的两个选定位与已知的位模式进行比较。如果所选择的比特与模式匹配，则比特被截断，并且剩余的8比特符号与数据串相连以形成码字。随后可以对码字字节进行解码，并通过根据需要附加位模式来执行任何纠错。如果选择的比特与图案不匹配，则修改伪数据字节，使得对数据字节和修改的伪数据字节的编码产生10位ECC符号，其中所选择的位与位模式匹配。所选择的位然后被截断，并且剩余的8位符号与数据串连接以形成码字。

53. 发明授权

US06769088B1 Sector-coding technique for reduced read-after-write operations 失效
标题翻译：用于减少读写后操作的扇区编码技术
公开(公告)号：US06769088B1
公开(公告)日：2004-07-27
申请号：US09345245
申请日：1999-06-30
申请人： Lih-Jyh Weng
发明人： Lih-Jyh Weng
IPC分类号： G11C2900
CPC分类号： G11B20/1879 , G11B20/1803 , G11B2020/1836
摘要： A mechanism for providing error protection for data that is to be stored in a data storage system in which data are stored in data sectors in a data storage area and redundant information that provides error protection for the data are stored in redundant sectors in a redundant storage area. New data that is written to a designated one of the data sectors, and that is not error protected by the redundant information, is received, and error correction information for the new data is selectively stored in an additional storage area to provide error protection for the new data instead of revising the redundant information to provide such error protection.
摘要翻译：用于为要存储在数据存储系统中的数据提供错误保护的机制，其中数据存储在数据存储区域中的数据扇区中，并且为数据提供错误保护的冗余信息存储在冗余存储器中的冗余扇区中区。接收到被写入指定的一个数据扇区并且不被冗余信息保护的新数据，并且新数据的纠错信息被选择性地存储在附加的存储区域中，以便为新数据而不是修改冗余信息以提供此类错误保护。

54. 发明授权

US06643819B1 Hybrid root-finding technique 失效
标题翻译：杂交寻根技术
公开(公告)号：US06643819B1
公开(公告)日：2003-11-04
申请号：US09491523
申请日：2000-01-26
申请人： Lih-Jyh Weng
发明人： Lih-Jyh Weng
IPC分类号： H03M1300
CPC分类号： H03M13/1545 , G11B20/18 , G11B2020/1836 , H03M7/16 , H03M13/15 , H03M13/1515
摘要： A root finding mechanism uses an affine polynomial to find the roots of an error locator polynomial. The affine polynomial is produced from the error locator polynomial and field elements for generating roots of the affine polynomial are determined. Gray code is used to select the field elements used to generate the different roots of the affine polynomial. The roots are tested as possible true roots of the error locator polynomial.
摘要翻译：根寻找机制使用仿射多项式来找出错误定位器多项式的根。从误差定位多项式产生仿射多项式，并确定用于产生仿射多项式根的场元。格雷码用于选择用于生成仿射多项式的不同根的场元素。根被测试为错误定位器多项式的可能真根。

55. 发明授权

US06637002B1 Decoder for error correcting block codes 有权
标题翻译：解码器用于纠错块码
公开(公告)号：US06637002B1
公开(公告)日：2003-10-21
申请号：US09176658
申请日：1998-10-21
申请人： Lih-Jyh Weng , Ba-Zhong Shen , Shih Mo , Chung Chang
发明人： Lih-Jyh Weng , Ba-Zhong Shen , Shih Mo , Chung Chang
IPC分类号： H03M1300
CPC分类号： H03M13/1545 , H03M13/6561
摘要： A decoder for decoding block error correction codes is described. The decoder includes a first search circuit to find roots of an error location polynomial corresponding to an error location and a second search circuit to find roots of an error location polynomial corresponding to an error location. A multiplexer is fed by the first search circuit and the second search circuit to produce an error location from the error location polynomial.
摘要翻译：描述用于解码块纠错码的解码器。解码器包括：第一搜索电路，用于找出与错误位置相对应的错误位置多项式的根，以及第二搜索电路，以找到对应于错误位置的错误位置多项式的根。多路复用器由第一搜索电路和第二搜索电路馈送以从误差位置多项式产生误差位置。

56. 发明授权

US06560747B1 Error counting mechanism 失效
标题翻译：错误计数机制
公开(公告)号：US06560747B1
公开(公告)日：2003-05-06
申请号：US09437696
申请日：1999-11-10
申请人： Lih-Jyh Weng
发明人： Lih-Jyh Weng
IPC分类号： G06F1100
CPC分类号： G11B20/1816 , H03M13/151 , H03M13/1535 , H03M13/1575
摘要： A mechanism for determining a number of errors in an error correction code codeword is presented. The mechanism obtains the degree of an error locator polynomial associated with syndromes generated for the codeword without determining coefficients of the error locator polynomial. The degree is identified as the number of errors. The degree is determined from the syndromes using a Euclidean process which determines the degree without finding the coefficients. Alternatively, the degree is determined by forming a trapezoid-shaped matrix from the syndrome values and finding the rank of that matrix.
摘要翻译：提出了一种用于确定纠错码码字中的错误数量的机制。该机制获得与为码字生成的校正子相关联的误差定位多项式的程度，而不确定误差定位多项式的系数。该程度被确定为错误的数量。从使用欧几里德过程的综合征确定程度，该过程确定了度数而不发现系数。或者，通过从综合征值形成梯形矩阵并找到该矩阵的秩来确定度数。

57. 发明授权

US06463564B1 Mis-synchronization detection system 有权
公开(公告)号：US06463564B1
公开(公告)日：2002-10-08
申请号：US09395840
申请日：1999-09-14
申请人： Lih-Jyh Weng
发明人： Lih-Jyh Weng
IPC分类号： H03M1300
CPC分类号： H03M13/15 , G11B20/1803
摘要： An error correction system produces a code word for recording by XOR'ing to a data code word that is encoded in accordance with a distance d Reed-Solomon code a coset leader that is a code word of a distance d′ super code of the distance d code, but not a code word of the distance d code. When the code word is later retrieved, the system XOR's the coset leader to the retrieved code word. If there is no synchronization error, the XOR'ing operation reproduces the original data code word. If, however, there is a synchronization error, the XOR'ing operation introduces into the retrieved code word a term that is a Hamming distance of d′ from every valid code word of the distance d Reed-Solomon code. The result should then contain more errors than the ECC can correct, as long as d ′ > d 2 . The system determines the super code from which to select the coset leader based on the generator polynomial of the distance d Reed-Solomon code. For a code with a generator polynomial which has consecutive roots &agr;L&agr;L+1&agr;L+2 . . . &agr;L+d−1, where “&agr;” is a primitive element of GF(2q), the system first selects as the super code a distance d−1 Reed-Solomon code with a generator polynomial that has d−1 consecutive roots. The system then selects from such a code a coset leader b(x) that is not also a code word of the distance d code. The system next checks that the term j(x)=b(x)*xS+b(x) is not a valid code word of the distance d code for every S of interest, where −T≦S≦T and T is the maximum number of symbols by which the read/write head may be mis-synchronized. If j(x) is a valid code word of the distance d−1 code, the system selects and tests each of the remaining coset leaders from the distance d−1 codes. If none of them are appropriate, the system selects and tests the coset leaders from a distance d−2 Reed-Solomon code that has a generator polynomial with d−2 consecutive roots, and so forth. To reduce the system storage requirements, the coset leader may be selected to be a code word produced by manipulating a shortened code word of the distance d′ code. The system then stores the shortened code word and performs the necessary manipulations to produce the coset leader.

58. 发明授权

US06389573B1 Enhanced read retrial scheme 有权
标题翻译：增强阅读重试方案
公开(公告)号：US06389573B1
公开(公告)日：2002-05-14
申请号：US09343111
申请日：1999-06-29
申请人： Lih-Jyh Weng
发明人： Lih-Jyh Weng
IPC分类号： H03M1300
CPC分类号： H03M13/15
摘要： A read retrial mechanism which increases the error correction ability of a decoding operation by converting errors to erasures is presented. The mechanism reads at least two copies of a code word from memory and compares corresponding symbols to identify symbol locations for which corresponding symbols are of unequal value. At least one of the code word copies is decoded by an error-erasure decoding operation using the symbol locations identified by the comparison as erasures.
摘要翻译：提出了通过将错误转换为擦除来提高解码操作的纠错能力的读取重试机制。该机制从存储器中读取码字的至少两个副本，并比较相应的符号以识别对应符号具有不等值的符号位置。通过使用由比较识别的符号位置作为擦除的错误消除解码操作来解码码字副本中的至少一个。

59. 发明授权

US06260173B1 Combined system for producing error correction code symbols and error syndromes 有权
标题翻译：用于产生纠错码符号和错误综合征的组合系统
公开(公告)号：US06260173B1
公开(公告)日：2001-07-10
申请号：US09219472
申请日：1998-12-23
申请人： Lih-Jyh Weng , Ba-Zhong Shen , Shih Mo , Chung-Hsing Chang
发明人： Lih-Jyh Weng , Ba-Zhong Shen , Shih Mo , Chung-Hsing Chang
IPC分类号： H03M1300
CPC分类号： H03M13/158 , H03M13/1515
摘要： A combined encoding/syndrome generating circuit is segmented into multiple-cell blocks that operate in parallel during encoding operations to produce interim sums. The interim sums are then combined to propagate a sum across the system, from the first cell to the last cell. Each cell includes a Galois Field multiplier and an associated update adder and register. A block of two cells includes two sets of associated Galois Field multipliers, registers and update adders, and a block feedback adder that produces the associated interim sum by adding together the products produced in parallel by each of the cells. A block with more than two cells includes additional feedback adders that operate in parallel to selectively combine the products produced by the plurality of cells, and produce an interim sum that includes a contribution from each of the cells in the block. The system then adds together the interim sums produced simultaneously by the various blocks, to propagate a sum across the system. Also, the interim sum from a given block is combined in parallel into the products produced by the respective cells of the next block, to include in the update signals that are fed back to the associated registers the contributions from each of the previous cells. During syndrome generation operations, the cells essentially operate independently to produce the syndromes. The current system includes more feedback adders than the conventional Fettweis-Hassner circuit, however, the delay through the current system is reduced from that of the conventional system, since many of the feedback adders in the current system operate in parallel.
摘要翻译：组合编码/校正子产生电路被分割成在编码操作期间并行操作以产生临时和的多小区块。然后组合中间和以在整个系统上传播一个从第一个单元到最后一个单元的和。每个单元包括伽罗瓦域乘法器和相关联的更新加法器和寄存器。两个单元的块包括两组相关联的伽罗瓦域乘法器，寄存器和更新加法器，以及块反馈加法器，其通过将由每个单元并行产生的乘积相加来产生相关联的临时和。具有多于两个单元的块包括并行操作的选择性组合由多个单元产生的乘积的另外的反馈加法器，并且产生包括来自块中的每个单元的贡献的中间和。然后，该系统将由各个块同时产生的临时总和相加，以在系统上传播和。此外，来自给定块的中间和并行组合为由下一个块的相应小区产生的产品，以将在反馈到相关联的寄存器的更新信号中包括来自每个先前小区的贡献。在综合征发生过程中，细胞基本上独立运作以产生综合征。目前的系统包括比传统的Fettweis-Hassner电路更多的反馈加法器，然而，通过当前系统的延迟比常规系统的延迟减小，因为当前系统中的许多反馈加法器并行操作。

60. 发明授权

US06199088B1 Circuit for determining multiplicative inverses in certain galois fields 失效
标题翻译：用于确定某些伽罗瓦域中乘法反演的电路
公开(公告)号：US06199088B1
公开(公告)日：2001-03-06
申请号：US09108170
申请日：1998-06-30
申请人： Lih-Jyh Weng , Diana Langer
发明人： Lih-Jyh Weng , Diana Langer
IPC分类号： G06F700
CPC分类号： G06F7/726 , G06F1/03
摘要： A system for producing a quotient B/A, where A and B are elements of GF(22M), 2M+1 is prime and 2 is a primitive element of GF(2M+1), first determines A−1 and then multiplies B by A−1. The system uses a (2M+1)-bit representation for A and produces, directly from A, an element C=A2M+1, where C also is an element of GF(22M) which is a subfield of GF(2M). The system produces M+1 bits to represent C by performing bit manipulations that are equivalent to permuting the (2M+1)-bits to produce A2M and multiplying the permuted bits by A. The bit manipulations are: c0=&Sgr;aiai; c1=&Sgr;aiai+1 . . . cM=&Sgr;aiai+M where the aj's and cj's are the coefficients of A and C, respectively. The system retrieves C−1 from a (2M−1)-element lookup table and multiplies C−1=A−2M+1 by A2M to produce A−1. This multiplication is performed as the exclusive-OR'ing of M+1 sums of cyclically shifted copies of A2M , which is a permutation of the 2M+1 bits of A. The multiplication of B by A−1 is also performed as the exclusive-OR'ing of cyclically shifted copies of a (2M+1)-bit representation of B.
摘要翻译：用于产生商B / A的系统，其中A和B是GF（22M），2M + 1的元素，素数为2，而2是GF（2M + 1）的原始元素，首先确定A-1，然后乘以B 由A-1。系统对A使用（2M + 1）位表示，直接从A产生元素C = A2M + 1，其中C也是作为GF（2M）的子域的GF（22M）的元素。系统通过执行等同于置换（2M + 1）位来产生A2M并将置换位乘以A的位操作来产生M + 1位来表示C。位操作是：c0 = SIGMAaiai; c1 = SIGMAaiai + 1。。。 cM = SIGMAaiai + M其中aj和cj分别是A和C的系数。系统从（2M-1）元素查找表中检索C-1，并通过A2M将C-1 = A-2M + 1乘以产生A-1。该乘法被执行为作为A的2M + 1比特的置换的A2M的循环移位副本的M + 1个和的异或运算.B乘以A-1还被执行为排他性 - （B）的（2M + 1）位表示的循环移位副本。

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