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    • 51. 发明授权
    • Card adapter
    • 卡适配器
    • US06824431B2
    • 2004-11-30
    • US10207477
    • 2002-07-29
    • Tsutomu ShimadaKaname SuwaTsuguhide SakataAtsushi NishioTakashi KawasakiKazuhiro Okazaki
    • Tsutomu ShimadaKaname SuwaTsuguhide SakataAtsushi NishioTakashi KawasakiKazuhiro Okazaki
    • H01R2400
    • H01R13/6335H01R13/6582H01R13/6595
    • Disclosed herein is a card adapter for electrically connecting electrical connecting portions of a card-shaped electronic device such as a CF card to contacts in a slot for a PC card provided in a personal computer. The card adapter 1 includes a chassis 10, a pair of conducting plates 40 provided on the upper and lower sides of the chassis 10, and a grounding member 20, and the like. The grounding member 20 is used to provide an electrical path for electrically connecting a grounding contact portion of the CF card to a grounding part of the slot without using the conducting plates 40 and it is formed into a single part. By using such a grounding member 20, the card adapter 1 can directly connect the grounding contact portion of the CF card to the grounding part of the slot to accomplish stable and reliable grounding.
    • 这里公开了一种卡适配器,用于将诸如CF卡的卡形电子设备的电连接部分电连接到设置在个人计算机中的用于PC卡的插槽中的触点。 卡适配器1包括底盘10,设置在底盘10的上侧和下侧的一对导电板40和接地构件20等。 接地构件20用于提供用于将CF卡的接地接触部分电连接到槽的接地部分而不使用导电板40并且其形成为单个部件的电路径。 通过使用这样的接地构件20,卡适配器1可以将CF卡的接地部分直接连接到槽的接地部分,以实现稳定可靠的接地。
    • 57. 发明授权
    • Detection circuit for identical and simultaneous access in a parallel
processor system with a multi-way multi-port cache
    • 用于具有多路多端口缓存的并行处理器系统中相同和同时访问的检测电路
    • US5742790A
    • 1998-04-21
    • US416475
    • 1995-04-04
    • Takashi Kawasaki
    • Takashi Kawasaki
    • G06F12/08G06F12/00
    • G06F12/0853G06F12/0864
    • A detection circuit for detecting a simultaneous and identical access signal in a parallel processor. The detection circuit includes a cache memory, having multiple ports, for generating a SAME WAY HIT signal; a control signal generating circuit for generating and providing a control signal to the cache memory and for receiving the SAME WAY HIT signal from the cache memory; and adders for sending memory address signals, including a set address signal, to the cache memory through each of the multiple ports. Also included is a circuit for retrieving a set address signal from the memory address signals provided by the adders and for sending the set address signals to the control signal generating circuit, the set address being a part of a memory address signal; and an AND gate, provided the set address signals and the SAME WAY HIT signal to be sent to the control signal generating circuit, for comparing the set address signals to the cache memory and informing whether the set address signals are identical and simultaneously accessed or not.
    • 一种用于在并行处理器中检测同时且相同的存取信号的检测电路。 检测电路包括具有多个端口的高速缓冲存储器,用于产生相同的方式HIT信号; 控制信号产生电路,用于产生并向高速缓存存储器提供控制信号并从高速缓冲存储器接收SAME WAY HIT信号; 以及用于通过多个端口中的每一个将包括设置的地址信号的存储器地址信号发送到高速缓冲存储器的加法器。 还包括用于从由加法器提供的存储器地址信号中检索设置的地址信号并将设置的地址信号发送到控制信号产生电路的电路,该地址是存储器地址信号的一部分; 和“与”门,提供要发送到控制信号发生电路的设置地址信号和“相同方向”信号,用于将设置的地址信号与高速缓冲存储器进行比较,并通知设置的地址信号是否相同并且同时被访问 。