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51. 发明授权

US07449373B2 Method of ion implanting for tri-gate devices 有权
标题翻译：三栅极器件离子注入方法
公开(公告)号：US07449373B2
公开(公告)日：2008-11-11
申请号：US11394614
申请日：2006-03-31
申请人： Brian S. Doyle , Suman Datta , Jack T. Kavalieros , Amlan Majumdar
发明人： Brian S. Doyle , Suman Datta , Jack T. Kavalieros , Amlan Majumdar
IPC分类号： H01L21/00
CPC分类号： H01L21/26586 , H01L29/66803 , H01L29/7851
摘要： A method for ion implanting a tip source and drain region and halo region for a tri-gate field-effect transistor is described. A silicon body is implanted, in one embodiment, from six different angles to obtain ideal regions.
摘要翻译：描述了用于三栅极场效应晶体管的用于离子注入尖端源极和漏极区域和晕圈区域的方法。在一个实施例中，从六个不同的角度植入硅体，以获得理想的区域。

52. 发明申请

US20080237735A1 Hetero-Bimos injection process for non-volatile flash memory 有权
标题翻译：异质闪存注入过程
公开(公告)号：US20080237735A1
公开(公告)日：2008-10-02
申请号：US11731162
申请日：2007-03-30
申请人： Jack T. Kavalieros , Suman Datta , Robert S. Chau , David L. Kencke
发明人： Jack T. Kavalieros , Suman Datta , Robert S. Chau , David L. Kencke
IPC分类号： H01L27/06 , H01L21/8249
CPC分类号： H01L21/8249 , H01L21/28273 , H01L27/0705 , H01L29/0821 , H01L29/66825 , H01L29/73 , H01L29/7606 , H01L29/7881
摘要： A hetero-BiMOS injection system comprises a MOSFET transistor formed on a substrate and a hetero-bipolar transistor formed within the substrate. The bipolar transistor can be used to inject charge carriers into a floating gate of the MOSFET transistor. This is done by operating the MOSFET transistor to form an inversion layer in its channel region and operating the bipolar transistor to drive minority charge carriers from the substrate into a floating gate of the MOSFET transistor. The substrate provides a silicon emitter and a silicon germanium containing base for the bipolar transistor. The inversion layer provides a silicon collector for the bipolar transistor.
摘要翻译：异质BiMOS注入系统包括形成在衬底上的MOSFET晶体管和形成在衬底内的异质双极晶体管。双极晶体管可用于将电荷载流子注入MOSFET晶体管的浮置栅极。这通过操作MOSFET晶体管在其沟道区域中形成反型层并且操作双极晶体管来驱动少数电荷载体从衬底驱动到MOSFET晶体管的浮置栅极。衬底为双极晶体管提供硅发射极和含硅锗基底。反型层为双极晶体管提供硅集电极。

53. 发明申请

US20080237678A1 On-chip memory cell and method of manufacturing same 审中-公开
标题翻译：片上存储单元及其制造方法
公开(公告)号：US20080237678A1
公开(公告)日：2008-10-02
申请号：US11729192
申请日：2007-03-27
申请人： Suman Datta , Jack T. Kavalieros , Brian S. Doyle , Dinesh Somasekhar , Ali Keshavarzi
发明人： Suman Datta , Jack T. Kavalieros , Brian S. Doyle , Dinesh Somasekhar , Ali Keshavarzi
IPC分类号： H01L27/108 , H01L21/336
CPC分类号： H01L27/10873 , H01L27/10826 , H01L29/785
摘要： An on-chip memory cell comprises a tri-gate access transistor (145) and a tri-gate capacitor (155). The on-chip memory cell may be an embedded DRAM on a three-dimensional tri-gate transistor and capacitor structures which is fully compatible with existing tri-gate logic transistor fabrication process. Embodiments of the invention use the high fin aspect ratio and inherently superior surface area of the tri-gate transistors to replace the “trench” capacitor in a commodity DRAM with an inversion mode tri-gate capacitor. The tall sidewalls of the tri-gate transistor provide large enough surface area to provide storage capacitance in a small cell area.
摘要翻译：片上存储单元包括三栅极存取晶体管（145）和三栅极电容器（155）。片上存储器单元可以是三维三栅晶体管上的嵌入式DRAM和与现有三栅逻辑晶体管制造工艺完全兼容的电容器结构。本发明的实施例使用三栅极晶体管的高翅片长宽比和固有优越的表面积来替代具有反向模式三栅极电容器的商品DRAM中的“沟槽”电容器。三栅极晶体管的高侧壁提供足够大的表面积，以在小单元区域中提供存储电容。

54. 发明申请

US20080017891A1 PINNING LAYER FOR LOW RESISTIVITY N-TYPE SOURCE DRAIN OHMIC CONTACTS 有权
标题翻译：密封层用于低电阻N型源漏管OHMIC接触
公开(公告)号：US20080017891A1
公开(公告)日：2008-01-24
申请号：US11480667
申请日：2006-06-30
申请人： Suman Datta , Jack T. Kavalieros , Robert S. Chau , Mark L. Doczy
发明人： Suman Datta , Jack T. Kavalieros , Robert S. Chau , Mark L. Doczy
IPC分类号： H01L29/76 , H01L29/745
CPC分类号： H01L29/0847 , H01L21/28525 , H01L29/7833
摘要： A system or apparatus including an N-type transistor structure including a gate electrode formed on a substrate and source and drain regions formed in the substrate; a contact to the source region; and a pinning layer disposed between the source region and the first contact and defining an interface between the pinning layer and the source region, wherein the pinning layer has donor-type surface states in a conduction band. A method including forming a transistor structure including a gate electrode on a substrate and source and drain regions formed in the substrate; depositing a pinning layer having donor-type surface states on the source and drain regions such that an interface is defined between the pinning layer and the respective one of the source and drain regions; and forming a first contact to the source region and a second contact to the drain region.
摘要翻译：一种包括N型晶体管结构的系统或装置，包括形成在衬底上的栅电极和形成在衬底中的源区和漏区; 与源区的联系; 以及钉扎层，其设置在所述源区域和所述第一触点之间并且限定所述钉扎层和所述源区域之间的界面，其中所述钉扎层在导带中具有施主型表面状态。一种包括在衬底上形成包括栅电极的晶体管结构和形成在衬底中的源极和漏极区的方法; 在源极和漏极区域上沉积具有施主型表面状态的钉扎层，使得在钉扎层与源极和漏极区域中的相应一个之间界定界面; 以及向所述源极区域形成第一接触和向所述漏极区域形成第二接触。

55. 发明申请

US20070232078A1 In situ processing for ultra-thin gate oxide scaling 审中-公开
标题翻译：用于超薄栅氧化物缩放的原位处理
公开(公告)号：US20070232078A1
公开(公告)日：2007-10-04
申请号：US11395853
申请日：2006-03-31
申请人： Matthew V. Metz , Suman Datta , Mark L. Doczy , Jack T. Kavalieros , Robert S. Chau , Gilbert Dewey
发明人： Matthew V. Metz , Suman Datta , Mark L. Doczy , Jack T. Kavalieros , Robert S. Chau , Gilbert Dewey
IPC分类号： H01L21/31
CPC分类号： H01L29/4966 , H01L21/28088 , H01L29/513 , H01L29/6659 , H01L29/7833
摘要： A method including depositing a material for a gate electrode on a substrate over a dielectric material, the gate electrode material comprising a metal; depositing a capping material over the gate electrode material under processing conditions that will not promote any oxygen species associated with the gate electrode material to travel through the gate electrode material to the substrate; and patterning a gate electrode structure comprising the gate electrode material.
摘要翻译：一种方法，包括在电介质材料上的衬底上沉积用于栅电极的材料，所述栅电极材料包括金属; 在不会促使与栅电极材料相关联的任何氧物质通过栅极电极材料移动到衬底的加工条件下，在栅电极材料上沉积封盖材料; 以及图案化包括栅电极材料的栅电极结构。

56. 发明授权

US08294180B2 CMOS devices with a single work function gate electrode and method of fabrication 有权
标题翻译： CMOS器件具有单功能功能的栅电极和制造方法
公开(公告)号：US08294180B2
公开(公告)日：2012-10-23
申请号：US13038190
申请日：2011-03-01
申请人： Brian S. Doyle , Been-Yih Jin , Jack T. Kavalieros , Suman Datta , Justin K. Brask , Robert S. Chau
发明人： Brian S. Doyle , Been-Yih Jin , Jack T. Kavalieros , Suman Datta , Justin K. Brask , Robert S. Chau
IPC分类号： H01L29/66
CPC分类号： H01L21/845 , H01L21/823807 , H01L21/823821 , H01L21/823878 , H01L27/1211 , H01L29/0673 , H01L29/068 , H01L29/1054 , H01L29/66439 , H01L29/66795 , H01L29/775 , H01L29/785
摘要： Described herein are a device utilizing a gate electrode material with a single work function for both the pMOS and nMOS transistors where the magnitude of the transistor threshold voltages is modified by semiconductor band engineering and article made thereby. Further described herein are methods of fabricating a device formed of complementary (pMOS and nMOS) transistors having semiconductor channel regions which have been band gap engineered to achieve a low threshold voltage.
摘要翻译：这里描述了利用具有单功函数的栅电极材料的器件，用于pMOS和nMOS晶体管，其中晶体管阈值电压的幅度由半导体带工程和由此制成的制品修改。本文进一步描述的是制造由互补（pMOS和nMOS）晶体管形成的器件的方法，该晶体管具有被设计成能够实现低阈值电压的带隙的半导体沟道区。

57. 发明申请

US20120061649A1 STRAIN-INDUCING SEMICONDUCTOR REGIONS 有权
标题翻译：应变诱导半导体区域
公开(公告)号：US20120061649A1
公开(公告)日：2012-03-15
申请号：US13160886
申请日：2011-06-15
申请人： Suman Datta , Jack T. Kavalieros , Been-Yih Jin
发明人： Suman Datta , Jack T. Kavalieros , Been-Yih Jin
IPC分类号： H01L29/12 , H01L21/336
CPC分类号： H01L29/1033 , H01L29/0673 , H01L29/201 , H01L29/205 , H01L29/41725 , H01L29/66431 , H01L29/66545 , H01L29/66628 , H01L29/66636 , H01L29/66787 , H01L29/775 , H01L29/78 , H01L29/785
摘要： A method to form a strain-inducing semiconductor region is described. In one embodiment, formation of a strain-inducing semiconductor region laterally adjacent to a crystalline substrate results in a uniaxial strain imparted to the crystalline substrate, providing a strained crystalline substrate. In another embodiment, a semiconductor region with a crystalline lattice of one or more species of charge-neutral lattice-forming atoms imparts a strain to a crystalline substrate, wherein the lattice constant of the semiconductor region is different from that of the crystalline substrate, and wherein all species of charge-neutral lattice-forming atoms of the semiconductor region are contained in the crystalline substrate.
摘要翻译：描述形成应变诱导半导体区域的方法。在一个实施方案中，形成横向邻近晶体衬底的应变诱导半导体区域导致赋予晶体衬底的单轴应变，从而提供应变的晶体衬底。在另一个实施方案中，具有一种或多种电荷 - 中性晶格形成原子的晶格的半导体区域向晶体衬底赋予应变，其中半导体区域的晶格常数与晶体衬底的晶格常数不同，以及其中所述半导体区域的电荷 - 中性晶格形成原子的所有种类都包含在所述晶体衬底中。

58. 发明授权

US07989280B2 Dielectric interface for group III-V semiconductor device 有权
标题翻译： III-V族半导体器件的介质界面
公开(公告)号：US07989280B2
公开(公告)日：2011-08-02
申请号：US12338839
申请日：2008-12-18
申请人： Justin K. Brask , Suman Datta , Mark L. Doczy , James M. Blackwell , Matthew V. Metz , Jack T. Kavalieros , Robert S. Chau
发明人： Justin K. Brask , Suman Datta , Mark L. Doczy , James M. Blackwell , Matthew V. Metz , Jack T. Kavalieros , Robert S. Chau
IPC分类号： H01L21/336
CPC分类号： H01L21/314 , H01L21/02178 , H01L21/02181 , H01L21/0228 , H01L21/28008 , H01L21/3141 , H01L21/31616 , H01L21/31645 , H01L29/2003 , H01L29/495 , H01L29/513 , H01L29/517 , H01L29/66462 , H01L29/7784
摘要： A Group III-V Semiconductor device and method of fabrication is described. A high-k dielectric is interfaced to a confinement region by a chalcogenide region.
摘要翻译：描述了III-V族半导体器件及其制造方法。高k电介质通过硫族化物区域连接到约束区域。

59. 发明授权

US07902014B2 CMOS devices with a single work function gate electrode and method of fabrication 有权
标题翻译： CMOS器件具有单功能功能的栅电极和制造方法
公开(公告)号：US07902014B2
公开(公告)日：2011-03-08
申请号：US11649545
申请日：2007-01-03
申请人： Brian S. Doyle , Been-Yih Jin , Jack T. Kavalieros , Suman Datta , Justin K. Brask , Robert S. Chau
发明人： Brian S. Doyle , Been-Yih Jin , Jack T. Kavalieros , Suman Datta , Justin K. Brask , Robert S. Chau
IPC分类号： H01L21/8234
CPC分类号： H01L21/845 , H01L21/823807 , H01L21/823821 , H01L21/823878 , H01L27/1211 , H01L29/0673 , H01L29/068 , H01L29/1054 , H01L29/66439 , H01L29/66795 , H01L29/775 , H01L29/785
摘要： Described herein are a device utilizing a gate electrode material with a single work function for both the pMOS and nMOS transistors where the magnitude of the transistor threshold voltages is modified by semiconductor band engineering and article made thereby. Further described herein are methods of fabricating a device formed of complementary (pMOS and nMOS) transistors having semiconductor channel regions which have been band gap engineered to achieve a low threshold voltage.
摘要翻译：这里描述了利用具有单功函数的栅电极材料的器件，用于pMOS和nMOS晶体管，其中晶体管阈值电压的幅度由半导体带工程和由此制成的制品修改。本文进一步描述的是制造由互补（pMOS和nMOS）晶体管形成的器件的方法，该晶体管具有被设计成能够实现低阈值电压的带隙的半导体沟道区。

60. 发明授权

US07825400B2 Strain-inducing semiconductor regions 有权
标题翻译：应变诱导半导体区域
公开(公告)号：US07825400B2
公开(公告)日：2010-11-02
申请号：US11450745
申请日：2006-06-09
申请人： Suman Datta , Jack T. Kavalieros , Been-Yih Jin
发明人： Suman Datta , Jack T. Kavalieros , Been-Yih Jin
IPC分类号： H01L29/06 , H01L31/072 , H01L31/109 , H01L31/0328 , H01L31/0336
CPC分类号： H01L29/1033 , H01L29/0673 , H01L29/201 , H01L29/205 , H01L29/41725 , H01L29/66431 , H01L29/66545 , H01L29/66628 , H01L29/66636 , H01L29/66787 , H01L29/775 , H01L29/78 , H01L29/785
摘要： A method to form a strain-inducing semiconductor region is described. In one embodiment, formation of a strain-inducing semiconductor region laterally adjacent to a crystalline substrate results in a uniaxial strain imparted to the crystalline substrate, providing a strained crystalline substrate. In another embodiment, a semiconductor region with a crystalline lattice of one or more species of charge-neutral lattice-forming atoms imparts a strain to a crystalline substrate, wherein the lattice constant of the semiconductor region is different from that of the crystalline substrate, and wherein all species of charge-neutral lattice-forming atoms of the semiconductor region are contained in the crystalline substrate.
摘要翻译：描述形成应变诱导半导体区域的方法。在一个实施方案中，形成横向邻近晶体衬底的应变诱导半导体区域导致赋予晶体衬底的单轴应变，从而提供应变的晶体衬底。在另一个实施方案中，具有一种或多种电荷 - 中性晶格形成原子的晶格的半导体区域向晶体衬底赋予应变，其中半导体区域的晶格常数与晶体衬底的晶格常数不同，以及其中所述半导体区域的电荷 - 中性晶格形成原子的所有种类都包含在所述晶体衬底中。

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