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51. 发明授权

US08884665B2 Multiple-phase clock generator 有权
标题翻译：多相时钟发生器
公开(公告)号：US08884665B2
公开(公告)日：2014-11-11
申请号：US13084817
申请日：2011-04-12
申请人： Chih-Chang Lin , Chan-Hong Chern , Ming-Chieh Huang , Tao Wen Chung
发明人： Chih-Chang Lin , Chan-Hong Chern , Ming-Chieh Huang , Tao Wen Chung
IPC分类号： H03B19/00 , H03K5/15
CPC分类号： H03K5/15013
摘要： A multiple-phase clock generator includes at least one stage of dividers. A clock signal is supplied as a first stage clock input to dividers in a first stage of dividers. An N-th stage includes 2N dividers, where N is a positive integer number. Each divider in the first stage is configured to divide a first clock frequency of the first stage clock input by 2 to provide a first stage output. Each divider in the N-th stage is configured to divide an N-th clock frequency of an N-th stage clock input by 2 to provide an N-th stage output. The N-th stage outputs from the dividers in the N-th stage provide 2N-phase clock signals that are equally distributed with a same phase difference between adjacent phase clock signals.
摘要翻译：多相时钟发生器包括至少一个分频器级。时钟信号作为第一级时钟输入提供给分频器的第一级中的分频器。第N级包括2N个分频器，其中N是正整数。第一级中的每个分频器被配置为将第一级时钟输入的第一时钟频率除以2以提供第一级输出。第N级中的每个除法器被配置为将输入的第N级时钟的第N个时钟频率除以2以提供第N级输出。在第N级的分频器的第N级输出提供2N相位时钟信号，它们在相邻的相位时钟信号之间以相同的相位差均匀分布。

52. 发明授权

US08872592B2 High-speed transimpedance amplifier 有权
标题翻译：高速互阻放大器
公开(公告)号：US08872592B2
公开(公告)日：2014-10-28
申请号：US13527365
申请日：2012-06-19
申请人： Tsung-Ching Huang , Chan-Hong Chern , Tao Wen Chung , Ming-Chieh Huang , Chih-Chang Lin
发明人： Tsung-Ching Huang , Chan-Hong Chern , Tao Wen Chung , Ming-Chieh Huang , Chih-Chang Lin
IPC分类号： H03F3/08
CPC分类号： H03F3/082 , H03F1/0205 , H03F3/08 , H03F3/3022 , H03F3/45179 , H03F3/45183 , H03F2200/216 , H03F2203/30031 , H03F2203/45222 , H03F2203/45644 , H03F2203/45686 , H03F2203/45702 , H03F2203/45724
摘要： A transimpedance amplifier includes a first inverter having a first input node and a first output node. The first input node is configured to be coupled to an input signal. A second inverter has a second input node and a second output node. The second input node is configured to receive a reference voltage terminal. The first inverter and the second inverter are configured to provide a differential output voltage signal between the first output node and the second output node.
摘要翻译：跨阻放大器包括具有第一输入节点和第一输出节点的第一反相器。第一输入节点被配置为耦合到输入信号。第二反相器具有第二输入节点和第二输出节点。第二输入节点被配置为接收参考电压端子。第一反相器和第二反相器被配置为在第一输出节点和第二输出节点之间提供差分输出电压信号。

53. 发明授权

US08862951B2 Decision feedback equalizer 有权
标题翻译：决策反馈均衡器
公开(公告)号：US08862951B2
公开(公告)日：2014-10-14
申请号：US13528877
申请日：2012-06-21
申请人： Ming-Chieh Huang , Chan-Hong Chern , Tao Wen Chung , Yuwen Swei , Chih-Chang Lin , Tsung-Ching Huang
发明人： Ming-Chieh Huang , Chan-Hong Chern , Tao Wen Chung , Yuwen Swei , Chih-Chang Lin , Tsung-Ching Huang
IPC分类号： G06F11/00 , H04L27/01
CPC分类号： H04L25/03057 , H04L25/06 , H04L25/08
摘要： A circuit includes a summation circuit for receiving an input data signal and a feedback signal including a previous data bit. The summation circuit is configured to output a conditioned input data signal to a clock and data recovery circuit. A first flip-flop is coupled to an output of the summation circuit and is configured to receive a first set of bits of the conditioned input data signal and a first clock signal having a frequency that is less than a frequency at which the input data signal is received by the first summation circuit. A second flip-flop is coupled to the output of the summation circuit and is configured to receive a second set of bits of the conditioned input data signal and a second clock signal having a frequency that is less than the frequency at which the input data signal is received by the first summation circuit.
摘要翻译：电路包括用于接收输入数据信号和包括先前数据位的反馈信号的求和电路。求和电路被配置为将调节的输入数据信号输出到时钟和数据恢复电路。第一触发器耦合到求和电路的输出，并且被配置为接收经调节的输入数据信号的第一比特组和具有小于输入数据信号的频率的频率的第一时钟信号由第一求和电路接收。第二触发器耦合到求和电路的输出，并且被配置为接收经调节的输入数据信号的第二组比特和具有小于输入数据信号的频率的频率的第二时钟信号由第一求和电路接收。

54. 发明授权

US08673312B2 Method for one-step purification of recombinant Helicobacter pylori neutrophil-activating protein 有权
标题翻译：重组幽门螺杆菌嗜中性粒细胞活化蛋白一步纯化方法
公开(公告)号：US08673312B2
公开(公告)日：2014-03-18
申请号：US13560593
申请日：2012-07-27
申请人： Hua-Wen Fu , Kuo-Shun Shih , Chih-Chang Lin , Yu-Chi Yang
发明人： Hua-Wen Fu , Kuo-Shun Shih , Chih-Chang Lin , Yu-Chi Yang
IPC分类号： A61K39/38 , A61K35/00 , A61K48/00 , C12P9/00 , C07C7/12
CPC分类号： C07K14/205
摘要： Helicobacter pylori is closely associated with chronic gastritis, peptic ulcer disease, and gastric adenocarcinoma. Helicobacter pylori neutrophil-activating protein (HP-NAP), a virulence factor of Helicobacter pylori, plays an important role in pathogenesis of Helicobacter pylori infection. Since HP-NAP has been proposed as a candidate vaccine against Helicobacter pylori infection, an efficient way to obtain pure HP-NAP needs to be developed. In the present invention, recombinant HP-NAP expressed in Bacillus subtilis and Escherichia coli was purified through a single step of DEAE SEPHADEX ion-exchange chromatography with high purity. Also, purified recombinant HP-NAP was able to stimulate neutrophils to produce reactive oxygen species. Thus, recombinant HP-NAP obtained from our Bacillus subtilis expression system and Escherichia coli expression system is functionally active. Furthermore, this one-step negative purification method should provide an efficient way to purify recombinant HP-NAP expressed in Bacillus subtilis and Escherichia coli for basic studies, vaccine development, or drug design.
摘要翻译：幽门螺杆菌与慢性胃炎，消化性溃疡病和胃腺癌密切相关。幽门螺杆菌嗜中性粒细胞激活蛋白（HP-NAP）是幽门螺杆菌的毒力因子，在幽门螺杆菌感染的发病机制中起重要作用。由于HP-NAP已被提出作为针对幽门螺杆菌感染的候选疫苗，因此需要开发获得纯HP-NAP的有效途径。在本发明中，通过具有高纯度的DEAE SEPHADEX离子交换色谱法的一步纯化在枯草芽孢杆菌和大肠杆菌中表达的重组HP-NAP。此外，纯化的重组HP-NAP能够刺激嗜中性粒细胞产生活性氧。因此，从我们的枯草芽孢杆菌表达系统和大肠杆菌表达系统获得的重组HP-NAP在功能上是活性的。此外，该一步负纯化方法应提供一种有效的方法来纯化在枯草芽孢杆菌和大肠杆菌中表达的重组HP-NAP用于基础研究，疫苗开发或药物设计。

55. 发明授权

US08456942B2 Regulators regulating charge pump and memory circuits thereof 有权
标题翻译：调节电荷泵及其存储电路的调节器
公开(公告)号：US08456942B2
公开(公告)日：2013-06-04
申请号：US13535034
申请日：2012-06-27
申请人： Tien-Chun Yang , Chih-Chang Lin , Ming-Chieh Huang
发明人： Tien-Chun Yang , Chih-Chang Lin , Ming-Chieh Huang
IPC分类号： G11C5/14
CPC分类号： G11C5/145 , G11C11/4074
摘要： A regulator for regulating a charge pump is provided. The regulator includes a comparator having a first input end capable of receiving a first voltage and a second input end capable of receiving a second voltage for determining enabling or disabling the charge pump. The first voltage is associated with an output voltage of the charge pump. The second voltage is associated with an internal power voltage and a reference voltage Vref.
摘要翻译：提供了一种用于调节电荷泵的调节器。调节器包括具有能够接收第一电压的第一输入端和能够接收用于确定启动或禁用电荷泵的第二电压的第二输入端的比较器。第一电压与电荷泵的输出电压相关联。第二电压与内部电源电压和参考电压Vref相关联。

56. 发明授权

US08378756B2 Drive loop for MEMS oscillator 有权
标题翻译： MEMS振荡器的驱动环路
公开(公告)号：US08378756B2
公开(公告)日：2013-02-19
申请号：US12782064
申请日：2010-05-18
申请人： Ming-Chieh Huang , Chiang Pu , Chan-Hong Chern , Chih-Chang Lin , Yuwen Swei
发明人： Ming-Chieh Huang , Chiang Pu , Chan-Hong Chern , Chih-Chang Lin , Yuwen Swei
IPC分类号： H03B5/30 , G01C19/00
CPC分类号： H03B5/30
摘要： Some embodiments regard a method comprising: generating a current according to a movement of the MEMS device; the movement is controlled by a control signal; generating a peak voltage according to the current; and adjusting the control signal when the peak voltage is out of a predetermined range.
摘要翻译：一些实施例涉及一种方法，包括：根据MEMS装置的移动产生电流; 移动由控制信号控制; 根据电流产生峰值电压; 以及当峰值电压超出预定范围时调节控制信号。

57. 发明授权

US08354862B2 Phase-lock assistant circuitry 有权
标题翻译：锁相辅助电路
公开(公告)号：US08354862B2
公开(公告)日：2013-01-15
申请号：US13448878
申请日：2012-04-17
申请人： Chih-Chang Lin , Chan-Hong Chern , Steven Swei , Ming-Chieh Huang , Tien-Chun Yang
发明人： Chih-Chang Lin , Chan-Hong Chern , Steven Swei , Ming-Chieh Huang , Tien-Chun Yang
IPC分类号： H03D13/00
CPC分类号： H03L7/08 , H03L7/081 , H03L7/087
摘要： A circuit including a first circuit configured to receive an input signal and first, third and fifth phase clocks of a clock, and generate a first early signal indicating the clock is earlier than the input signal and a first late signal indicating the clock is later than the input signal. The circuit further includes a second circuit configured to receive an input signal and second, a fourth and sixth phase clocks of the clock, and generate a second early signal indicating the clock is earlier than the input signal and a second late signal indicating the clock is later than the input signal. The circuit further includes a third circuit configured to generate a first increase signal. The circuit further includes a fourth circuit configured to generate a first decrease signal.
摘要翻译：包括被配置为接收输入信号和时钟的第一，第三和第五相位时钟并且产生指示时钟的第一早期信号的第一电路的电路早于输入信号，并且指示时钟的第一晚信号晚于输入信号。电路还包括配置成接收时钟的输入信号和第二，第四和第六相位时钟的第二电路，并且产生指示时钟早于输入信号的第二早期信号，并且指示时钟的第二延迟信号是晚于输入信号。电路还包括被配置为产生第一增加信号的第三电路。电路还包括被配置为产生第一减小信号的第四电路。

58. 发明授权

US08179162B2 Phase-lock assistant circuitry 有权
标题翻译：锁相辅助电路
公开(公告)号：US08179162B2
公开(公告)日：2012-05-15
申请号：US12835130
申请日：2010-07-13
申请人： Chih-Chang Lin , Chan-Hong Chern , Steven Swei , Ming-Chieh Huang , Tien-Chun Yang
发明人： Chih-Chang Lin , Chan-Hong Chern , Steven Swei , Ming-Chieh Huang , Tien-Chun Yang
IPC分类号： H03D13/00 , H03L7/06
CPC分类号： H03L7/08 , H03L7/081 , H03L7/087
摘要： Some embodiments regard a circuit comprising: a first circuit configured to lock a frequency of an output clock to a frequency of a reference clock; a second circuit configured to align an input signal to a phase clock of the output clock; a third circuit configured to use a first set of phase clocks of the output clock and a second set of phase clocks of the output clock to improve alignment of the input signal to the phase clock of the output clock; and a lock detection circuit configured to turn on the first circuit when the frequency of the output clock is not locked to the frequency of the reference clock; and to turn off the first circuit and to turn on the second circuit and the third circuit when the frequency of the output clock is locked to the frequency of the reference clock.
摘要翻译：一些实施例涉及一种电路，包括：第一电路，其被配置为将输出时钟的频率锁定到参考时钟的频率; 第二电路，被配置为将输入信号与所述输出时钟的相位时钟对准; 第三电路，被配置为使用所述输出时钟的第一组相位时钟和所述输出时钟的第二组相位时钟，以改善所述输入信号与所述输出时钟的相位时钟的对准; 以及锁定检测电路，被配置为当所述输出时钟的频率未被锁定到所述参考时钟的频率时接通所述第一电路; 并且当输出时钟的频率被锁定到参考时钟的频率时，关闭第一电路并接通第二电路和第三电路。

59. 发明授权

US08068576B2 Counters and exemplary applications 有权
标题翻译：计数器和示范应用
公开(公告)号：US08068576B2
公开(公告)日：2011-11-29
申请号：US12699458
申请日：2010-02-03
申请人： Chih-Chang Lin , Tien-Chun Yang , Steven Swei
发明人： Chih-Chang Lin , Tien-Chun Yang , Steven Swei
IPC分类号： H03K21/00
CPC分类号： H03K21/38
摘要： Embodiments described herein are related to a counter. In some embodiments, the counter can be used as a divider, e.g., in a fractional PLL. In some embodiments, the counter (e.g., the main counter or counter C) includes a first counter (e.g., counter C1) and a second counter (e.g., counter C2), which, together with the first counter C1, perform the counting function for counter C. For example, if counter C is to count to the value N, then counter C1 counts, e.g., to N1, and counter C2 counts to N2 where N=N1+N2. For counter C1 to count to N1, N1 is loaded to counter C1. Similarly, for counter C2 to count to N2, N2 is loaded to counter C2. While counter C1 counts (e.g., to N1), N2 can be loaded to counter C2. After counter C1 finishes counting to N1, N2, if loaded, is available for counter C2 to start counting to this N2. Counters C1 and C2 can alternately count and thus provide continuous counting for counter C. Other embodiments and exemplary applications are also disclosed.
摘要翻译：本文描述的实施例涉及计数器。在一些实施例中，计数器可以用作分频器，例如在分数PLL中。在一些实施例中，计数器（例如，主计数器或计数器C）包括第一计数器（例如，计数器C1）和第二计数器（例如，计数器C2），其与第一计数器C1一起执行计数功能对于计数器C.例如，如果计数器C计数到值N，则计数器C1计数，例如，到N1，并且计数器C2计数到N2，其中N = N1 + N2。对于计数器C1计数到N1，N1被加载到计数器C1。类似地，对于计数器C2计数到N2，N2被加载到计数器C2。当计数器C1计数（例如，到N1）时，可以将N2加载到计数器C2。在计数器C1结束计数到N1之后，N2（如果加载）可用于计数器C2开始计数到这个N2。计数器C1和C2可以交替地计数并因此为计数器C提供连续计数。还公开了其他实施例和示例性应用。

60. 发明申请

US20110199152A1 INTEGRATED CIRCUITS INCLUDING A CHARGE PUMP CIRCUIT AND OPERATING METHODS THEREOF 有权
标题翻译：集成电路，包括充电泵电路及其工作方法
公开(公告)号：US20110199152A1
公开(公告)日：2011-08-18
申请号：US12706886
申请日：2010-02-17
申请人： Steven SWEI , Chih-Chang Lin , Tien-Chun Yang , Chan-Hong Chern , Ming-Chieh Huang
发明人： Steven SWEI , Chih-Chang Lin , Tien-Chun Yang , Chan-Hong Chern , Ming-Chieh Huang
IPC分类号： G05F1/10
CPC分类号： G05F1/10 , G05F3/02 , H03L7/0895 , H03L7/0896 , H03L7/0898
摘要： An integrated circuit includes a first current source. A second current source is electrically coupled with the first current source via a conductive line. A switch circuit is coupled between the first current source and the second current source. A first circuit is coupled between a first node and a second node. The first node is disposed between the first current source and the switch circuit. The second node is coupled with the first current source. The first circuit is configured for substantially equalizing voltages on the first node and the second node. A second circuit is coupled between a third node and a fourth node. The third node is disposed between the second current source and the switch circuit. The fourth node is disposed coupled with the second current source. The second circuit is configured for substantially equalizing voltages on the third node and the fourth node.
摘要翻译：集成电路包括第一电流源。第二电流源经由导线与第一电流源电耦合。开关电路耦合在第一电流源和第二电流源之间。第一电路耦合在第一节点和第二节点之间。第一节点设置在第一电流源和开关电路之间。第二节点与第一电流源耦合。第一电路被配置为基本上均衡第一节点和第二节点上的电压。第二电路耦合在第三节点和第四节点之间。第三节点设置在第二电流源和开关电路之间。第四节点被布置成与第二电流源耦合。第二电路被配置为基本上均衡第三节点和第四节点上的电压。

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