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51. 发明申请

US20070263433A1 Semiconductor device 有权
公开(公告)号：US20070263433A1
公开(公告)日：2007-11-15
申请号：US11812641
申请日：2007-06-20
申请人： Kenichi Osada , Kiyoo Itoh
发明人： Kenichi Osada , Kiyoo Itoh
IPC分类号： G11C5/06 , G11C11/00 , G11C8/00
CPC分类号： H01L27/24 , G11C7/04 , G11C13/0004
摘要： Memory blocks having memory cells which are comprised of vertical transistors and memory elements in which the resistance value is varied depending on the temperature imposed on the upper side thereof, are laminated to realize a highly-integrated non-volatile memory.

52. 发明申请

US20070246767A1 Semiconductor device formed on a SOI substrate 审中-公开
标题翻译：形成在SOI衬底上的半导体器件
公开(公告)号：US20070246767A1
公开(公告)日：2007-10-25
申请号：US11812694
申请日：2007-06-21
申请人： Kenichi Osada , Takayuki Kawahara , Masanao Yamaoka
发明人： Kenichi Osada , Takayuki Kawahara , Masanao Yamaoka
IPC分类号： H01L29/76
CPC分类号： H01L29/78648 , G11C11/412 , H01L21/823878 , H01L21/84 , H01L27/0928 , H01L27/11 , H01L27/1108 , H01L27/1203 , H01L29/4908 , H01L29/78609 , H01L2924/0002 , H01L2924/00
摘要： Thresholds of MISFETS of a Full Depletion-type SOI substrate cannot be controlled by changing impurity density as with bulk silicon MISFETs. Therefore, it is difficult to set a suitable threshold for each circuit. According to the semiconductor device of the present invention, gate electrodes of P-channel type MISFETs composing a memory cell are made of N-type polysilicon, gate electrodes of N-channel type MISFETs are made of P-type polysilicon and gate electrodes of P-channel type and N-channel type MISFETs of peripheral circuits and a logic circuit are made of P-type silicon germanium. A suitable threshold can be achieved for each circuit using a SOI substrate, thereby making it possible to fully leverage the characteristics of the SOI substrate.
摘要翻译：完全耗尽型SOI衬底的MISFETS的阈值不能通过改变杂质密度来控制，就像体硅硅MISFET那样。因此，难以为每个电路设定合适的阈值。根据本发明的半导体器件，构成存储单元的P沟道型MISFET的栅电极由N型多晶硅制成，N沟道型MISFET的栅电极由P型多晶硅制成，栅电极为P 通道型和外围电路的N沟道型MISFET和逻辑电路由P型硅锗制成。对于使用SOI衬底的每个电路，可以实现合适的阈值，从而可以充分利用SOI衬底的特性。

53. 发明授权

US07251157B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07251157B2
公开(公告)日：2007-07-31
申请号：US10933336
申请日：2004-09-03
申请人： Kenichi Osada , Kiyoo Itoh
发明人： Kenichi Osada , Kiyoo Itoh
IPC分类号： G11C11/00
CPC分类号： H01L27/24 , G11C7/04 , G11C13/0004
摘要： Memory blocks having memory cells which are comprised of vertical transistors and memory elements in which the resistance value is varied depending on the temperature imposed on the upper side thereof, are laminated to realize a highly-integrated non-volatile memory.
摘要翻译：具有由垂直晶体管构成的存储单元和其中电阻值根据其上侧施加的温度而变化的存储单元的存储器块被层叠以实现高度集成的非易失性存储器。

54. 发明申请

US20070159871A1 Semiconductor device with a non-erasable memory and/or a nonvolatile memory 失效
标题翻译：具有不可擦除存储器和/或非易失性存储器的半导体器件
公开(公告)号：US20070159871A1
公开(公告)日：2007-07-12
申请号：US11715918
申请日：2007-03-09
申请人： Kenichi Osada , Riichiro Takemura , Norikatsu Takaura , Nozomu Matsuzaki , Takayuki Kawahara
发明人： Kenichi Osada , Riichiro Takemura , Norikatsu Takaura , Nozomu Matsuzaki , Takayuki Kawahara
IPC分类号： G11C16/06 , G11C11/34 , G11C7/10 , G11C11/00
CPC分类号： G11C13/0004 , G11C13/0033 , G11C13/004 , G11C13/0064 , G11C13/0069 , G11C16/3454 , G11C2013/0092 , G11C2213/82
摘要： A semiconductor device comprises a plurality of memory cells, a central processing unit, a timer circuit which times a RESET time, and a timer circuit which times a SET time. A threshold voltage of an NMOS transistor of each memory cell is lower than that of the peripheral circuit, thereby easily executing a RESET operation. The direction of a flowing current is changed across the RESET operation and the SET operation, and the bit lines are activated at high speed, thus preventing system malfunctions. Further, the semiconductor device can overcome such problems as a wrong write operation and data destruction, resulting from the variation in the CMOS transistors when operating phase change elements with minimum size CMOS transistors at a core voltage (e.g. 1.2 V). According to the present invention, stable operations can be realized at a low voltage, using minimum-size cell transistors.
摘要翻译：一种半导体器件包括多个存储单元，一个中央处理单元，一个复位时间的定时器电路，以及一个定时器电路，该定时器电路需要一个SET时间。每个存储单元的NMOS晶体管的阈值电压低于外围电路的阈值电压，从而容易地执行复位操作。流过电流的方向在复位操作和SET操作中改变，位线被高速激活，从而防止系统故障。此外，半导体器件可以克服由于核心电压（例如1.2V）下操作具有最小尺寸CMOS晶体管的相位变化元件时CMOS晶体管的变化而导致的错误写入操作和数据破坏的问题。根据本发明，可以使用最小尺寸的单元晶体管在低电压下实现稳定的操作。

55. 发明授权

US07206216B2 Semiconductor device with a non-erasable memory and/or a nonvolatile memory 失效
公开(公告)号：US07206216B2
公开(公告)日：2007-04-17
申请号：US11057682
申请日：2005-02-15
申请人： Kenichi Osada , Riichiro Takemura , Norikatsu Takaura , Nozomu Matsuzaki , Takayuki Kawahara
发明人： Kenichi Osada , Riichiro Takemura , Norikatsu Takaura , Nozomu Matsuzaki , Takayuki Kawahara
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C13/0033 , G11C13/004 , G11C13/0064 , G11C13/0069 , G11C16/3454 , G11C2013/0092 , G11C2213/82
摘要： A semiconductor device comprises a plurality of memory cells, a central processing unit, a timer circuit which times a RESET time, and a timer circuit which times a SET time. A threshold voltage of an NMOS transistor of each memory cell is lower than that of the peripheral circuit, thereby easily executing a RESET operation. The direction of a flowing current is changed across the RESET operation and the SET operation, and the bit lines are activated at high speed, thus preventing system malfunctions. Further, the semiconductor device can overcome such problems as a wrong write operation and data destruction, resulting from the variation in the CMOS transistors when operating phase change elements with minimum size CMOS transistors at a core voltage (e.g. 1.2 V). According to the present invention, stable operations can be realized at a low voltage, using minimum-size cell transistors.

56. 发明申请

US20050185445A1 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US20050185445A1
公开(公告)日：2005-08-25
申请号：US11057682
申请日：2005-02-15
申请人： Kenichi Osada , Riichiro Takemura , Norikatsu Takaura , Nozomu Matsuzaki , Takayuki Kawahara
发明人： Kenichi Osada , Riichiro Takemura , Norikatsu Takaura , Nozomu Matsuzaki , Takayuki Kawahara
IPC分类号： G11C13/00 , G06F13/00 , G11C11/00 , G11C16/02 , G11C16/10 , G11C16/26 , G11C16/34 , G11C19/08 , H01L27/10 , H01L27/105
CPC分类号： G11C13/0004 , G11C13/0033 , G11C13/004 , G11C13/0064 , G11C13/0069 , G11C16/3454 , G11C2013/0092 , G11C2213/82
摘要： A semiconductor device comprises a plurality of memory cells, a central processing unit, a timer circuit which times a RESET time, and a timer circuit which times a SET time. A threshold voltage of an NMOS transistor of each memory cell is lower than that of the peripheral circuit, thereby easily executing a RESET operation. The direction of a flowing current is changed across the RESET operation and the SET operation, and the bit lines are activated at high speed, thus preventing system malfunctions. Further, the semiconductor device can overcome such problems as a wrong write operation and data destruction, resulting from the variation in the CMOS transistors when operating phase change elements with minimum size CMOS transistors at a core voltage (e.g. 1.2 V). According to the present invention, stable operations can be realized at a low voltage, using minimum-size cell transistors.
摘要翻译：一种半导体器件包括多个存储单元，一个中央处理单元，一个复位时间的定时器电路，以及一个定时器电路，该定时器电路需要一个SET时间。每个存储单元的NMOS晶体管的阈值电压低于外围电路的阈值电压，从而容易地执行复位操作。流过电流的方向在复位操作和SET操作中改变，位线被高速激活，从而防止系统故障。此外，半导体器件可以克服由于核心电压（例如1.2V）下操作具有最小尺寸CMOS晶体管的相位变化元件时CMOS晶体管的变化而导致的错误写入操作和数据破坏的问题。根据本发明，可以使用最小尺寸的单元晶体管在低电压下实现稳定的操作。

57. 发明授权

US06862227B2 Semiconductor memory device having the operating voltage of the memory cell controlled 有权
标题翻译：具有控制存储单元的工作电压的半导体存储器件
公开(公告)号：US06862227B2
公开(公告)日：2005-03-01
申请号：US10445919
申请日：2003-05-28
申请人： Masanao Yamaoka , Kenichi Osada
发明人： Masanao Yamaoka , Kenichi Osada
IPC分类号： G11C11/413 , G11C11/417 , G11C11/419 , G11C11/4193 , G11C29/02 , G11C11/41
CPC分类号： G11C29/02 , G11C5/146 , G11C5/147 , G11C11/41 , G11C11/412 , G11C11/413 , G11C11/417 , G11C11/419 , G11C29/021 , G11C29/028 , G11C2029/0409
摘要： An SRAM circuit which can be operated at a reduced operation margin, especially at a low operating voltage by increasing or optimizing the operation margin of the SRAM circuit. The threshold voltage of the produced transistor in the SRAM circuit is detected to compare the operating voltage of a memory cell with the operating voltage of a peripheral circuit in order to adjust it to the optimum value, and the substrate bias voltage is further controlled.
摘要翻译：一种SRAM电路，通过增加或优化SRAM电路的工作裕度，可以以较低的工作电压工作，特别是在低工作电压下工作。检测SRAM电路中产生的晶体管的阈值电压，以将存储单元的工作电压与外围电路的工作电压进行比较，以将其调整到最佳值，并进一步控制衬底偏置电压。

58. 发明授权

US06839268B2 Semiconductor memory apparatus, semiconductor apparatus, data processing apparatus and computer system 有权
标题翻译：半导体存储装置，半导体装置，数据处理装置及计算机系统
公开(公告)号：US06839268B2
公开(公告)日：2005-01-04
申请号：US10686569
申请日：2003-10-17
申请人： Kenichi Osada , Hisayuki Higuchi , Koichiro Ishibashi
发明人： Kenichi Osada , Hisayuki Higuchi , Koichiro Ishibashi
IPC分类号： G11C11/413 , G06F12/08 , G11C7/06 , G11C7/18 , G11C11/401 , G11C11/41 , H01L21/8244 , H01L27/11 , G11C11/00
CPC分类号： G11C7/18 , G06F12/0802 , G11C7/065
摘要： A semiconductor memory apparatus is provided with a memory array, a first global bit line connected to a sense amplifier, a second global bit line connected to a write amplifier, and a selection circuit for connecting a plurality of bit lines selectively to the first global bit line and the second global bit line.

59. 发明授权

US06756814B2 Logic circuit and semiconductor device 有权
标题翻译：逻辑电路和半导体器件
公开(公告)号：US06756814B2
公开(公告)日：2004-06-29
申请号：US10345242
申请日：2003-01-16
申请人： Yoshikazu Saitou , Kenichi Osada
发明人： Yoshikazu Saitou , Kenichi Osada
IPC分类号： H03K19175
CPC分类号： H03K19/0016
摘要： The present invention is directed to simplify a circuit for fixing an output logic of a logic gate while suppressing a subthreshold current. A logic circuit has an n-channel type first transistor capable of interrupting power supply to a logic gate in accordance with an input control signal, and a p-channel type second transistor capable of fixing an output node of the logic gate to a high level interlockingly with the power supply interrupting operation by the first transistor, and a threshold of the first transistor is set to be higher than that of a transistor as a component of the logic gate. Means for interrupting the power supply to the logic gate is realized by the first transistor, and means for fixing an output node of the logic gate to the high level is realized by the second transistor, thereby simplifying the circuit for fixing the output logic of the logic gate while suppressing a subthreshold current.
摘要翻译：本发明旨在简化用于在抑制亚阈值电流的同时固定逻辑门的输出逻辑的电路。逻辑电路具有能够根据输入控制信号中断到逻辑门的电源的n沟道型第一晶体管，以及能够将逻辑门的输出节点固定为高电平的p沟道型第二晶体管与第一晶体管的电源中断操作互锁，并且将第一晶体管的阈值设置为高于作为逻辑门的组件的晶体管的阈值。用于中断对逻辑门的电源的装置由第一晶体管实现，并且通过第二晶体管实现将逻辑门的输出节点固定为高电平的装置，从而简化用于固定逻辑门的输出逻辑的电路同时抑制亚阈值电流。

60. 发明授权

US06657911B2 Semiconductor device with low power consumption memory circuit 有权
标题翻译：具有低功耗存储电路的半导体器件
公开(公告)号：US06657911B2
公开(公告)日：2003-12-02
申请号：US10274985
申请日：2002-10-22
申请人： Masanao Yamaoka , Koichiro Ishibashi , Shigezumi Matsui , Kenichi Osada
发明人： Masanao Yamaoka , Koichiro Ishibashi , Shigezumi Matsui , Kenichi Osada
IPC分类号： G11C700
CPC分类号： G11C11/419 , G11C5/146 , G11C5/147 , G11C11/4125 , G11C11/417 , G11C2207/2227
摘要： The present invention relates to a system LSI consolidating a logic circuit and an SRAM circuit. More specifically, the present invention relates to a semiconductor device which can reduce a leakage current and the power consumption in the standby state. The logic circuit in the system LSI is provided with a power switch so as to cut off the switch at the time of standby, reducing a leakage current. At the same time, the SRAM circuit controls a substrate bias to reduce the leakage current.
摘要翻译：本发明涉及一种整合逻辑电路和SRAM电路的系统LSI。更具体地说，本发明涉及能够减少待机状态下的漏电流和功耗的半导体装置。系统LSI中的逻辑电路设置有电源开关，以便在断开时切断开关待机，减少漏电流。同时，SRAM电路控制衬底偏置以减少漏电流。

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