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51. 发明授权

US08829574B2 Method and system for a GaN vertical JFET with self-aligned source and gate 有权
标题翻译：具有自对准源极和栅极的GaN垂直JFET的方法和系统
公开(公告)号：US08829574B2
公开(公告)日：2014-09-09
申请号：US13334514
申请日：2011-12-22
申请人： Donald R. Disney , Isik C. Kizilyalli , Hui Nie , Linda Romano , Richard J. Brown , Madhan Raj
发明人： Donald R. Disney , Isik C. Kizilyalli , Hui Nie , Linda Romano , Richard J. Brown , Madhan Raj
IPC分类号： H01L29/808 , H01L21/335 , H01L29/66 , H01L29/78
CPC分类号： H01L29/66924 , H01L21/027 , H01L21/283 , H01L21/308 , H01L29/1095 , H01L29/2003 , H01L29/402 , H01L29/66446 , H01L29/66893 , H01L29/66909 , H01L29/66916 , H01L29/7832 , H01L29/808 , H01L29/8083 , H01L29/8086
摘要： A semiconductor device includes a III-nitride substrate, a first III-nitride epitaxial layer coupled to the III-nitride substrate and having a mesa, and a second III-nitride epitaxial layer coupled to a top surface of the mesa. The semiconductor device further includes a III-nitride gate structure coupled to a side surface of the mesa, and a spacer configured to provide electrical insulation between the second III-nitride epitaxial layer and the III-nitride gate structure.
摘要翻译：半导体器件包括III族氮化物衬底，耦合到III族氮化物衬底并具有台面的第一III族氮化物外延层和耦合到台面的顶表面的第二III族氮化物外延层。半导体器件还包括耦合到台面的侧表面的III族氮化物栅极结构，以及被配置为在第二III族氮化物外延层和III族氮化物栅极结构之间提供电绝缘的间隔物。

52. 发明申请

US20130146886A1 Vertical GaN JFET with Gate Source Electrodes on Regrown Gate 有权
标题翻译：垂直GaN JFET与栅极源电极在Regrown Gate
公开(公告)号：US20130146886A1
公开(公告)日：2013-06-13
申请号：US13315720
申请日：2011-12-09
申请人： Donald R. Disney , Hui Nie , Isik C. Kizilyalli , Richard J. Brown
发明人： Donald R. Disney , Hui Nie , Isik C. Kizilyalli , Richard J. Brown
IPC分类号： H01L29/808 , H01L21/335 , H01L29/20
CPC分类号： H01L29/8083 , H01L29/0623 , H01L29/2003 , H01L29/402 , H01L29/66446 , H01L29/66462 , H01L29/66909 , H01L29/66924
摘要： A semiconductor structure includes a GaN substrate with a first surface and a second surface. The GaN substrate is characterized by a first conductivity type and a first dopant concentration. A first electrode is electrically coupled to the second surface of the GaN substrate. The semiconductor structure further includes a first GaN epitaxial layer of the first conductivity type coupled to the first surface of the GaN substrate and a second GaN layer of a second conductivity type coupled to the first GaN epitaxial layer. The first GaN epitaxial layer comprises a channel region. The second GaN epitaxial layer comprises a gate region and an edge termination structure. A second electrode coupled to the gate region and a third electrode coupled to the channel region are both disposed within the edge termination structure.
摘要翻译：半导体结构包括具有第一表面和第二表面的GaN衬底。 GaN衬底的特征在于第一导电类型和第一掺杂剂浓度。第一电极电耦合到GaN衬底的第二表面。半导体结构还包括耦合到GaN衬底的第一表面的第一导电类型的第一GaN外延层和耦合到第一GaN外延层的第二导电类型的第二GaN层。第一GaN外延层包括沟道区。第二GaN外延层包括栅极区域和边缘端接结构。耦合到栅极区域的第二电极和耦合到沟道区域的第三电极都设置在边缘端接结构内。

53. 发明申请

US20130292686A1 METHOD AND SYSTEM FOR PLANAR REGROWTH IN GAN ELECTRONIC DEVICES 有权
公开(公告)号：US20130292686A1
公开(公告)日：2013-11-07
申请号：US13465812
申请日：2012-05-07
申请人： Isik C. Kizilyalli , Linda Romano , David P. Bour
发明人： Isik C. Kizilyalli , Linda Romano , David P. Bour
IPC分类号： H01L29/20 , H01L21/337 , H01L21/20
CPC分类号： H01L29/66924 , H01L29/2003 , H01L29/66446 , H01L29/7832 , H01L29/8083
摘要： A vertical JFET includes a III-nitride substrate and a III-nitride epitaxial layer of a first conductivity type coupled to the III-nitride substrate. The first III-nitride epitaxial layer has a first dopant concentration. The vertical JFET also includes a III-nitride epitaxial structure coupled to the first III-nitride epitaxial layer. The III-nitride epitaxial structure includes a set of channels of the first conductivity type and having a second dopant concentration, a set of sources of the first conductivity type, having a third dopant concentration greater than the first dopant concentration, and each characterized by a contact surface, and a set of regrown gates interspersed between the set of channels. An upper surface of the set of regrown gates is substantially coplanar with the contact surfaces of the set of sources.

54. 发明授权

US09117839B2 Method and system for planar regrowth in GAN electronic devices 有权
标题翻译： GAN电子设备中平面再生长的方法和系统
公开(公告)号：US09117839B2
公开(公告)日：2015-08-25
申请号：US13465812
申请日：2012-05-07
申请人： Isik C. Kizilyalli , Linda Romano , David P. Bour
发明人： Isik C. Kizilyalli , Linda Romano , David P. Bour
IPC分类号： H01L29/15 , H01L29/66 , H01L29/808 , H01L29/20
CPC分类号： H01L29/66924 , H01L29/2003 , H01L29/66446 , H01L29/7832 , H01L29/8083
摘要： A vertical JFET includes a III-nitride substrate and a III-nitride epitaxial layer of a first conductivity type coupled to the III-nitride substrate. The first III-nitride epitaxial layer has a first dopant concentration. The vertical JFET also includes a III-nitride epitaxial structure coupled to the first III-nitride epitaxial layer. The III-nitride epitaxial structure includes a set of channels of the first conductivity type and having a second dopant concentration, a set of sources of the first conductivity type, having a third dopant concentration greater than the first dopant concentration, and each characterized by a contact surface, and a set of regrown gates interspersed between the set of channels. An upper surface of the set of regrown gates is substantially coplanar with the contact surfaces of the set of sources.
摘要翻译：垂直JFET包括III族氮化物衬底和与III族氮化物衬底耦合的第一导电类型的III族氮化物外延层。第一III族氮化物外延层具有第一掺杂剂浓度。垂直JFET还包括耦合到第一III族氮化物外延层的III族氮化物外延结构。 III族氮化物外延结构包括一组第一导电类型的沟道并且具有第二掺杂剂浓度，第一导电类型的一组源，其具有大于第一掺杂剂浓度的第三掺杂剂浓度，并且各自的特征在于：接触表面，以及一组重新生长的门，散布在通道组之间。该组再生栅极的上表面与该组源的接触表面基本共面。

55. 发明授权

US09716196B2 Self-bypass diode function for gallium arsenide photovoltaic devices 有权
公开(公告)号：US09716196B2
公开(公告)日：2017-07-25
申请号：US13023733
申请日：2011-02-09
申请人： Hui Nie , Brendan M. Kayes , Isik C. Kizilyalli
发明人： Hui Nie , Brendan M. Kayes , Isik C. Kizilyalli
IPC分类号： H01L31/0304 , H01L27/142 , H01L31/0735 , H01L31/0443
CPC分类号： H01L31/03046 , H01L27/142 , H01L31/0304 , H01L31/0443 , H01L31/0735 , Y02E10/544 , Y02P70/521
摘要： Embodiments of the invention generally relate to photovoltaic devices. In one embodiment, a method for forming a gallium arsenide based photovoltaic device includes providing a semiconductor structure, the structure including an absorber layer comprising gallium arsenide. A bypass function is provided in a p-n junction of the semiconductor structure, where under reverse-bias conditions the p-n junction breaks down in a controlled manner by a Zener breakdown effect.

56. 发明授权

US09093591B2 Optoelectronic devices including heterojunction and intermediate layer 有权
公开(公告)号：US09093591B2
公开(公告)日：2015-07-28
申请号：US13451455
申请日：2012-04-19
申请人： Hui Nie , Brendan M. Kayes , Isik C. Kizilyalli
发明人： Hui Nie , Brendan M. Kayes , Isik C. Kizilyalli
IPC分类号： H01L21/04 , H01L31/0735 , H01L31/0224 , H01L31/18
摘要： Embodiments generally relate to optoelectronic semiconductor devices such as solar cells. In one aspect, a device includes an absorber layer made of gallium arsenide (GaAs) and having only one type of doping. An emitter layer is located closer than the absorber layer to a back side of the device and is made of a different material and having a higher bandgap than the absorber layer. A heterojunction is formed between the emitter layer and the absorber layer, and a p-n junction is formed between the emitter layer and the absorber layer and at least partially within the different material at a location offset from the heterojunction. An intermediate layer is located between the absorber layer and the emitter layer and provides the offset of the p-n junction from the heterojunction, and includes a graded layer and an ungraded back window layer.

57. 发明申请

US20130161634A1 METHOD AND SYSTEM FOR FABRICATING EDGE TERMINATION STRUCTURES IN GAN MATERIALS 有权
标题翻译：用于制造甘油材料边缘终止结构的方法和系统
公开(公告)号：US20130161634A1
公开(公告)日：2013-06-27
申请号：US13335383
申请日：2011-12-22
申请人： Donald R. Disney , Isik C. Kizilyalli , Linda Romano , Andrew Edwards , Hui Nie
发明人： Donald R. Disney , Isik C. Kizilyalli , Linda Romano , Andrew Edwards , Hui Nie
IPC分类号： H01L29/18 , H01L21/302
CPC分类号： H01L29/872 , H01L21/0495 , H01L21/2654 , H01L21/76224 , H01L29/0611 , H01L29/0619 , H01L29/0649 , H01L29/0692 , H01L29/2003 , H01L29/402
摘要： A method for fabricating an edge termination, which can be used in conjunction with GaN-based materials, includes providing a substrate of a first conductivity type. The substrate has a first surface and a second surface. The method also includes forming a first GaN epitaxial layer of the first conductivity type coupled to the first surface of the substrate and forming a second GaN epitaxial layer of a second conductivity type opposite to the first conductivity type. The second GaN epitaxial layer is coupled to the first GaN epitaxial layer. The substrate, the first GaN epitaxial layer and the second GaN epitaxial layer can be referred to as an epitaxial structure.
摘要翻译：可以与GaN基材料一起使用的用于制造边缘终端的方法包括提供第一导电类型的衬底。基板具有第一表面和第二表面。该方法还包括形成耦合到衬底的第一表面的第一导电类型的第一GaN外延层，并形成与第一导电类型相反的第二导电类型的第二GaN外延层。第二GaN外延层耦合到第一GaN外延层。衬底，第一GaN外延层和第二GaN外延层可以被称为外延结构。

58. 发明申请

US20120199188A1 METAL CONTACT FORMATION AND WINDOW ETCH STOP FOR PHOTOVOLTAIC DEVICES 审中-公开
标题翻译：金属接触形成和窗口灭火器用于光伏器件
公开(公告)号：US20120199188A1
公开(公告)日：2012-08-09
申请号：US13023844
申请日：2011-02-09
申请人： Hui NIE , Brendan M. Kayes , Isik C. Kizilyalli
发明人： Hui NIE , Brendan M. Kayes , Isik C. Kizilyalli
IPC分类号： H01L31/0216 , H01L31/18 , H01L31/04 , H01L31/0224
CPC分类号： H01L31/022425 , H01L31/035281 , H01L31/0735 , Y02E10/544
摘要： Embodiments of the invention generally relate to photovoltaic devices and more specifically, to metallic contacts disposed on photovoltaic devices and to the fabrication processes for forming such metallic contacts. In one aspect, a method for contact patterning on a photovoltaic device includes providing a semiconductor structure that includes a front contact layer and a window layer underneath the front contact layer, where the window layer also acts as an etch stop layer. At least one metal layer is deposited on the front contact layer, and a resist is applied on portions of the at least one metal layer. The at least one metal layer and the front contact layer are etched through to achieve the desired metallization.
摘要翻译：本发明的实施例一般涉及光伏器件，更具体地涉及设置在光伏器件上的金属触点和用于形成这种金属触点的制造工艺。在一个方面，一种用于在光伏器件上接触图案化的方法包括提供半导体结构，该半导体结构包括前接触层和在前接触层下方的窗口层，其中窗口层还用作蚀刻停止层。在前接触层上沉积至少一个金属层，并且将抗蚀剂施加到至少一个金属层的部分上。蚀刻至少一个金属层和前接触层以实现期望的金属化。

59. 发明授权

US09691921B2 Textured metallic back reflector 有权
公开(公告)号：US09691921B2
公开(公告)日：2017-06-27
申请号：US12904047
申请日：2010-10-13
申请人： Harry Atwater , Brendan Kayes , Isik C. Kizilyalli , Hui Nie
发明人： Harry Atwater , Brendan Kayes , Isik C. Kizilyalli , Hui Nie
IPC分类号： H01L31/00 , H01L21/00 , H01L31/0232 , H01L31/056 , H01L31/0304 , H01L31/0236 , H01L31/18 , H01L31/20 , H01L31/0693
CPC分类号： H01L31/02327 , H01L31/0236 , H01L31/02366 , H01L31/0304 , H01L31/03046 , H01L31/056 , H01L31/0693 , H01L31/18 , H01L31/184 , H01L31/1844 , H01L31/1852 , H01L31/208 , Y02E10/50 , Y02E10/52 , Y02E10/544
摘要： Embodiments of the invention generally relate to device fabrication of thin films used as solar devices or other electronic devices, and include textured back reflectors utilized in solar applications. In one embodiment, a method for forming a textured metallic back reflector which includes depositing a metallic layer on a gallium arsenide material within a thin film stack, forming an array of metallic islands from the metallic layer during an annealing process, removing or etching material from the gallium arsenide material to form apertures between the metallic islands, and depositing a metallic reflector layer to fill the apertures and cover the metallic islands. In another embodiment, a textured metallic back reflector includes an array of metallic islands disposed on a gallium arsenide material, a plurality of apertures disposed between the metallic islands and extending into the gallium arsenide material, a metallic reflector layer disposed over the metallic islands, and a plurality of reflector protrusions formed between the metallic islands and extending from the metallic reflector layer and into the apertures formed in the gallium arsenide material.

60. 发明授权

US09178099B2 Methods for forming optoelectronic devices including heterojunction 有权
标题翻译：用于形成包括异质结的光电器件的方法
公开(公告)号：US09178099B2
公开(公告)日：2015-11-03
申请号：US13451439
申请日：2012-04-19
申请人： Hui Nie , Brendan M. Kayes , Isik C. Kizilyalli
发明人： Hui Nie , Brendan M. Kayes , Isik C. Kizilyalli
IPC分类号： H01L31/0304 , H01L31/0735 , H01L31/0224 , H01L31/18
CPC分类号： H01L31/0735 , H01L31/022441 , H01L31/1896 , Y02E10/52 , Y02E10/544
摘要： Embodiments generally relate to optoelectronic semiconductor devices such as photovoltaic cells. In one aspect, a method for forming a device includes forming an absorber layer made of gallium arsenide (GaAs) and having one type of doping, and forming an emitter layer made of a different material and having a higher bandgap than the absorber layer. An intermediate layer can be formed between emitter and absorber layers. A heterojunction and p-n junction are formed between the emitter layer and the absorber layer, where the p-n junction is formed at least partially within the different material at a location offset from the heterojunction. A majority of the absorber layer can be outside of a depletion region formed by the p-n junction. The p-n junction causes a voltage to be generated in the cell in response to the cell being exposed to light at a front side.
摘要翻译：实施例通常涉及诸如光伏电池的光电半导体器件。一方面，用于形成器件的方法包括形成由砷化镓（GaAs）制成并具有一种类型的掺杂的吸收层，并形成由不同材料制成并具有比吸收层更高的带隙的发射极层。可以在发射极和吸收层之间形成中间层。在发射极层和吸收层之间形成异质结和p-n结，其中在与异质结偏离的位置处至少部分地在不同的材料内形成p-n结。吸收层的大部分可以在由p-n结形成的耗尽区的外部。 p-n结导致电池响应于电池暴露于正面的光而产生电压。

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