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51. 发明授权

US06509233B2 Method of making trench-gated MOSFET having cesium gate oxide layer 有权
公开(公告)号：US06509233B2
公开(公告)日：2003-01-21
申请号：US10094476
申请日：2002-03-07
申请人： Mike Chang , Sik Lui , Sung-Shan Tai
发明人： Mike Chang , Sik Lui , Sung-Shan Tai
IPC分类号： H01L21336
CPC分类号： H01L29/7813 , H01L21/28167 , H01L21/31155 , H01L29/42368 , H01L29/517
摘要： Cesium is implanted into the gate oxide layer of a vertical trench-gated MOSFET. The cesium, which is an electropositive material, reduces the threshold voltage of the device and lowers the on-resistance by improving the accumulation region adjacent the bottom of the trench.

52. 发明授权

US08394702B2 Method for making dual gate oxide trench MOSFET with channel stop using three or four masks process 有权
标题翻译：使用三个或四个掩模工艺制造具有通道停止的双栅氧化物沟槽MOSFET的方法
公开(公告)号：US08394702B2
公开(公告)日：2013-03-12
申请号：US12782573
申请日：2010-05-18
申请人： Sung-Shan Tai , Sik Lui , Xiaobin Wang
发明人： Sung-Shan Tai , Sik Lui , Xiaobin Wang
IPC分类号： H01L21/336 , H01L21/8249 , H01L21/425 , H01L21/20 , H01L29/66
CPC分类号： H01L29/7813 , H01L29/0638 , H01L29/0653 , H01L29/0878 , H01L29/407 , H01L29/41766 , H01L29/4236 , H01L29/456 , H01L29/66727 , H01L29/66734 , H01L29/7811
摘要： A semiconductor device and fabrication methods are disclosed. The device includes a plurality of gate electrodes formed in trenches located in an active region of a semiconductor substrate. A first gate runner is formed in the substrate and electrically connected to the gate electrodes, wherein the first gate runner surrounds the active region. A second gate runner is connected to the first gate runner and located between the active region and a termination region. A termination structure surrounds the first and second gate runners and the active region. The termination structure includes a conductive material in an insulator-lined trench in the substrate, wherein the termination structure is electrically shorted to a source or body layer of the substrate thereby forming a channel stop for the device.
摘要翻译：公开了半导体器件和制造方法。该器件包括形成在位于半导体衬底的有源区中的沟槽中的多个栅电极。第一栅极流道形成在基板中并电连接到栅电极，其中第一栅极流道围绕有源区。第二浇口浇道连接到第一浇口浇道并且位于活性区域和终止区域之间。终端结构围绕第一和第二栅极流道和有源区域。端接结构包括在衬底中的绝缘体衬里的沟槽中的导电材料，其中端接结构电气短路到衬底的源极或体层，从而形成用于器件的通道停止。

53. 发明授权

US08324711B2 Precision high-frequency capacitor formed on semiconductor substrate 有权
标题翻译：精密高频电容器形成于半导体基板上
公开(公告)号：US08324711B2
公开(公告)日：2012-12-04
申请号：US13075752
申请日：2011-03-30
申请人： Haim Goldberger , Sik Lui , Jacek Korec , Y. Mohammed Kasem , Harianto Wong , Jack Van Den Heuvel
发明人： Haim Goldberger , Sik Lui , Jacek Korec , Y. Mohammed Kasem , Harianto Wong , Jack Van Den Heuvel
IPC分类号： H01L21/02
CPC分类号： H01G4/33 , H01G4/38 , H01L23/481 , H01L28/40 , H01L29/66181 , H01L29/945 , H01L2224/0401 , H01L2224/05 , H01L2224/13025 , H01L2224/131 , H01L2924/13091 , Y10S438/957 , H01L2924/014 , H01L2924/00
摘要： A precision high-frequency capacitor includes a dielectric layer formed on the front side surface of a semiconductor substrate and a first electrode on top of the dielectric layer. The semiconductor substrate is heavily doped and therefore has a low resistivity. A second electrode, insulated from the first electrode, is also formed over the front side surface. In one embodiment, the second electrode is connected by a metal-filled via to a layer of conductive material on the back side of the substrate. In alternative embodiments, the via is omitted and the second electrode is either in electrical contact with the substrate or is formed on top of the dielectric layer, yielding a pair of series-connected capacitors. ESD protection for the capacitor can be provided by a pair of oppositely-directed diodes formed in the substrate and connected in parallel with the capacitor. To increase the capacitance of the capacitor while maintaining a low effective series resistance, each of the electrodes may include a plurality of fingers, which are interdigitated with the fingers of the other electrode. The capacitor is preferably fabricated in a wafer-scale process concurrently with numerous other capacitors on the wafer, and the capacitors are then separated from each other by a conventional dicing technique.
摘要翻译：精密高频电容器包括形成在半导体衬底的前侧表面上的电介质层和位于电介质层顶部的第一电极。半导体衬底是重掺杂的，因此具有低电阻率。与第一电极绝缘的第二电极也形成在前侧表面上。在一个实施例中，第二电极通过金属填充的通孔连接到衬底背面上的导电材料层。在替代实施例中，省略通孔，并且第二电极与衬底电接触或者形成在电介质层的顶部，从而产生一对串联电容器。电容器的ESD保护可以由形成在衬底中并与电容器并联连接的一对相反方向的二极管提供。为了在保持低有效串联电阻的同时增加电容器的电容，每个电极可以包括与另一个电极的指状物交叉的多个指状物。电容器优选与晶片上的许多其它电容器同时地以晶片级工艺制造，然后通过常规的切割技术将电容器彼此分离。

54. 发明申请

US20120074896A1 Semiconductor Device Die with Integrated MOSFET and Low Forward Voltage Diode-Connected Enhancement Mode JFET and Method 有权
标题翻译：具有集成MOSFET和低正向电压二极管连接增强模式JFET和方法的半导体器件芯片
公开(公告)号：US20120074896A1
公开(公告)日：2012-03-29
申请号：US12893978
申请日：2010-09-29
申请人： Sik Lui , Wei Wang
发明人： Sik Lui , Wei Wang
IPC分类号： H02J7/00 , H01L21/8232 , H01L27/06
CPC分类号： H01L27/0617 , H01L27/098
摘要： A semiconductor die with integrated MOSFET and diode-connected enhancement mode JFET is disclosed. The MOSFET-JFET die includes common semiconductor substrate region (CSSR) of type-1 conductivity. A MOSFET device and a diode-connected enhancement mode JFET (DCE-JFET) device are located upon CSSR. The DCE-JFET device has the CSSR as its DCE-JFET drain. At least two DCE-JFET gate regions of type-2 conductivity located upon the DCE-JFET drain and laterally separated from each other with a DCE-JFET gate spacing. At least a DCE-JFET source of type-1 conductivity located upon the CSSR and between the DCE-JFET gates. A top DCE-JFET electrode, located atop and in contact with the DCE-JFET gate regions and DCE-JFET source regions. When properly configured, the DCE-JFET simultaneously exhibits a forward voltage Vf substantially lower than that of a PN junction diode while the reverse leakage current can be made comparable to that of a PN junction diode.
摘要翻译：公开了具有集成MOSFET和二极管连接的增强型JFET的半导体管芯。 MOSFET-JFET管芯包括类型1导电性的公共半导体衬底区域（CSSR）。 MOSFET器件和二极管连接的增强型JFET（DCE-JFET）器件位于CSSR上。 DCE-JFET器件具有CSSR作为其DCE-JFET漏极。至少两个DCE-JFET栅极区域，位于DCE-JFET漏极上，并以DCE-JFET栅极间隔彼此横向分离。至少一个位于CSSR上和DCE-JFET门之间的类型1电导率的DCE-JFET源。位于顶部并与DCE-JFET栅极区域和DCE-JFET源极区域接触的顶部DCE-JFET电极。当正确配置时，DCE-JFET同时呈现基本上低于PN结二极管的正向电压Vf，而反向漏电流可以与PN结二极管的相反。

55. 发明申请

US20110233667A1 DUAL GATE OXIDE TRENCH MOSFET WITH CHANNEL STOP TRENCH AND THREE OR FOUR MASKS PROCESS 有权
标题翻译：具有通道停止通道和三个或四个屏蔽过程的双栅氧化物晶体管
公开(公告)号：US20110233667A1
公开(公告)日：2011-09-29
申请号：US12782573
申请日：2010-05-18
申请人： Sung-Shan Tai , Sik Lui , Xiaobin Wang
发明人： Sung-Shan Tai , Sik Lui , Xiaobin Wang
IPC分类号： H01L29/78 , H01L21/336 , H01L27/088
CPC分类号： H01L29/7813 , H01L29/0638 , H01L29/0653 , H01L29/0878 , H01L29/407 , H01L29/41766 , H01L29/4236 , H01L29/456 , H01L29/66727 , H01L29/66734 , H01L29/7811
摘要： A semiconductor device and fabrication methods are disclosed. The device includes a plurality of gate electrodes formed in trenches located in an active region of a semiconductor substrate. A first gate runner is formed in the substrate and electrically connected to the gate electrodes, wherein the first gate runner surrounds the active region. A second gate runner is connected to the first gate runner and located between the active region and a termination region. A termination structure surrounds the first and second gate runners and the active region. The termination structure includes a conductive material in an insulator-lined trench in the substrate, wherein the termination structure is electrically shorted to a source or body layer of the substrate thereby forming a channel stop for the device.
摘要翻译：公开了半导体器件和制造方法。该器件包括形成在位于半导体衬底的有源区域中的沟槽中的多个栅电极。第一栅极流道形成在基板中并电连接到栅电极，其中第一栅极流道围绕有源区。第二浇口浇道连接到第一浇口浇道并且位于活性区域和终止区域之间。终端结构围绕第一和第二栅极流道和有源区域。端接结构包括在衬底中的绝缘体衬里的沟槽中的导电材料，其中端接结构电气短路到衬底的源极或体层，从而形成用于器件的通道停止。

56. 发明授权

US08753935B1 High frequency switching MOSFETs with low output capacitance using a depletable P-shield 有权
标题翻译：具有低输出电容的高频开关MOSFET，采用可消耗P型屏蔽
公开(公告)号：US08753935B1
公开(公告)日：2014-06-17
申请号：US13724093
申请日：2012-12-21
申请人： Madhur Bobde , Hamza Yilmaz , Sik Lui , Daniel Ng
发明人： Madhur Bobde , Hamza Yilmaz , Sik Lui , Daniel Ng
IPC分类号： H01L21/336 , H01L21/28 , H01L29/40 , H01L29/423
CPC分类号： H01L29/7813 , H01L21/2257 , H01L27/0251 , H01L27/04 , H01L29/0619 , H01L29/0623 , H01L29/0634 , H01L29/0696 , H01L29/1095 , H01L29/407 , H01L29/41766 , H01L29/42368 , H01L29/4238 , H01L29/456 , H01L29/47 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/7808 , H01L29/7811
摘要： Aspects of the present disclosure describe a high density trench-based power MOSFETs with self-aligned source contacts and methods for making such devices. The source contacts are self-aligned with spacers and the active devices may have a two-step gate oxide. A lower portion may have a thickness that is larger than the thickness of an upper portion of the gate oxide. The MOSFETS also may include a depletable shield in a lower portion of the substrate. The depletable shield may be configured such that during a high drain bias the shield substantially depletes. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
摘要翻译：本公开的方面描述了具有自对准源触点的高密度沟槽基功率MOSFET和用于制造这种器件的方法。源触点与间隔物自对准，并且有源器件可以具有两步栅极氧化物。下部可以具有比栅极氧化物的上部的厚度大的厚度。 MOSFET也可以在衬底的下部包括可消除的屏蔽。可消除的屏蔽可以被配置成使得在高排水偏压期间，屏蔽件基本上消耗掉。要强调的是，提供这个摘要是为了符合要求摘要的规则，允许搜索者或其他读者快速确定技术公开内容的主题。提交它的理解是，它不会用于解释或限制权利要求的范围或含义。

57. 发明申请

US20130175612A1 DUAL GATE OXIDE TRENCH MOSFET WITH CHANNEL STOP TRENCH 有权
标题翻译：具有通道停止电位器的双栅氧化物晶体管MOSFET
公开(公告)号：US20130175612A1
公开(公告)日：2013-07-11
申请号：US13780579
申请日：2013-02-28
申请人： Sung-Shan Tai , Sik Lui , Xiaobin Wang
发明人： Sung-Shan Tai , Sik Lui , Xiaobin Wang
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L29/0638 , H01L29/0653 , H01L29/0878 , H01L29/407 , H01L29/41766 , H01L29/4236 , H01L29/456 , H01L29/66727 , H01L29/66734 , H01L29/7811
摘要： A semiconductor device and fabrication methods are disclosed. The device includes a plurality of gate electrodes formed in trenches located in an active region of a semiconductor substrate. A first gate runner is formed in the substrate and electrically connected to the gate electrodes, wherein the first gate runner surrounds the active region. A second gate runner is connected to the first gate runner and located between the active region and a termination region. A termination structure surrounds the first and second gate runners and the active region. The termination structure includes a conductive material in an insulator-lined trench in the substrate, wherein the termination structure is electrically shorted to a source or body layer of the substrate thereby forming a channel stop for the device.
摘要翻译：公开了半导体器件和制造方法。该器件包括形成在位于半导体衬底的有源区中的沟槽中的多个栅电极。第一栅极流道形成在基板中并电连接到栅电极，其中第一栅极流道围绕有源区。第二浇口浇道连接到第一浇口浇道并且位于活性区域和终止区域之间。终端结构围绕第一和第二栅极流道和有源区域。端接结构包括在衬底中的绝缘体衬里的沟槽中的导电材料，其中端接结构电气短路到衬底的源极或体层，从而形成用于器件的通道停止。

58. 发明申请

US20080108202A1 PRECISION HIGH-FREQUENCY CAPACITOR FORMED ON SEMICONDUCTOR SUBSTRATE 有权
标题翻译：精密高频电容器在半导体衬底上形成
公开(公告)号：US20080108202A1
公开(公告)日：2008-05-08
申请号：US11966965
申请日：2007-12-28
申请人： Haim Goldberger , Sik Lui , Jacek Korec , Y. Kasem , Harianto Wong , Jack Van Den Heuvel
发明人： Haim Goldberger , Sik Lui , Jacek Korec , Y. Kasem , Harianto Wong , Jack Van Den Heuvel
IPC分类号： H01L21/283
CPC分类号： H01G4/33 , H01G4/38 , H01L23/481 , H01L28/40 , H01L29/66181 , H01L29/945 , H01L2224/0401 , H01L2224/05 , H01L2224/13025 , H01L2224/131 , H01L2924/13091 , Y10S438/957 , H01L2924/014 , H01L2924/00
摘要： A method of fabricating a capacitor in a semiconductor substrate. The semiconductor substrate is doped to have a low resistivity. A second electrode, insulated from a first electrode, is formed over a front side surface and connected by a metal-filled via to the back side surface. The via may be omitted and the second electrode may be in electrical contact with the substrate or may be formed on top of the dielectric layer, yielding a pair of series-connected capacitors. ESD protection for the capacitor is provided by a pair of oppositely-directed diodes formed in the substrate connected in parallel with the capacitor. Capacitance is increased while maintaining a low effective series resistance. Electrodes include a plurality of fingers, which are interdigitated with the fingers of other electrode. The capacitor is fabricated in a wafer-scale process with other capacitors, where capacitors are separated from each other by a dicing technique.
摘要翻译：一种在半导体衬底中制造电容器的方法。掺杂半导体衬底以具有低电阻率。与第一电极绝缘的第二电极形成在前侧表面上，并且通过金属填充的通孔连接到背侧表面。可以省略通孔，并且第二电极可以与衬底电接触，或者可以形成在介电层的顶部，从而产生一对串联电容器。电容器的ESD保护由形成在与电容器并联连接的衬底中的一对相反方向的二极管提供。电容增加同时保持低有效的串联电阻。电极包括多个指状物，其与另一个电极的指状物交叉指向。电容器采用具有其他电容器的晶片级工艺制造，其中电容器通过切割技术彼此分离。

59. 发明授权

US09136060B2 Precision high-frequency capacitor formed on semiconductor substrate 有权
标题翻译：精密高频电容器形成于半导体基板上
公开(公告)号：US09136060B2
公开(公告)日：2015-09-15
申请号：US11966965
申请日：2007-12-28
申请人： Haim Goldberger , Sik Lui , Jacek Korec , Y. Mohammed Kasem , Harianto Wong , Jack Van Den Heuvel
发明人： Haim Goldberger , Sik Lui , Jacek Korec , Y. Mohammed Kasem , Harianto Wong , Jack Van Den Heuvel
IPC分类号： H01L21/20 , H01G4/33 , H01G4/38 , H01L49/02 , H01L29/94 , H01L29/66 , H01L23/48
CPC分类号： H01G4/33 , H01G4/38 , H01L23/481 , H01L28/40 , H01L29/66181 , H01L29/945 , H01L2224/0401 , H01L2224/05 , H01L2224/13025 , H01L2224/131 , H01L2924/13091 , Y10S438/957 , H01L2924/014 , H01L2924/00
摘要： A method of fabricating a capacitor in a semiconductor substrate. The semiconductor substrate is doped to have a low resistivity. A second electrode, insulated from a first electrode, is formed over a front side surface and connected by a metal-filled via to the back side surface. The via may be omitted and the second electrode may be in electrical contact with the substrate or may be formed on top of the dielectric layer, yielding a pair of series-connected capacitors. ESD protection for the capacitor is provided by a pair of oppositely-directed diodes formed in the substrate connected in parallel with the capacitor. Capacitance is increased while maintaining a low effective series resistance. Electrodes include a plurality of fingers, which are interdigitated with the fingers of other electrode. The capacitor is fabricated in a wafer-scale process with other capacitors, where capacitors are separated from each other by a dicing technique.
摘要翻译：一种在半导体衬底中制造电容器的方法。掺杂半导体衬底以具有低电阻率。与第一电极绝缘的第二电极形成在前侧表面上，并且通过金属填充的通孔连接到背侧表面。可以省略通孔，并且第二电极可以与衬底电接触，或者可以形成在介电层的顶部，从而产生一对串联电容器。电容器的ESD保护由形成在与电容器并联连接的衬底中的一对相反方向的二极管提供。电容增加同时保持低有效的串联电阻。电极包括多个指状物，其与另一个电极的指状物交叉指向。电容器采用具有其他电容器的晶片级工艺制造，其中电容器通过切割技术彼此分离。

60. 发明授权

US08669613B2 Semiconductor device die with integrated MOSFET and low forward voltage diode-connected enhancement mode JFET and method 有权
标题翻译：具有集成MOSFET和低正压二极管连接增强型JFET和方法的半导体器件裸片
公开(公告)号：US08669613B2
公开(公告)日：2014-03-11
申请号：US12893978
申请日：2010-09-29
申请人： Sik Lui , Wei Wang
发明人： Sik Lui , Wei Wang
IPC分类号： H01L29/66
CPC分类号： H01L27/0617 , H01L27/098
摘要： A semiconductor die with integrated MOSFET and diode-connected enhancement mode JFET is disclosed. The MOSFET-JFET die includes common semiconductor substrate region (CSSR) of type-1 conductivity. A MOSFET device and a diode-connected enhancement mode JFET (DCE-JFET) device are located upon CSSR. The DCE-JFET device has the CSSR as its DCE-JFET drain. At least two DCE-JFET gate regions of type-2 conductivity located upon the DCE-JFET drain and laterally separated from each other with a DCE-JFET gate spacing. At least a DCE-JFET source of type-1 conductivity located upon the CSSR and between the DCE-JFET gates. A top DCE-JFET electrode, located atop and in contact with the DCE-JFET gate regions and DCE-JFET source regions. When properly configured, the DCE-JFET simultaneously exhibits a forward voltage Vf substantially lower than that of a PN junction diode while the reverse leakage current can be made comparable to that of a PN junction diode.
摘要翻译：公开了具有集成MOSFET和二极管连接的增强型JFET的半导体管芯。 MOSFET-JFET管芯包括类型1导电性的公共半导体衬底区域（CSSR）。 MOSFET器件和二极管连接的增强型JFET（DCE-JFET）器件位于CSSR上。 DCE-JFET器件具有CSSR作为其DCE-JFET漏极。至少两个DCE-JFET栅极区域，位于DCE-JFET漏极上，并以DCE-JFET栅极间隔彼此横向分离。至少一个位于CSSR上和DCE-JFET门之间的类型1电导率的DCE-JFET源。位于顶部并与DCE-JFET栅极区域和DCE-JFET源极区域接触的顶部DCE-JFET电极。当正确配置时，DCE-JFET同时呈现基本上低于PN结二极管的正向电压Vf，而反向漏电流可以与PN结二极管的相反。

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