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51. 发明申请

US20060255826A1 Systems and methods for testing microelectronic imagers and microfeature devices 有权
标题翻译：用于测试微电子成像器和微特征器件的系统和方法
公开(公告)号：US20060255826A1
公开(公告)日：2006-11-16
申请号：US11409060
申请日：2006-04-24
申请人： Salman Akram , William Hiatt , Alan Wood , Charles Watkins , Kyle Kirby
发明人： Salman Akram , William Hiatt , Alan Wood , Charles Watkins , Kyle Kirby
IPC分类号： G01R31/26
CPC分类号： G01R31/2635 , G01R31/2831
摘要： Systems and methods for testing microelectronic imagers and microfeature devices are disclosed herein. In one embodiment, a method includes providing a microfeature workpiece including a substrate having a front side, a backside, and a plurality of microelectronic dies. The individual dies include an integrated circuit and a plurality of contact pads at the backside of the substrate operatively coupled to the integrated circuit. The method includes contacting individual contact pads with corresponding pins of a probe card. The method further includes testing the dies. In another embodiment, the individual dies can further comprise an image sensor at the front side of the substrate and operatively coupled to the integrated circuit. The image sensors are illuminated while the dies are tested.
摘要翻译：本文公开了用于测试微电子成像器和微特征器件的系统和方法。在一个实施例中，一种方法包括提供微功能工件，其包括具有正面，背面和多个微电子管芯的衬底。各个管芯包括集成电路和在衬底的背面可操作地耦合到集成电路的多个接触焊盘。该方法包括使各个接触垫与探针卡的相应引脚接触。该方法还包括测试模具。在另一个实施例中，各个管芯还可以包括在衬底的前侧的图像传感器，并可操作地耦合到集成电路。在测试模具时，图像传感器被照亮。

52. 发明授权

US07129156B2 Method for fabricating a silicon carbide interconnect for semiconductor components using heating 失效
标题翻译：使用加热制造半导体元件的碳化硅互连的方法
公开(公告)号：US07129156B2
公开(公告)日：2006-10-31
申请号：US11259508
申请日：2005-10-26
申请人： Salman Akram , Alan G. Wood
发明人： Salman Akram , Alan G. Wood
IPC分类号： H01L21/44
CPC分类号： H01L23/147 , G01R1/06711 , G01R1/06755 , G01R1/07314 , G01R3/00 , H01L23/13 , H01L23/498 , H01L23/49838 , H01L23/49872 , H01L23/49877 , H01L2924/0002 , H01L2924/09701 , H01L2924/00
摘要： An interconnect for semiconductor components includes a substrate, and interconnect contacts on the substrate for electrically engaging component contacts on the components. The interconnect contacts include silicon carbide conductive layers, and conductors in electrical communication with the silicon carbide conductive layers. The silicon carbide conductive layers provides a wear resistant surface, and improved heat transfer between the component contacts and the interconnect contacts. The silicon carbide conductive layers can comprise doped silicon carbide, or alternately thermally oxidized silicon carbide. The interconnect can be configured for use with a testing apparatus for testing discrete components such as dice or chip scale packages, or alternately for use with a testing apparatus for testing wafer sized components, such as wafers, panels and boards. In addition, the interconnect can be configured for constructing semiconductor packages and electronic assemblies such as multi chip modules.
摘要翻译：用于半导体部件的互连件包括衬底和衬底上的互连触点，用于电连接部件上的组件触点。互连触点包括碳化硅导电层和与碳化硅导电层电连通的导体。碳化硅导电层提供耐磨表面，并且改善部件触点和互连触点之间的热传递。碳化硅导电层可以包括掺杂的碳化硅，或交替地热氧化的碳化硅。互连可以被配置用于与用于测试分立元件（例如骰子或芯片尺寸封装）的测试设备一起使用，或者替代地与用于测试晶片尺寸的元件（例如晶片，面板和板）的测试设备一起使用。此外，互连可以被配置用于构造半导体封装和诸如多芯片模块的电子组件。

53. 发明授权

US07129114B2 Methods relating to singulating semiconductor wafers and wafer scale assemblies 有权
标题翻译：关于单片半导体晶片和晶片标尺组件的方法
公开(公告)号：US07129114B2
公开(公告)日：2006-10-31
申请号：US10797504
申请日：2004-03-10
申请人： Salman Akram
发明人： Salman Akram
IPC分类号： H01L21/44 , H01L21/46
CPC分类号： H01L21/78 , B23K26/364 , B23K26/40 , B23K2103/50 , B28D1/221 , B28D5/00 , H01L2224/11
摘要： Methods relating to the singulation of dice from semiconductor wafers. Trenches or channels are formed in the bottom surface of a semiconductor wafer, corresponding in location to the wafer streets. The trenches may be formed by etching or through an initial laser cut. The wafer is then singulated along the streets with a laser preferably having a beam narrower than the trenches. Multiple, laterally spaced lasers may be used in combination during a single pass to perform simultaneous singulating cuts. Additional edge protection for integrated circuitry on the active surface of the semiconductor dice may be provided by forming trenches or channels along the streets in the active surface instead of the bottom surface, disposing protective material along the streets and within the trenches prior to singulation and cutting through the wafer, leaving protective material on the sidewalls of the channels.
摘要翻译：关于从半导体晶片分割骰子的方法。沟槽或通道形成在半导体晶片的底表面中，对应于晶片街道的位置。沟槽可以通过蚀刻或通过初始激光切割形成。然后使用激光器沿着街道将晶片分割成优选地具有比沟槽窄的光束。在单次通过期间可以组合使用多个横向间隔开的激光器，以执行同时分割切割。在半导体晶片的有源表面上的集成电路的附加边缘保护可以通过在有源表面中的街道上形成沟槽或沟道而不是底表面来提供，在切割和切割之前沿街道和沟槽内布置保护材料通过晶片，将保护材料留在通道的侧壁上。

54. 发明授权

US07115961B2 Packaged microelectronic imaging devices and methods of packaging microelectronic imaging devices 有权
标题翻译：封装的微电子成像装置和封装微电子成像装置的方法
公开(公告)号：US07115961B2
公开(公告)日：2006-10-03
申请号：US10925502
申请日：2004-08-24
申请人： Charles M. Watkins , David R. Hembree , Peter A. Benson , Salman Akram
发明人： Charles M. Watkins , David R. Hembree , Peter A. Benson , Salman Akram
IPC分类号： H01L31/203
CPC分类号： H01L27/14625 , H01L24/94 , H01L27/14618 , H01L27/14634 , H01L27/1469 , H01L31/0203 , H01L2224/48091 , H01L2224/48227 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01077 , H01L2924/01078 , H01L2924/14 , H01L2924/00014 , H01L2924/00
摘要： Microelectronic imaging devices and methods of packaging microelectronic imaging devices are disclosed herein. In one embodiment, a microelectronic imaging device includes a microelectronic die having an integrated circuit, an image sensor electrically coupled to the integrated circuit, and a plurality of bond-pads electrically coupled to the integrated circuit. The imaging device further includes a cover over the image sensor and a plurality of interconnects in and/or on the cover that are electrically coupled to corresponding bond-pads of the die. The interconnects provide external electrical contacts for the bond-pads of the die. The interconnects can extend through the cover or along a surface of the cover.
摘要翻译：本文公开了微电子成像装置和包装微电子成像装置的方法。在一个实施例中，微电子成像装置包括具有集成电路的微电子管芯，电耦合到集成电路的图像传感器，以及电耦合到集成电路的多个接合焊盘。所述成像装置还包括覆盖在所述图像传感器上的盖和在所述盖中和/或盖上的多个互连件，其电耦合到所述管芯的相应接合焊盘。互连件为模具的焊盘提供外部电触头。互连可以延伸穿过盖或沿着盖的表面。

55. 发明申请

US20060192230A1 Image sensor packages and frame structure thereof 有权
标题翻译：图像传感器封装及其框架结构
公开(公告)号：US20060192230A1
公开(公告)日：2006-08-31
申请号：US11411265
申请日：2006-04-26
申请人： Alan Wood , Kyle Kirby , Warren Farnworth , Salman Akram
发明人： Alan Wood , Kyle Kirby , Warren Farnworth , Salman Akram
IPC分类号： H01L27/148 , H01L31/0203
CPC分类号： H01L27/14618 , B33Y80/00 , H01L27/14625 , H01L2224/48091 , H01L2924/00014
摘要： A semiconductor package such as an image sensor package. A frame structure includes an array of frames, each having an aperture therethrough, into which an image sensor die in combination with a cover glass, filter, lens or other components may be installed in precise mutual alignment. Singulated image sensor dice and other components may be picked and placed into each frame of the frame structure. Alternatively, the frame structure may be configured to be aligned with and joined to a wafer bearing a plurality of image sensor dice, wherein optional, downwardly protruding skirts along peripheries of the frames may be received into kerfs cut along streets between die locations on the wafer, followed by installation of other package components. In either instance, the frame structure in combination with singulated image sensor dice or a joined wafer is singulated into individual image sensor packages. Various external connection approaches may be used.
摘要翻译：诸如图像传感器封装的半导体封装。框架结构包括每个具有穿过其中的孔的框架阵列，图像传感器与盖玻片，过滤器，透镜或其它部件组合的模具可以精确相互对准地安装在该框架中。单片图像传感器骰子和其他组件可以被拾取并放置在框架结构的每个帧中。或者，框架结构可以被配置为与承载多个图像传感器骰子的晶片对准并且连接到其上，其中沿着框架的周边的任选的向下突出的裙边可以被接收到沿着晶片上的模具位置之间沿着街道切割的切口，然后安装其他包装组件。在任一情况下，将帧结构与单独的图像传感器芯片或连接的晶片组合成单独的图像传感器封装。可以使用各种外部连接方法。

56. 发明授权

US07093358B2 Method for fabricating an interposer 有权
标题翻译：中介层的制造方法
公开(公告)号：US07093358B2
公开(公告)日：2006-08-22
申请号：US10648163
申请日：2003-08-26
申请人： Salman Akram , Alan G. Wood , Warren M. Farnworth
发明人： Salman Akram , Alan G. Wood , Warren M. Farnworth
IPC分类号： H01R43/16
CPC分类号： H05K7/1061 , B33Y10/00 , B33Y30/00 , B33Y80/00 , G01R1/0408 , G01R1/0433 , G01R1/0466 , G01R1/0483 , G01R1/07378 , G01R3/00 , H01L23/32 , H01L23/49827 , H01L2224/16111 , H01L2224/16237 , H01L2224/8114 , H01L2224/81385 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01049 , H01L2924/01082 , H01L2924/12042 , H01L2924/12044 , H01L2924/15787 , H01L2924/351 , H05K1/112 , H05K1/141 , H05K3/3436 , H05K2201/049 , H05K2201/09472 , H05K2201/10378 , H05K2201/10734 , H05K2201/2018 , H05K2203/167 , Y10T29/49126 , Y10T29/4913 , Y10T29/49144 , Y10T29/49147 , Y10T29/49156 , Y10T29/49165 , Y10T29/49204 , Y10T29/49218 , Y10T29/49222 , H01L2924/00
摘要： An interposer including a fence that receives and aligns a semiconductor device, such as a flip-chip type semiconductor device, with an interposer substrate. The fence may include edges that are configured to progressively align a semiconductor device with the interposer substrate. The fence may also include one or more laterally recessed regions to facilitate rough alignment of a semiconductor device with the interposer substrate. Methods for fabricating the fence include the use of stereolithographic and molding processes. When stereolithography is used to fabricate the fence, a machine vision system that includes at least one camera operably associated with a computer may be used to control a stereolithography apparatus and facilitates recognition of the position and orientation of interposer substrates on and around which material is to be applied in one or more layers to form the fence. As a result, the interposer substrates need not be precisely mechanically aligned.
摘要翻译：一种插入器，其包括接纳半导体器件（例如倒装芯片型半导体器件）与栅介质基板的栅栏。栅栏可以包括被配置为使半导体器件与插入器衬底逐渐对准的边缘。挡板还可以包括一个或多个侧向凹入区域，以便于半导体器件与插入器基板的粗略对准。围栏的制造方法包括使用立体光刻和成型工艺。当使用立体光刻制造栅栏时，可以使用包括与计算机可操作地相关联的至少一个照相机的机器视觉系统来控制立体光刻设备并且有助于识别材料在其上和周围的插入物基板的位置和取向应用于一层或多层以形成栅栏。结果，内插器基板不需要精确地机械对准。

57. 发明申请

US20060181294A1 System for testing semiconductor components having interconnect with variable flexure contacts 有权
标题翻译：用于测试具有与可变挠曲触点互连的半导体部件的系统
公开(公告)号：US20060181294A1
公开(公告)日：2006-08-17
申请号：US11389794
申请日：2006-03-27
申请人： Salman Akram , Alan Wood
发明人： Salman Akram , Alan Wood
IPC分类号： G01R31/02
CPC分类号： G01R1/0735 , G01R1/0425 , G01R1/0483 , G01R1/07342 , G01R3/00 , H01L2224/05568 , H01L2224/05573 , H01L2224/1601 , H01L2224/16237 , H01L2224/81191 , H01L2224/81193 , H01L2224/81899 , H01L2924/00014 , H05K3/326 , H01L2224/05599
摘要： A test system for testing semiconductor components includes an interconnect having a substrate and contacts on the substrate for electrically engaging terminal contacts on the components. The interconnect also includes one or more cavities in the substrate which form flexible segments proximate to the interconnect contacts. The flexible segments permit the interconnect contacts to move independently in the z-direction to accommodate variations in the height and planarity of the terminal contacts. In addition, the cavities can be pressurized, or alternately filled with a polymer material, to adjust a compliancy of the flexible segments. Different embodiments of the interconnect contacts include: metallized recesses for retaining the terminal contacts, metallized projections for penetrating the terminal contacts, metallized recesses with penetrating projections, and leads contained on a polymer tape and cantilevered over metallized recesses. The test system can be configured for testing wafer sized components, such as wafers and boards, or for testing die sized components, such as unpackaged dice and chip scale packages.
摘要翻译：用于测试半导体部件的测试系统包括具有基板和在基板上的触点的互连，用于电连接部件上的端子触点。互连还包括在基板中形成靠近互连触点的柔性段的一个或多个空腔。柔性部分允许互连触头在z方向上独立地移动以适应端子触头的高度和平面度的变化。此外，空腔可以被加压，或交替地填充聚合物材料，以调节柔性段的符合性。互连触点的不同实施例包括：用于保持端子触头的金属化凹槽，用于穿透端子触头的金属化突起，具有穿透突起的金属化凹槽以及包含在聚合物带上的引线，并悬挂在金属化凹槽上。测试系统可以配置用于测试晶片尺寸的组件，如晶圆和电路板，或用于测试裸片大小的组件，如未封装的芯片和芯片级封装。

58. 发明授权

US07090750B2 Plating 失效
标题翻译：电镀
公开(公告)号：US07090750B2
公开(公告)日：2006-08-15
申请号：US10228505
申请日：2002-08-26
申请人： Salman Akram , David R. Hembree
发明人： Salman Akram , David R. Hembree
IPC分类号： C25D17/00
CPC分类号： H01L21/67086 , C25D5/08 , C25D17/001 , C25F7/00 , H01L21/67051 , H01L21/67057 , H01L21/6708
摘要： An apparatus and method for treating a substrate to deposit, clean or etch material on a substrate using a first horizontal chuck to which a plurality of substrates is attached and electrically charged. Spaced closely to the first horizontal chuck is a coextensive horizontal second chuck which receives and showers reaction solution over all portions of each substrate. During the reaction process, both chucks are substantially submerged in reaction solution within a tank. At least one of the chucks is attached and controllable from a control arm. At least one of the chucks is rotated about a vertical axis at a slow speed during the reaction process. The axes of rotation of the two chucks may be coincident, or the axes may be offset from each other, and/or one or both axes may be offset from the chuck centerpoint(s). One of the chucks may also be periodically moved in a vertical direction relative to the other chuck.
摘要翻译：一种用于使用第一水平卡盘处理衬底以沉积，清洁或蚀刻衬底上的材料的装置和方法，多个衬底附着并带电的第一水平卡盘。与第一个水平卡盘密切相邻的是一个共同延伸的水平第二卡盘，它在每个基板的所有部分上接收和反射反应溶液。在反应过程中，两个卡盘基本上浸没在罐内的反应溶液中。至少一个卡盘从控制臂附接和控制。在反应过程中，至少一个卡盘以垂直轴线以慢速旋转。两个卡盘的旋转轴线可以重合，或者轴线可能彼此偏移，和/或一个或两个轴线可能偏离卡盘中心点。其中一个卡盘也可以相对于另一个卡盘在垂直方向周期性地移动。

59. 发明授权

US07043831B1 Method for fabricating a test interconnect for bumped semiconductor components by forming recesses and cantilevered leads on a substrate 失效
标题翻译：通过在基板上形成凹陷和悬臂引线来制造用于凸起的半导体部件的测试互连的方法
公开(公告)号：US07043831B1
公开(公告)日：2006-05-16
申请号：US09844532
申请日：2001-04-30
申请人： Warren M. Farnworth , Salman Akram
发明人： Warren M. Farnworth , Salman Akram
IPC分类号： H01K3/10
CPC分类号： H05K3/326 , G01R1/0466 , G01R31/2853 , H05K1/118 , H05K3/4092 , H05K2201/0373 , H05K2201/0397 , H05K2201/09036 , H05K2201/09081 , H05K2201/10734 , Y10T29/49117 , Y10T29/49121 , Y10T29/4913 , Y10T29/49139 , Y10T29/4914 , Y10T29/49155 , Y10T29/49165
摘要： A method for fabricating an interconnect for semiconductor components includes the steps of: providing a substrate; forming a metal layer on the substrate; etching projections in the metal layer; etching the metal layer to form patterns of leads; etching recesses in the substrate to cantilever the leads and form contacts for electrically engaging bumped contacts on a component; and then forming conductors to the leads. With the substrate comprising silicon, insulating layers can also be formed on the substrate, and within the recesses, for electrically insulating the leads and the conductors. With the conductors formed on a same surface of the substrate as the contacts, the same etching process can be used to form the conductors and the leads.
摘要翻译：一种用于半导体器件的互连的制造方法包括以下步骤：提供衬底; 在基板上形成金属层; 在金属层中蚀刻突起; 蚀刻金属层以形成引线图案; 蚀刻基板中的凹槽以悬臂引线并形成用于电连接部件上的凸起触点的触点; 然后在引线上形成导体。对于包含硅的衬底，绝缘层也可以形成在衬底上，并且在凹部内形成，用于使引线和导体电绝缘。由于导体形成在与触点相同的基板表面上，所以可以使用相同的蚀刻工艺来形成导体和引线。

60. 发明申请

US20060094160A1 Die stacking scheme 有权
公开(公告)号：US20060094160A1
公开(公告)日：2006-05-04
申请号：US11299225
申请日：2005-12-09
申请人： Salman Akram
发明人： Salman Akram
IPC分类号： H01L21/50 , H01L21/48 , H01L21/44
CPC分类号： H01L25/0657 , H01L2224/0554 , H01L2224/05568 , H01L2224/05573 , H01L2224/16145 , H01L2224/32145 , H01L2224/48145 , H01L2225/06506 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06527 , H01L2924/00014 , H01L2924/14 , H01L2924/15311 , H01L2924/19041 , H01L2224/05599 , H01L2924/00012 , H01L2224/0555 , H01L2224/0556
摘要： An improved semiconductor die stacking scheme is provided. In accordance with one embodiment of the present invention, a method of stacking a plurality of semiconductor die is provided. In accordance with another embodiment of the present invention a multiple die semiconductor assembly is provided. Each embodiment relates generally to a stacked semiconductor die assembly including a substrate, first and second semiconductor dice including stacking surfaces and active surfaces, a decoupling capacitor, and one or more conductive lines connecting elements of the assembly.

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