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51. 发明申请

US20070035560A1 Apparatus for providing multiple screens and method of dynamically configuring multiple screens 审中-公开
标题翻译：用于提供多个屏幕的设备和动态地配置多个屏幕的方法
公开(公告)号：US20070035560A1
公开(公告)日：2007-02-15
申请号：US11496544
申请日：2006-08-01
申请人： Jong-ho Lee , Kwang-kee Lee , Un-gyo Jung , Glenn Adams
发明人： Jong-ho Lee , Kwang-kee Lee , Un-gyo Jung , Glenn Adams
IPC分类号： G09G5/00
CPC分类号： G09G5/14 , G09G2340/0407 , G09G2340/0464 , G09G2340/10 , G09G2340/12 , G09G2340/125 , H04N5/445 , H04N5/44591 , H04N5/45 , H04N21/4312 , H04N21/4314 , H04N21/4316 , H04N21/443 , H04N21/4622
摘要： An apparatus for providing multiple screens and a method of dynamically configuring multiple screens are provided. The apparatus for providing multiple screens includes a digital signal processing module which receives predetermined information and restores a service based on the predetermined information, a service processing module which displays one or more logical screens associated with the service, and an output module which arranges the logical screens provided by the service processing module at different locations on a display screen. The logical screens have attribute information indicating whether the logical screens are visible on the display screen.
摘要翻译：提供了一种用于提供多个屏幕的装置和一种动态配置多个屏幕的方法。用于提供多个屏幕的装置包括数字信号处理模块，其接收预定信息并基于预定信息恢复服务;服务处理模块，其显示与服务相关联的一个或多个逻辑屏幕;以及输出模块，其布置逻辑由服务处理模块在显示屏幕上的不同位置提供的屏幕。逻辑屏幕具有指示逻辑屏幕是否在显示屏幕上可见的属性信息。

52. 发明申请

US20070030389A1 Apparatus for providing multiple screens and method of dynamically configuring multiple screens 有权
标题翻译：用于提供多个屏幕的设备和动态地配置多个屏幕的方法
公开(公告)号：US20070030389A1
公开(公告)日：2007-02-08
申请号：US11496403
申请日：2006-08-01
申请人： Jong-ho Lee , Kwang-kee Lee , Un-gyo Jung , Glenn Adams
发明人： Jong-ho Lee , Kwang-kee Lee , Un-gyo Jung , Glenn Adams
IPC分类号： H04N5/445
CPC分类号： G09G5/14 , G09G2340/0407 , G09G2340/0464 , G09G2340/10 , G09G2340/12 , G09G2340/125 , H04N5/445 , H04N5/44591 , H04N5/45 , H04N21/4312 , H04N21/4314 , H04N21/4316 , H04N21/443 , H04N21/4622
摘要： An apparatus for providing multiple screens and a method of dynamically configuring the multiple screens are provided. The apparatus for providing multiple screens uses flags included transferred packets in order to dynamically configure multiple screens that provide a plurality of contents on a physical display device and a method of dynamically configuring multiple screens. The apparatus for providing multiple screens includes a digital signal processing module which determines whether an application included in data information can be executed on a screen on the basis of received data information, and an operational module which operates the application on the screen on the basis of the determination result.
摘要翻译：提供了一种用于提供多个屏幕的设备和动态配置多个屏幕的方法。用于提供多个屏幕的装置使用包括传送分组的标志，以动态地配置在物理显示设备上提供多个内容的多个屏幕以及动态配置多个屏幕的方法。用于提供多个屏幕的设备包括数字信号处理模块，其确定包括在数据信息中的应用是否可以基于接收到的数据信息在屏幕上执行;以及操作模块，其基于在屏幕上操作该应用确定结果。

53. 发明申请

US20060175289A1 Method of fabricating semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20060175289A1
公开(公告)日：2006-08-10
申请号：US11338633
申请日：2006-01-25
申请人： Hyung-suk Jung , Jong-ho Lee , Jae-eon Park , Sung-kee Han , Min-joo Kim
发明人： Hyung-suk Jung , Jong-ho Lee , Jae-eon Park , Sung-kee Han , Min-joo Kim
IPC分类号： C03C15/00 , H01L21/302 , B44C1/22 , C23F1/00
CPC分类号： H01L29/517 , H01L21/02172 , H01L21/265 , H01L21/28194 , H01L21/31691 , H01L21/32134 , H01L21/32135
摘要： A method of fabricating a semiconductor device including a high-k dielectric for as a gate insulating layer is provided. The method includes forming a high-k dielectric layer and a conductive layer on a substrate, dry etching a portion of the conductive layer, performing a process to increase a wet etch rate of a remaining portion of the conductive layer, and forming a conductive layer pattern by wet etching the remaining portion of the conductive layer after performing the plasma process or the ion implantation. The process to increase the wet etch rate of the conductive layer including a plasma process and/or an ion implantation on the remaining portion of the conductive layer.
摘要翻译：提供一种制造包括用作栅极绝缘层的高k电介质的半导体器件的方法。该方法包括在衬底上形成高k电介质层和导电层，干蚀刻导电层的一部分，执行增加导电层剩余部分的湿蚀刻速率的工艺，以及形成导电层在执行等离子体处理或离子注入之后湿式蚀刻导电层的剩余部分的图案。包括在导电层的剩余部分上包括等离子体工艺和/或离子注入的导电层的湿蚀刻速率的方法。

54. 发明授权

US07037863B2 Post thermal treatment methods of forming high dielectric layers over interfacial layers in integrated circuit devices 有权
公开(公告)号：US07037863B2
公开(公告)日：2006-05-02
申请号：US10659945
申请日：2003-09-10
申请人： Seok-Joo Doh , Hyung-suk Jung , Nae-in Lee , Jong-ho Lee , Yun-seok Kim
发明人： Seok-Joo Doh , Hyung-suk Jung , Nae-in Lee , Jong-ho Lee , Yun-seok Kim
IPC分类号： H01L21/00
CPC分类号： H01L21/02329 , H01L21/02178 , H01L21/02181 , H01L21/02189 , H01L21/02192 , H01L21/022 , H01L21/02323 , H01L21/02337 , H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/28211 , H01L21/3143 , H01L21/31616 , H01L21/31641 , H01L21/31645 , H01L21/31662 , H01L28/56 , H01L29/513 , H01L29/517 , H01L29/518
摘要： High dielectric layers formed from layers of hafnium oxide, zirconium oxide, aluminum oxide, yttrium oxide, and/or other metal oxides and silicates disposed on silicon substrates or ozone oxide layers over silicon substrates may be nitrided and post thermally treated by oxidation, annealing, or a combination of oxidation and annealing to form high dielectric layers having superior mobility and interfacial characteristics.

55. 发明申请

US20060081905A1 Dielectric multilayer of microelectronic device and method of fabricating the same 审中-公开
标题翻译：微电子器件的介质多层及其制造方法
公开(公告)号：US20060081905A1
公开(公告)日：2006-04-20
申请号：US11233335
申请日：2005-09-22
申请人： Seok-jun Won , Dae-jin Kwon , Jong-ho Lee
发明人： Seok-jun Won , Dae-jin Kwon , Jong-ho Lee
IPC分类号： H01L29/94
CPC分类号： H01L21/022 , H01L21/02194 , H01L21/0228 , H01L21/28194 , H01L21/3141 , H01L21/3142 , H01L21/31637 , H01L21/31641 , H01L21/31645 , H01L29/40114 , H01L29/517 , H01L29/78
摘要： A dielectric multilayer suitable for improving a performance of a microelectronic device and a method of fabricating the dielectric multilayer are provided. The dielectric multilayer of the microelectronic device comprises a composite layer which is formed of oxides of two or more different elements and in which a laminar structure is not formed, and a single layer which is formed on at least one surface of the composite layer and is formed of an oxide of a single element.
摘要翻译：提供一种适用于改善微电子器件的性能的电介质多层及其制造方法。微电子器件的电介质多层包括由两个或更多个不同元素的氧化物形成并且其中没有形成层状结构的复合层和形成在复合层的至少一个表面上的单层，并且是由单一元素的氧化物形成。

56. 发明授权

US06875678B2 Post thermal treatment methods of forming high dielectric layers in integrated circuit devices 有权
标题翻译：在集成电路器件中形成高介电层的后热处理方法
公开(公告)号：US06875678B2
公开(公告)日：2005-04-05
申请号：US10650415
申请日：2003-08-29
申请人： Hyung-suk Jung , Nae-in Lee , Jong-ho Lee , Yun-seok Kim
发明人： Hyung-suk Jung , Nae-in Lee , Jong-ho Lee , Yun-seok Kim
IPC分类号： H01L21/28 , H01L21/314 , H01L21/316 , H01L21/318 , H01L29/51 , H01L21/3205 , H01L21/4763
CPC分类号： H01L21/02329 , H01L21/02178 , H01L21/02181 , H01L21/02189 , H01L21/02192 , H01L21/022 , H01L21/02337 , H01L21/0234 , H01L21/28185 , H01L21/28202 , H01L21/3143 , H01L21/3144 , H01L21/31604 , H01L21/31641 , H01L21/31645 , H01L21/3185 , H01L29/513 , H01L29/517 , H01L29/518
摘要： High dielectric layers formed from layers of hafnium oxide, zirconium oxide, aluminum oxide, yttrium oxide, and/or other metal oxides and silicates disposed on silicon substrates may be nitrided and post thermally treated by oxidation, annealing, or a combination of oxidation and annealing to form high dielectric layers having superior mobility and interfacial characteristics.
摘要翻译：可以将设置在硅基板上的由氧化铪，氧化锆，氧化铝，氧化钇和/或其它金属氧化物和硅酸盐的层形成的高介电层氮化并通过氧化，退火或氧化和退火的组合进行后热处理以形成具有优异的迁移率和界面特性的高介电层。

57. 发明授权

US06680224B2 Methods of forming and operating field effect transistors having gate and sub-gate electrodes 有权
标题翻译：形成和操作具有栅极和子栅电极的场效应晶体管的方法
公开(公告)号：US06680224B2
公开(公告)日：2004-01-20
申请号：US10389846
申请日：2003-03-17
申请人： Hyung-cheol Shin , Jong-ho Lee , Sang-yeon Han
发明人： Hyung-cheol Shin , Jong-ho Lee , Sang-yeon Han
IPC分类号： H01L218234
CPC分类号： H01L29/66643 , H01L21/2807 , H01L21/28105 , H01L29/1083 , H01L29/4983 , H01L29/7831 , H01L29/7836
摘要： Field effect transistors include a semiconductor substrate having a channel region of first conductivity type therein extending adjacent a surface thereof. Source and drain regions of second conductivity type are also provided at opposite ends of the channel region. The source and drain regions extend in the semiconductor substrate and form P-N rectifying junctions with the channel region. A gate electrode extends on the channel region and comprises a first electrically conductive material having a first work function. A first sub-gate electrode extends on the channel region and comprises a second electrically conductive material having a second work function that is unequal to the first work function. The second electrically conductive material is preferably selected so that a difference between the second work function and a work function of the channel region is sufficient to form an inversion-layer in a portion of the channel region extending opposite the first sub-gate electrode when the first sub-gate electrode is at a zero potential bias relative to the channel region.
摘要翻译：场效应晶体管包括其中具有第一导电类型的沟道区的半导体衬底，其在其表面附近延伸。第二导电类型的源极和漏极区域也设置在沟道区域的相对端。源区和漏区在半导体衬底中延伸并与沟道区形成P-N整流结。栅电极在沟道区域上延伸并且包括具有第一功函数的第一导电材料。第一子栅极电极在沟道区域上延伸并且包括具有不等于第一功函数的第二功函数的第二导电材料。优选选择第二导电材料，使得第二功函数和沟道区的功函数之间的差足以在沟道区域的与第一子栅电极相对延伸的部分中形成反转层，当第第一子栅极电极相对于沟道区域处于零电位偏置。

58. 发明授权

US06352864B1 Single transistor cell, method for manufacturing the same, memory circuit composed of single transistors cells, and method for driving the same 有权
标题翻译：单晶体管单元，其制造方法，由单晶体管单元构成的存储电路及其驱动方法
公开(公告)号：US06352864B1
公开(公告)日：2002-03-05
申请号：US09624398
申请日：2000-07-24
申请人： Jong-ho Lee
发明人： Jong-ho Lee
IPC分类号： H01L2100
CPC分类号： H01L29/6684 , G11C11/22 , G11C11/223 , H01L21/28291 , H01L29/78391
摘要： A semiconductor memory device, a method for manufacturing the same, a memory circuit including the semiconductor memory device, and a method for driving the same, are provided. In detail, one transistor forms a memory cell, and a single transistor cell capable of arbitrarily accessing the memory cell, a method for manufacturing the same, a memory circuit, and a method for driving the memory circuit, are provided. An island type semiconductor layer as an active region is formed on a ferroelectric layer. A word line crosses the semiconductor layer. A source is formed on the semiconductor layer on one side of the word line, and a drain is formed on the other side. A plate line is formed below the ferroelectric layer to face the word line, and intersects the word line. A drive line is connected to the source, and a bit line is connected to the drain.
摘要翻译：提供半导体存储器件，其制造方法，包括半导体存储器件的存储器电路及其驱动方法。详细地说，提供了一个晶体管形成存储单元，以及能够任意访问存储单元的单个晶体管单元，其制造方法，存储器电路和用于驱动存储器电路的方法。在铁电层上形成作为有源区的岛状半导体层。字线穿过半导体层。源极形成在字线一侧的半导体层上，另一侧形成漏极。在铁电层下方形成面对字线的板线，并与字线相交。驱动线连接到源极，位线连接到漏极。

59. 发明授权

US06222756B1 Single transistor cell, method for manufacturing the same, memory circuit composed of single transistor cells, and method for driving the same 有权
公开(公告)号：US06222756B1
公开(公告)日：2001-04-24
申请号：US09221974
申请日：1998-12-29
申请人： Jong-ho Lee
发明人： Jong-ho Lee
IPC分类号： G11C1122
CPC分类号： H01L29/6684 , G11C11/22 , G11C11/223 , H01L21/28291 , H01L29/78391
摘要： A semiconductor memory device, a method for manufacturing the same, a memory circuit including the semiconductor memory device, and a method for driving the same, are provided. In detail, one transistor forms a memory cell, and a single transistor cell capable of arbitrarily accessing the memory cell, a method for manufacturing the same, a memory circuit, and a method for driving the memory circuit, are provided. An island type semiconductor layer as an active region is formed on a ferroelectric layer. A word line crosses the semiconductor layer. A source is formed on the semiconductor layer on one side of the word line, and a drain is formed on the other side. A plate line is formed below the ferroelectric layer to face the word line, and intersects the word line. A drive line is connected to the source, and a bit line is connected to the drain.

60. 发明授权

US6046927A Nonvolatile semiconductor memory device, a method of fabricating the same, and read, erase write methods of the same 有权
标题翻译：非易失性半导体存储器件，其制造方法以及其读取，擦除写入方法
公开(公告)号：US6046927A
公开(公告)日：2000-04-04
申请号：US177569
申请日：1998-10-23
申请人： Jong-ho Lee , In-Seon Park , Cha-Young Yoo
发明人： Jong-ho Lee , In-Seon Park , Cha-Young Yoo
IPC分类号： H01L27/108 , G11C11/22 , H01L21/8242 , H01L21/8246 , H01L27/105
CPC分类号： G11C11/22
摘要： A ferroelectric memory device includes a silicon-on-insulator substrate having a handling wafer, a first insulating layer, and a semiconductor layer. It also includes a first conductive layer used as a bit line formed in the first insulating layer, a source region formed in the semiconductor layer, a drain region formed in the semiconductor layer, a second insulating layer formed over the semiconductor layer between the source and drain regions, a second conductive layer for use as both a lower electrode and gate electrode, formed over the second insulating layer between the source and drain regions, a ferroelectric layer formed over the semiconductor layer, and a third conductive layer for use as an upper electrode formed over the ferroelectric layer. For reading, writing, and erasing, different voltages are applied to the upper electrode and the semiconductor layer between the drain and source. For writing, the upper electrode receives a writing voltage, and the semiconductor layer receives a ground voltage. This brings the drain and source to a floating state to either invert polarization of the ferroelectric layer or retain initial polarization, depending upon the data. For erasing, the upper electrode receives an erasing voltage, and the semiconductor layer receives a ground voltage. This brings the drain and source to a floating state. For reading, the upper electrode receives a reading voltage, and the semiconductor layer receives a ground voltage. A sensing current is then provided to the drain, and potential variation is sensed on the bit line.
摘要翻译：铁电存储器件包括具有处理晶片，第一绝缘层和半导体层的绝缘体上硅衬底。它还包括用作形成在第一绝缘层中的位线的第一导电层，形成在半导体层中的源极区，形成在半导体层中的漏极区，在半导体层之间形成的第二绝缘层，漏极区域，用作下电极和栅电极的第二导电层，形成在源区和漏区之间的第二绝缘层上，形成在半导体层上的铁电层，以及用作上层的第三导电层形成在铁电层上的电极。对于读取，写入和擦除，不同的电压施加到漏极和源极之间的上部电极和半导体层。对于写入，上部电极接收写入电压，并且半导体层接收地电压。这取决于数据，将漏极和源极引入浮置状态以反转铁电层的极化或保持初始极化。为了擦除，上部电极接收擦除电压，半导体层接收接地电压。这将使排水和源处于浮动状态。为了读取，上部电极接收读取电压，半导体层接收接地电压。然后将感测电流提供给漏极，并且在位线上感测到电位变化。

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