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51. 发明申请

US20080211106A1 VIA/CONTACT AND DAMASCENE STRUCTURES AND MANUFACTURING METHODS THEREOF 有权
标题翻译：威盛/联系人和丹麦结构及其制造方法
公开(公告)号：US20080211106A1
公开(公告)日：2008-09-04
申请号：US11680981
申请日：2007-03-01
申请人： Shih-Chieh Chang , Ying-Lang Wang , Kei-Wei Chen , Jung-Chih Tsao , Yu-Sheng Wang
发明人： Shih-Chieh Chang , Ying-Lang Wang , Kei-Wei Chen , Jung-Chih Tsao , Yu-Sheng Wang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76831 , H01L21/7684
摘要： A method for forming a semiconductor structure includes forming a dielectric layer over a substrate. A first non-conductive barrier layer is formed over the dielectric layer. At least one opening is formed through the first non-conductive barrier layer and within the dielectric layer. A second non-conductive barrier layer is formed over the first non-conductive barrier layer and within the opening. At least a portion of the second non-conductive barrier layer is removed, thereby at least partially exposing a top surface of the first non-conductive barrier layer and a bottom surface of the opening, with the second non-conductive barrier layer remaining on sidewalls of the opening. A seed layer and conductive layer is then formed and a single polishing operation removes the seed layer and conductive layer.
摘要翻译：形成半导体结构的方法包括在衬底上形成电介质层。在电介质层上形成第一非导电阻挡层。通过第一非导电阻挡层和介电层内形成至少一个开口。在第一非导电阻挡层上并在开口内形成第二非导电阻挡层。去除第二非导电阻挡层的至少一部分，从而至少部分地暴露第一非导电阻挡层的顶表面和开口的底表面，而第二非导电阻挡层保留在侧壁上的开幕。然后形成种子层和导电层，并且单次抛光操作去除种子层和导电层。

52. 发明授权

US07128821B2 Electropolishing method for removing particles from wafer surface 有权
标题翻译：从晶片表面去除颗粒的电抛光方法
公开(公告)号：US07128821B2
公开(公告)日：2006-10-31
申请号：US10761477
申请日：2004-01-20
申请人： Shih-Ho Lin , Chung-Chang Chen , Kei-Wei Chen , Shih-Tzung Chang , Chao-Lung Chen , Po-Jen Shih , Yu-Ku Lin , Ying-Lang Wang
发明人： Shih-Ho Lin , Chung-Chang Chen , Kei-Wei Chen , Shih-Tzung Chang , Chao-Lung Chen , Po-Jen Shih , Yu-Ku Lin , Ying-Lang Wang
IPC分类号： C25D5/34 , C25F1/00
CPC分类号： H01L21/76843 , B24B37/042 , B24B37/046 , C25D3/38 , C25D5/18 , C25D7/123 , C25F3/02 , H01L21/02068 , H01L21/32115 , H01L21/76865 , H01L21/76873
摘要： An electropolishing method for removing potential device-contaminating particles from a wafer, is disclosed. The method includes immersing the wafer in an electropolishing electrolyte solution and removing defects and particles from the wafer by rotational friction between the wafer and the electrolyte solution in combination with electrolysis. The method is effective in removing particles from via openings of all sizes, including via openings having a width smaller than about 0.2 μm.
摘要翻译：公开了一种用于从晶片去除潜在的器件污染颗粒的电抛光方法。该方法包括将晶片浸入电解抛光电解质溶液中，并通过晶片和电解质溶液之间的旋转摩擦与电解结合从晶片去除缺陷和颗粒。该方法有效地从各种尺寸的通孔开口去除颗粒，包括宽度小于约0.2μm的通孔。

53. 发明申请

US20060055928A1 Test device and method for laser alignment calibration 有权
标题翻译：用于激光对准校准的测试装置和方法
公开(公告)号：US20060055928A1
公开(公告)日：2006-03-16
申请号：US10942554
申请日：2004-09-15
申请人： Shih-Tzung Chang , Yu-Ku Lin , Shih-Ho Lin , Kei-Wei Chen , Ting-Chun Wang , Ching-Hwan Su , Ying-Lang Wang
发明人： Shih-Tzung Chang , Yu-Ku Lin , Shih-Ho Lin , Kei-Wei Chen , Ting-Chun Wang , Ching-Hwan Su , Ying-Lang Wang
IPC分类号： G01B11/00
CPC分类号： H01L22/34 , G01B21/042
摘要： A novel test device and method for calibrating the alignment of a laser beam emitted from a laser metrology tool with respect to a target area on a substrate. The test device includes a laser-sensitive material having a calibration pattern that includes a target point. When the tool is properly adjusted, the laser beam strikes the target point and is released to production. If the laser beam misses the target point, the tool is re-adjusted and re-tested until the laser beam strikes the target point.
摘要翻译：一种用于校准从激光计量工具发射的激光束相对于衬底上的目标区域的对准的新型测试装置和方法。测试装置包括具有包括目标点的校准图案的激光敏感材料。当工具被正确调整时，激光束撞击目标点并释放到生产中。如果激光束错过目标点，则重新调整工具并重新测试直到激光束撞击目标点。

54. 发明申请

US20050236181A1 Novel ECP method for preventing the formation of voids and contamination in vias 审中-公开
标题翻译：用于防止通孔中形成空隙和污染的新型ECP方法
公开(公告)号：US20050236181A1
公开(公告)日：2005-10-27
申请号：US10917543
申请日：2004-08-12
申请人： Kei-Wei Chen , Shih-Ho Lin , Chun-Chang Chen , Ching-Hwan Su , Yu-Ku Lin , Ying-Lang Wang , De-Dui Liao , Meng-Chao Tzeng
发明人： Kei-Wei Chen , Shih-Ho Lin , Chun-Chang Chen , Ching-Hwan Su , Yu-Ku Lin , Ying-Lang Wang , De-Dui Liao , Meng-Chao Tzeng
IPC分类号： H01L21/768 , H01L23/522 , H05K1/03 , H05K1/09 , H05K1/11
CPC分类号： H01L21/76816 , H01L21/76807 , H01L23/5226 , H01L2924/0002 , Y10T29/49165 , H01L2924/00
摘要： A method for preventing the formation of voids and contaminants in vias during the fabrication of a metal interconnect structure such as a dual damascene structure is disclosed. The method includes providing a substrate; providing a dielectric layer having trench openings and via openings on the substrate, wherein the ratio of the sum of the areas of the trench openings to the sum of the areas of the via openings is between 1 and 300; wherein the via opening bottom has a width of less than about 25 μm; and electroplating a metal in the trench openings and via openings. An interconnect structure having at least one void-free via is further disclosed.
摘要翻译：公开了一种用于在金属互连结构例如双镶嵌结构的制造期间防止在通孔中形成空隙和污染物的方法。该方法包括提供基板; 在衬底上提供具有沟槽开口和通孔开口的电介质层，其中沟槽开口的面积之和与通路孔的面积之和的比值在1和300之间; 其中所述通孔开口底部具有小于约25μm的宽度; 以及在沟槽开口和通孔中电镀金属。还公开了具有至少一个无空隙通孔的互连结构。

55. 发明申请

US20100230815A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20100230815A1
公开(公告)日：2010-09-16
申请号：US12785618
申请日：2010-05-24
申请人： Jung-Chih Tsao , Kei-Wei Chen , Yu-Ku Lin
发明人： Jung-Chih Tsao , Kei-Wei Chen , Yu-Ku Lin
IPC分类号： H01L23/522 , H01L23/48
CPC分类号： H01L23/5226 , H01L21/76805 , H01L21/76807 , H01L21/76832 , H01L21/76844 , H01L21/76846 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： Semiconductor devices and methods for fabricating the same. An exemplary device includes a substrate, a dielectric layer, a protection layer, and a conformal barrier layer. The dielectric layer overlies the substrate and comprises an opening. The opening comprises a lower portion and a wider upper portion, exposing parts of the substrate. The bottoms of the upper portion act as shoulders of the opening. The protection layer overlies at least one shoulder of the opening. The conformal barrier layer is disposed in the opening and overlies the protection layer and the dielectric layer, wherein etching resistance of the protection layer against inert-gas plasma is higher than that of the barrier layer.
摘要翻译：半导体器件及其制造方法。示例性器件包括衬底，电介质层，保护层和共形阻挡层。电介质层覆盖在衬底上并且包括开口。开口包括下部和较宽的上部，暴露基底的部分。上部的底部作为开口的肩部。保护层覆盖开口的至少一个肩部。共形阻挡层设置在开口中并覆盖保护层和电介质层，其中保护层对惰性气体等离子体的耐蚀性高于阻挡层的抗蚀性。

56. 发明授权

US07417321B2 Via structure and process for forming the same 有权
标题翻译：通过结构及其形成方法
公开(公告)号：US07417321B2
公开(公告)日：2008-08-26
申请号：US11323484
申请日：2005-12-30
申请人： Jung-Chih Tsao , Kei-Wei Chen , Ying-Jing Lu , Yu-Sheng Wang , Yu-Ku Lin
发明人： Jung-Chih Tsao , Kei-Wei Chen , Ying-Jing Lu , Yu-Sheng Wang , Yu-Ku Lin
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76844 , H01L21/76805 , H01L21/76846 , H01L21/76865 , H01L23/5226 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： Via structure and process flow for interconnection in a semiconductor product. A bottom metal layer is provided to represent a connection layer in the semiconductor product. An isolation layer on the bottom metal layer comprises a via hole exposing a portion of the bottom metal layer. The via hole comprises a sidewall and a bottom. A first barrier metal layer is disposed on the sidewall of the via hole, but not on the bottom of the via hole. A metal under-layer is formed on the bottom of the via hole and on the first barrier metal layer. A second barrier metal layer is formed on the metal under-layer. A metal fill layer fills the via hole. A lattice mismatch between the metal under-layer and the second barrier metal layer is less than about 5%.
摘要翻译：通过半导体产品互连的结构和工艺流程。提供底部金属层以表示半导体产品中的连接层。底部金属层上的隔离层包括露出底部金属层的一部分的通孔。通孔包括侧壁和底部。第一阻挡金属层设置在通孔的侧壁上，但不设置在通孔的底部。在通孔的底部和第一阻挡金属层上形成金属底层。在金属底层上形成第二阻挡金属层。金属填充层填充通孔。金属底层和第二阻挡金属层之间的晶格失配小于约5％。

57. 发明授权

US07208404B2 Method to reduce Rs pattern dependence effect 有权
标题翻译：减少Rs模式依赖效应的方法
公开(公告)号：US07208404B2
公开(公告)日：2007-04-24
申请号：US10687183
申请日：2003-10-16
申请人： Jung-Chih Tsao , Chi-Wen Li , Kei-Wei Chen , Jye-Wei Hsu , Hsien-Pin Fong , Steven Lin , Ray Chuang
发明人： Jung-Chih Tsao , Chi-Wen Li , Kei-Wei Chen , Jye-Wei Hsu , Hsien-Pin Fong , Steven Lin , Ray Chuang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76877 , H01L21/288 , H01L21/7684
摘要： A method of forming a copper interconnect in an opening within a pattern is described. The copper interconnect has an Rs that is nearly independent of opening width and pattern density. A first copper layer having a concave upper surface and thickness t1 is formed in a via or trench in a dielectric layer by depositing copper and performing a first CMP step. A second copper layer with a thickness t2 where t2≦t1 and having a convex lower surface is deposited on the first copper layer by a selective electroplating method. The first and second copper layers are annealed and then a second CMP step planarizes the second copper layer to become coplanar with the dielectric layer. The invention is also a copper interconnect comprised of the aforementioned copper layers where the first copper layer has a grain density (GD1)≧GD2 for the second copper layer.
摘要翻译：描述了在图案内的开口中形成铜互连的方法。铜互连具有几乎独立于开口宽度和图案密度的Rs。通过沉积铜并执行第一CMP步骤，在电介质层中的通孔或沟槽中形成具有凹上表面和厚度t 1的第一铜层。具有厚度为2 的第二铜层，其中具有凸下表面的第二铜层沉积在第一铜层上通过选择性电镀方法。对第一和第二铜层进行退火，然后第二CMP步骤将第二铜层平坦化成与电介质层共面。本发明也是由上述铜层构成的铜布线，其中第一铜层具有第二铜层的晶粒密度（G SUB D1）= G D2 D2。

58. 发明授权

US09673244B2 Image sensor isolation region and method of forming the same 有权
公开(公告)号：US09673244B2
公开(公告)日：2017-06-06
申请号：US13415546
申请日：2012-03-08
申请人： Shiu-Ko JangJian , Min Hao Hong , Kei-Wei Chen , Szu-An Wu
发明人： Shiu-Ko JangJian , Min Hao Hong , Kei-Wei Chen , Szu-An Wu
IPC分类号： H01L31/109 , H01L27/146
CPC分类号： H01L27/1463 , H01L27/1464
摘要： Image sensors comprising an isolation region according to embodiments are disclosed, as well as methods of forming the image sensors with isolation region. An embodiment is a structure comprising a semiconductor substrate, a photo element in the semiconductor substrate, and an isolation region in the semiconductor substrate. The isolation region is proximate the photo element and comprises a dielectric material and an epitaxial region. The epitaxial region is disposed between the semiconductor substrate and the dielectric material.

59. 发明申请

US20050118808A1 Method of reducing the pattern effect in the CMP process 有权
标题翻译：降低CMP工艺中图案效果的方法
公开(公告)号：US20050118808A1
公开(公告)日：2005-06-02
申请号：US10724201
申请日：2003-12-01
申请人： Chi-Wen Liu , Jung-Chih Tsao , Shien-Ping Feng , Kei-Wei Chen , Shih-Chi Lin , Ray Chuang
发明人： Chi-Wen Liu , Jung-Chih Tsao , Shien-Ping Feng , Kei-Wei Chen , Shih-Chi Lin , Ray Chuang
IPC分类号： H01L21/302 , H01L21/321 , H01L21/44 , H01L21/4763 , H01L21/768
CPC分类号： H01L21/3212 , H01L21/7684
摘要： A method of reducing the pattern effect in the CMP process. The method comprises the steps of providing a semiconductor substrate having a patterned dielectric layer, a barrier layer on the patterned dielectric layer, and a conductive layer on the barrier layer; performing a first CMP process to remove part of the conductive layer before the barrier layer is polished, thereby a step height of the conductive layer is reduced; depositing a layer of material substantially the same as the conductive layer on the conductive layer; and performing a second CMP process to expose the dielectric layer. A method of eliminating the dishing phenomena after a CMP process and a CMP rework method are also provided.
摘要翻译：降低CMP工艺中图案效果的方法。该方法包括以下步骤：提供具有图案化介电层的半导体衬底，图案化电介质层上的阻挡层和阻挡层上的导电层; 在阻挡层被抛光之前执行第一CMP工艺以去除导电层的一部分，从而降低导电层的台阶高度; 在导电层上沉积与导电层基本相同的材料层; 以及执行第二CMP工艺以暴露所述电介质层。还提供了在CMP处理和CMP返工方法之后消除凹陷现象的方法。

60. 发明申请

US20130320478A1 System and Method for Processing a Backside Illuminated Photodiode 有权
标题翻译：用于处理背面照明光电二极管的系统和方法
公开(公告)号：US20130320478A1
公开(公告)日：2013-12-05
申请号：US13486833
申请日：2012-06-01
申请人： Shiu-Ko JangJian , Kei-Wei Chen , Chi-Cherng Jeng , Min Hao Hong
发明人： Shiu-Ko JangJian , Kei-Wei Chen , Chi-Cherng Jeng , Min Hao Hong
IPC分类号： H01L31/103 , H01L29/36 , H01L31/18
CPC分类号： H01L31/103 , H01L29/36 , H01L31/1037 , H01L31/18 , H01L31/1812 , Y02E10/50
摘要： System and method for processing a semiconductor device surface to reduce dark current and white pixel anomalies. An embodiment comprises a method applied to a semiconductor or photodiode device surface adjacent to a photosensitive region, and opposite a side having circuit structures for the device. A doped layer may optionally be created at a depth of less than about 10 nanometers below the surface of the substrate and may be doped with a boron concentration between about 1E13 and 1E16. An oxide may be created on the substrate using a temperature sufficient to reduce the surface roughness below a predetermined roughness threshold, and optionally at a temperature between about 300° C. and 500° C. and a thickness between about 1 nanometer and about 10 nanometers. A dielectric may then be created on the oxide, the dielectric having a refractive index greater than a predetermined refractive threshold, optionally at least about 2.0.
摘要翻译：用于处理半导体器件表面以减少暗电流和白色像素异常的系统和方法。一个实施例包括应用于与光敏区域相邻的半导体或光电二极管器件表面的方法，以及与该器件的电路结构相反的一侧。掺杂层可以任选地在衬底表面下方小于约10纳米的深度处产生，并且可以掺杂在约1E13和1E16之间的硼浓度。可以使用足以将表面粗糙度降低到预定粗糙度阈值以下且可选地在约300℃至500℃之间的温度和约1纳米至约10纳米的厚度的温度在基底上产生氧化物。然后可以在氧化物上产生电介质，电介质具有大于预定折射阈值的折射率，任选至少约2.0。

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