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51. 发明申请

US20070105509A1 RF transmission leakage mitigator, method of mitigating an RF transmission leakage and CDMA tranceiver employing the same 有权
标题翻译： RF传输泄漏减轻器，减轻RF传输泄漏的方法以及采用其的CDMA接收机
公开(公告)号：US20070105509A1
公开(公告)日：2007-05-10
申请号：US11270121
申请日：2005-11-09
申请人： Khurram Muhammad , Dirk Leipold
发明人： Khurram Muhammad , Dirk Leipold
IPC分类号： H03C1/52 , H04B1/68
CPC分类号： H03C5/00 , H04B1/525 , H04B1/707
摘要： The present invention provides an RF transmission leakage mitigator for use with a full-duplex, wireless transceiver. In one embodiment, the RF transmission leakage mitigator includes an inversion generator configured to provide an RF transmission inversion signal of an interfering transceiver RF transmission to a receiving portion of the transceiver thereby creating a residual leakage signal. Additionally, the RF transmission leakage mitigator also includes a residual processor coupled to the inversion generator and configured to adjust the RF transmission inversion signal of the interfering transceiver RF transmission based on reducing the residual leakage signal to a specified level.
摘要翻译：本发明提供了一种与全双工无线收发器一起使用的RF传输泄漏缓解器。在一个实施例中，RF传输泄漏减轻器包括反相发生器，其被配置为将干扰收发器RF传输的RF发射反转信号提供给收发器的接收部分，从而产生残余泄漏信号。此外，RF传输泄漏缓解器还包括耦合到反向发生器并被配置为基于将剩余泄漏信号减小到指定电平来调整干扰收发器RF传输的RF发射反转信号的残余处理器。

52. 发明申请

US20050104654A1 Technique for improving antialiasing and adjacent channel interference filtering using cascaded passive IIR filter stages combined with direct sampling and mixing 有权
标题翻译：使用级联无源IIR滤波器级与直接采样和混合相结合的改进抗混叠和相邻信道干扰滤波的技术
公开(公告)号：US20050104654A1
公开(公告)日：2005-05-19
申请号：US10712593
申请日：2003-11-13
申请人： Khurram Muhammad , Robert Staszewski , Dirk Leipold
发明人： Khurram Muhammad , Robert Staszewski , Dirk Leipold
IPC分类号： H03B1/00 , H03H19/00 , H04B1/10
CPC分类号： H04B1/109 , H03H19/004
摘要： A technique of improving antialiasing and adjacent channel interference filtering uses cascaded passive IIR filter stages combined with direct sampling and mixing. The methodology and related architecture allows for increased passive IIR filtering without necessitating use of amplifier stages.
摘要翻译：改进抗混叠和相邻信道干扰滤波的技术使用级联无源IIR滤波器级与直接采样和混合相结合。该方法和相关架构允许增加无源IIR滤波，而不需要使用放大器级。

53. 发明授权

US08855236B2 Digital amplitude modulation 有权
标题翻译：数字幅度调制
公开(公告)号：US08855236B2
公开(公告)日：2014-10-07
申请号：US13237740
申请日：2011-09-20
申请人： Robert B. Staszewski , Sameh Rezeq , Dirk Leipold
发明人： Robert B. Staszewski , Sameh Rezeq , Dirk Leipold
IPC分类号： H03C1/52 , H04L27/36
CPC分类号： H04L27/361
摘要： A transmitter using quadrature modulation includes a rectangular to polar converter for converting data symbols into a polar form, where each polar symbol has a magnitude signal and an angle signal. Digital phase modulation circuitry includes an all digital PLL circuit for generating a phase modulated RF carrier signal responsive to the angle signal frequency control word (FCW) and a carrier frequency FCW. A digitally controlled amplifier for amplifying the phase modulated signal is controlled by a digital amplitude control circuitry for controlling the gain of the digitally controlled amplifier responsive to the magnitude signal.
摘要翻译：使用正交调制的发射机包括用于将数据符号转换成极性形式的矩形到极化转换器，其中每个极性符号具有幅度信号和角度信号。数字相位调制电路包括全数字PLL电路，用于响应角度信号频率控制字（FCW）和载波频率FCW产生相位调制的RF载波信号。用于放大相位调制信号的数字控制放大器由数字幅度控制电路控制，用于响应于幅度信号来控制数字控制放大器的增益。

54. 发明授权

US07555057B2 Predistortion calibration in a transceiver assembly 有权
标题翻译：收发器组件中的预失真校准
公开(公告)号：US07555057B2
公开(公告)日：2009-06-30
申请号：US10749654
申请日：2003-12-31
申请人： Robert B. Staszewski , Dirk Leipold
发明人： Robert B. Staszewski , Dirk Leipold
IPC分类号： H04K1/02 , H04L25/03 , H04L25/49
CPC分类号： H03F1/3282 , H03F1/0211 , H03F1/3247 , H03F2200/331
摘要： Systems and methods are provided for calibrating a digital predistorter in an integrated transceiver circuit. A digital transmitter path provides a signal from a digital input. The transmitter path includes a digital predistorter that predistorts the digital input to mitigate nonlinearities associated with a power amplifier. The integrated transceiver circuit further includes a receiver path associated with the digital transmitter path. A coupling element provides the signal from the transmitter path to the receiver path. A signal evaluator determines values for at least one parameter associated with the digital predistorter based on the signal.
摘要翻译：提供了用于校准集成收发器电路中的数字预失真器的系统和方法。数字发射器路径提供来自数字输入的信号。发射机路径包括数字预失真器，其预失真数字输入以减轻与功率放大器相关联的非线性。集成收发器电路还包括与数字发送器路径相关联的接收器路径。耦合元件提供从发射机路径到接收机路径的信号。信号评估器基于该信号确定与数字预失真器相关联的至少一个参数的值。

55. 发明授权

US07440511B2 Transmit filter 有权
标题翻译：发射滤波器
公开(公告)号：US07440511B2
公开(公告)日：2008-10-21
申请号：US10001448
申请日：2001-10-31
申请人： Robert B. Staszewski , Dirk Leipold
发明人： Robert B. Staszewski , Dirk Leipold
IPC分类号： H04L27/00
CPC分类号： H03H17/0283 , H04L7/0029
摘要： A transmit filter (100) receives a stream of data symbols (DT_TX) at a baseband symbol clock rate. An available clock (FREF) is used to generate sample points for producing a generating an oversampled signal. The available clock is independent from the baseband symbol clock, and does not need to be an integer multiple of the clock. Upon identifying a start sequence in the data stream, a phase tracking circuit (106) is used to determine a current position relative to the baseband symbol clock. A state circuit (104) stores the last three, or more, data symbols. Based on the last three data symbols (which determines the shape of the curve for the current data symbol) and the current position (which determines the current position on the curve), a filter circuit (108) generates a sample point.
摘要翻译：发射滤波器（100）以基带符号时钟速率接收数据符号流（DT_TX）。可用时钟（FREF）用于产生用于产生过采样信号的采样点。可用时钟独立于基带符号时钟，不需要是时钟的整数倍。在识别数据流中的起始序列时，使用相位跟踪电路（106）来确定相对于基带符号时钟的当前位置。状态电路（104）存储最后三个或更多数据符号。基于最后三个数据符号（其确定当前数据符号的曲线的形状）和当前位置（其确定曲线上的当前位置），滤波器电路（108）产生采样点。

56. 发明授权

US07183860B2 Gain calibration of a digital controlled oscillator 有权
标题翻译：增益数字控制振荡器的校准
公开(公告)号：US07183860B2
公开(公告)日：2007-02-27
申请号：US11149859
申请日：2005-06-10
申请人： Robert B. Staszewski , Gennady Feygin , Oren E. Eliezer , Dirk Leipold
发明人： Robert B. Staszewski , Gennady Feygin , Oren E. Eliezer , Dirk Leipold
IPC分类号： H03C3/06 , H03L7/091 , H03L7/099
CPC分类号： H03L7/0991 , H03L7/085 , H03L2207/50
摘要： A novel apparatus for and a method of estimating, calibrating and tracking in real-time the gain of a radio frequency (RF) digitally controlled oscillator (DCO) in an all-digital phase locked loop (ADPLL). Precise setting of the inverse DCO gain in the ADPLL modulating path allows direct wideband frequency modulation that is independent of the ADPLL loop bandwidth. The gain calibration technique is based on a steepest descent iterative algorithm wherein the phase ADPLL error is sampled and correlated with the modulating data to generate a gradient. The gradient is then scaled and added to the current value of the DCO gain multiplier.
摘要翻译：一种用于实时估计，校准和跟踪全数字锁相环（ADPLL）中的射频（RF）数字控制振荡器（DCO）的增益的新型装置和方法。 ADPLL调制路径中逆DCO增益的精确设置允许直接宽带频率调制，与ADPLL环路带宽无关。增益校准技术基于最速下降迭代算法，其中相位ADPLL误差被采样并与调制数据相关以产生梯度。然后将梯度缩放并添加到DCO增益乘数的当前值。

57. 发明授权

US06809598B1 Hybrid of predictive and closed-loop phase-domain digital PLL architecture 有权
标题翻译：预测和闭环相域数字PLL架构的混合
公开(公告)号：US06809598B1
公开(公告)日：2004-10-26
申请号：US09695516
申请日：2000-10-24
申请人： Robert B. Staszewski , Dirk Leipold , Kenneth Maggio
发明人： Robert B. Staszewski , Dirk Leipold , Kenneth Maggio
IPC分类号： H03L706
CPC分类号： H04B1/7156 , H03C3/0925 , H03C3/0941 , H03C3/0966 , H03C3/0975 , H03L7/1806 , H03L2207/50 , H04B2001/71566 , H04L27/12
摘要： A phase-domain digital PLL loop is implemented using a hybrid of predictive and closed-loop architecture that allows direct DCO oscillator transmit modulation in the GFSK modulation scheme of “BLUETOOTH” or GSM, as well as the chip phase modulation of the 802.11b or Wideband-CDMA. The current gain of the DCO oscillator is predicted by observing past phase error responses to previous DCO corrections. DCO control is then augmented with the “open-loop” instantaneous frequency jump estimate of the new frequency control word.
摘要翻译：使用预测和闭环架构的混合来实现相域数字PLL环路，其允许在“蓝牙”或GSM的GFSK调制方案中直接DCO振荡器发送调制，以及802.11b的芯片相位调制或宽带CDMA。 DCO振荡器的当前增益是通过观察对先前DCO校正的过去相位误差响应来预测的。然后用新的频率控制字的“开环”瞬时频率跳跃估计来增加DCO控制。

58. 发明授权

US06593773B2 Power saving circuitry using predictive logic 有权
公开(公告)号：US06593773B2
公开(公告)日：2003-07-15
申请号：US09967275
申请日：2001-09-28
申请人： Robert B. Staszewski , Dirk Leipold
发明人： Robert B. Staszewski , Dirk Leipold
IPC分类号： H03D324
CPC分类号： H03L7/16 , H03K19/0016 , H03L7/085 , H03L7/087 , H03L7/091 , H03L7/093 , H03L7/099 , H03L2207/50 , H04L7/0029
摘要： To conserve power in a circuit where a high-speed signal HSIG controls combinational logic (10), while a low-speed signal LCLK drives a logic/memory circuit (12) that samples the output of the combinational logic, predictive logic state machine (14) generates a clock, P_LCLK, which has an active level preceding the active edge of LCLK by a period sufficient to allow the combinational logic to reach the desired state prior to the active edge of LCLK and, preferably, allows for possible jitter in LCLK. Responsive to P_LCLK, the signal suspend circuitry (16) either passes HSIG or gates off HSIG. Further reductions in power can be accomplished by predicting which portions of the logic/memory circuit (12) will be used, and clocking those portions.

59. 发明授权

US06326851B1 Digital phase-domain PLL frequency synthesizer 有权
标题翻译：数字相域PLL频率合成器
公开(公告)号：US06326851B1
公开(公告)日：2001-12-04
申请号：US09603023
申请日：2000-06-26
申请人： Robert B. Staszewski , Dirk Leipold
发明人： Robert B. Staszewski , Dirk Leipold
IPC分类号： H03L7085
CPC分类号： H03L7/18 , H03L7/085
摘要： A frequency synthesizer architecture naturally combines transmitter modulation capability with a wideband all-digital PLL modulation scheme to maximize a digitally-intensive implementation by operating in a synchronous phase-domain. Synchronous logic is provided across a digitally controlled VCO and is synchronous to the VCO output clock by implementing a timing adjustment in association with a reference calculation to allow a frequency control word to contain both channel information and transmit modulation information.
摘要翻译：频率合成器架构自然地将发射机调制能力与宽带全数字PLL调制方案相结合，以通过在同步相域中操作来最大化数字密集型实现。通过实施与参考计算相关联的定时调整，跨数字控制VCO提供同步逻辑，并且与VCO输出时钟同步，以允许频率控制字包含信道信息和发送调制信息。

60. 发明授权

US08385476B2 Digital phase locked loop 有权
公开(公告)号：US08385476B2
公开(公告)日：2013-02-26
申请号：US10131523
申请日：2002-04-24
申请人： Robert B. Staszewski , Dirk Leipold
发明人： Robert B. Staszewski , Dirk Leipold
IPC分类号： H03D1/00 , H04L27/06
CPC分类号： H03L7/0992 , H03C3/0966 , H03K19/0016 , H03L7/08 , H03L7/085 , H03L7/087 , H03L7/091 , H03L7/093 , H03L7/099 , H03L7/0991 , H03L7/16 , H03L2207/50 , H04L7/0029 , H04L7/0331
摘要： A phase locked loop circuit (30, 100, 110) includes a controllable oscillator (42) for generating an output signal of desired frequency responsive to a control signal, a first phase detection circuit (32, 102, 112) for generating an output indicative of phase differential responsive to the output signal and a first edge of a reference signal and a second phase detection circuit (34, 104, 114) for generating an output indicative of phase differential responsive to the output signal and a second edge of a reference signal. The control signal to the controllable oscillator (42) is driven by the outputs of the first and second phase detections circuits.

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